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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [component/] [Actel/] [DirectCore/] [CoreAHBLite/] [5.3.101/] [rtl/] [vhdl/] [core/] [coreahblite_slavestage.vhd] - Blame information for rev 3

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-- ********************************************************************/
-- Actel Corporation Proprietary and Confidential
-- Copyright 2013 Actel Corporation.  All rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
--
-- Description: CoreAHBLite slave stage logic for
--                              matrix (4 masters by 16 slaves),
--                              instantiates the following modules:
--                              COREAHBLITE_SLAVEARBITER
--
--
-- SVN Revision Information:
-- SVN $Revision: 23120 $
-- SVN $Date: 2014-07-17 19:56:23 +0530 (Thu, 17 Jul 2014) $
--
--
-- *********************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity COREAHBLITE_SLAVESTAGE is
    generic(SYNC_RESET      : integer := 0);
    port (
        HCLK                 : in std_logic;
        HRESETN              : in std_logic;
        HREADYOUT            : in std_logic;
        HRESP                : in std_logic;
        HSEL                 : out std_logic;
        HADDR                : out std_logic_vector(31 downto 0);
        HSIZE                : out std_logic_vector(2 downto 0);
        HTRANS               : out std_logic;
        HWRITE               : out std_logic;
        HWDATA               : out std_logic_vector(31 downto 0);
        HREADY_S             : out std_logic;
        HMASTLOCK            : out std_logic;
        MADDRSEL             : in std_logic_vector(3 downto 0);
        MDATASEL             : in std_logic_vector(3 downto 0);
        MPREVDATASLAVEREADY  : in std_logic_vector(3 downto 0);
        MADDRREADY           : out std_logic_vector(3 downto 0);
        MDATAREADY           : out std_logic_vector(3 downto 0);
        MHRESP               : out std_logic_vector(3 downto 0);
        M0GATEDHADDR         : in std_logic_vector(31 downto 0);
        M0GATEDHMASTLOCK     : in std_logic;
        M0GATEDHSIZE         : in std_logic_vector(2 downto 0);
        M0GATEDHTRANS        : in std_logic;
        M0GATEDHWRITE        : in std_logic;
        M1GATEDHADDR         : in std_logic_vector(31 downto 0);
        M1GATEDHMASTLOCK     : in std_logic;
        M1GATEDHSIZE         : in std_logic_vector(2 downto 0);
        M1GATEDHTRANS        : in std_logic;
        M1GATEDHWRITE        : in std_logic;
        M2GATEDHADDR         : in std_logic_vector(31 downto 0);
        M2GATEDHMASTLOCK     : in std_logic;
        M2GATEDHSIZE         : in std_logic_vector(2 downto 0);
        M2GATEDHTRANS        : in std_logic;
        M2GATEDHWRITE        : in std_logic;
        M3GATEDHADDR         : in std_logic_vector(31 downto 0);
        M3GATEDHMASTLOCK     : in std_logic;
        M3GATEDHSIZE         : in std_logic_vector(2 downto 0);
        M3GATEDHTRANS        : in std_logic;
        M3GATEDHWRITE        : in std_logic;
        HWDATA_M0            : in std_logic_vector(31 downto 0);
        HWDATA_M1            : in std_logic_vector(31 downto 0);
        HWDATA_M2            : in std_logic_vector(31 downto 0);
        HWDATA_M3            : in std_logic_vector(31 downto 0)
    );
end entity COREAHBLITE_SLAVESTAGE;
 
architecture trans of COREAHBLITE_SLAVESTAGE is
 
 
function or_v (
    v : std_logic_vector) return std_logic is
    variable sl : std_logic := '0';
begin
    for i in v'range loop
       sl := sl or v(i);
    end loop;
    return(sl);
end or_v;
 
constant TRN_IDLE       : std_logic := '0';
constant MASTER_NONE    : std_logic_vector(3 downto 0) := "0000";
 
 
    component COREAHBLITE_SLAVEARBITER is
            generic(SYNC_RESET   : integer := 0);
        port (
            HCLK                 : in std_logic;
            HRESETN              : in std_logic;
            MADDRSEL             : in std_logic_vector(3 downto 0);
            ADDRPHEND            : in std_logic;
            M0GATEDHMASTLOCK     : in std_logic;
            M1GATEDHMASTLOCK     : in std_logic;
            M2GATEDHMASTLOCK     : in std_logic;
            M3GATEDHMASTLOCK     : in std_logic;
            MASTERADDRINPROG     : out std_logic_vector(3 downto 0)
        );
    end component;
 
    signal masterAddrInProg           : std_logic_vector(3 downto 0);
    signal masterDataInProg           : std_logic_vector(3 downto 0);
    signal addrPhMasterHREADY         : std_logic;
    signal addrPhMasterDataPhComplete : std_logic;
    signal preHTRANS                  : std_logic;
 
    -- Declare intermediate signals for referenced outputs
    signal HREADY_S_xhdl0             : std_logic;
    signal aresetn                : std_logic;
    signal sresetn                : std_logic;
 
begin
    aresetn <= '1' WHEN (SYNC_RESET=1) ELSE HRESETN;
    sresetn <= HRESETN WHEN (SYNC_RESET=1) ELSE '1';
    -- Drive referenced outputs
    HREADY_S <= HREADY_S_xhdl0;
    process (HCLK, aresetn)
    begin
        if ((not(aresetn)) = '1') then
            masterDataInProg <= MASTER_NONE;
        elsif (HCLK'event and HCLK = '1') then
            if ((not(sresetn)) = '1') then
                masterDataInProg <= MASTER_NONE;
                    else
                if (HREADY_S_xhdl0 = '1') then
                    masterDataInProg <= masterAddrInProg;
                end if;
            end if;
        end if;
    end process;
 
 
 
    slave_arbiter : COREAHBLITE_SLAVEARBITER
                generic map(SYNC_RESET => SYNC_RESET)
        port map (
            HCLK              => HCLK,
            HRESETN           => HRESETN,
            MADDRSEL          => MADDRSEL,
            ADDRPHEND         => HREADY_S_xhdl0,
            M0GATEDHMASTLOCK  => M0GATEDHMASTLOCK,
            M1GATEDHMASTLOCK  => M1GATEDHMASTLOCK,
            M2GATEDHMASTLOCK  => M2GATEDHMASTLOCK,
            M3GATEDHMASTLOCK  => M3GATEDHMASTLOCK,
            MASTERADDRINPROG  => masterAddrInProg
        );
    process (masterAddrInProg,
             M0GATEDHTRANS, M0GATEDHSIZE, M0GATEDHWRITE, M0GATEDHADDR, M0GATEDHMASTLOCK,
             M1GATEDHTRANS, M1GATEDHSIZE, M1GATEDHWRITE, M1GATEDHADDR, M1GATEDHMASTLOCK,
             M2GATEDHTRANS, M2GATEDHSIZE, M2GATEDHWRITE, M2GATEDHADDR, M2GATEDHMASTLOCK,
             M3GATEDHTRANS, M3GATEDHSIZE, M3GATEDHWRITE, M3GATEDHADDR, M3GATEDHMASTLOCK,
             MPREVDATASLAVEREADY)
    begin
        case masterAddrInProg is
            when "0001" =>
                HSEL <= '1';
                preHTRANS <= M0GATEDHTRANS;
                HSIZE <= M0GATEDHSIZE;
                HWRITE <= M0GATEDHWRITE;
                HADDR <= M0GATEDHADDR;
                HMASTLOCK <= M0GATEDHMASTLOCK;
                addrPhMasterHREADY <= MPREVDATASLAVEREADY(0);
            when "0010" =>
                HSEL <= '1';
                preHTRANS <= M1GATEDHTRANS;
                HSIZE <= M1GATEDHSIZE;
                HWRITE <= M1GATEDHWRITE;
                HADDR <= M1GATEDHADDR;
                HMASTLOCK <= M1GATEDHMASTLOCK;
                addrPhMasterHREADY <= MPREVDATASLAVEREADY(1);
            when "0100" =>
                HSEL <= '1';
                preHTRANS <= M2GATEDHTRANS;
                HSIZE <= M2GATEDHSIZE;
                HWRITE <= M2GATEDHWRITE;
                HADDR <= M2GATEDHADDR;
                HMASTLOCK <= M2GATEDHMASTLOCK;
                addrPhMasterHREADY <= MPREVDATASLAVEREADY(2);
            when "1000" =>
                HSEL <= '1';
                preHTRANS <= M3GATEDHTRANS;
                HSIZE <= M3GATEDHSIZE;
                HWRITE <= M3GATEDHWRITE;
                HADDR <= M3GATEDHADDR;
                HMASTLOCK <= M3GATEDHMASTLOCK;
                addrPhMasterHREADY <= MPREVDATASLAVEREADY(3);
            when others =>
                HSEL <= '0';
                preHTRANS <= TRN_IDLE;
                HSIZE <= "000";
                HWRITE <= '0';
                HADDR <= "00000000000000000000000000000000";
                HMASTLOCK <= '0';
                addrPhMasterHREADY <= '1';
        end case;
    end process;
 
    addrPhMasterDataPhComplete <= or_v((masterAddrInProg and MDATASEL));
    HTRANS <= preHTRANS and (addrPhMasterHREADY or addrPhMasterDataPhComplete);
    HREADY_S_xhdl0 <= HREADYOUT;
    process (masterDataInProg, HWDATA_M0, HWDATA_M1, HWDATA_M2, HWDATA_M3)
    begin
        case masterDataInProg is
            when "0001" =>
                HWDATA <= HWDATA_M0;
            when "0010" =>
                HWDATA <= HWDATA_M1;
            when "0100" =>
                HWDATA <= HWDATA_M2;
            when "1000" =>
                HWDATA <= HWDATA_M3;
            when others =>
                HWDATA <= "00000000000000000000000000000000";
        end case;
    end process;
 
    process (masterDataInProg, HRESP)
    begin
        MHRESP <= "0000";
        case masterDataInProg is
            when "0001" =>
                MHRESP(0) <= HRESP;
            when "0010" =>
                MHRESP(1) <= HRESP;
            when "0100" =>
                MHRESP(2) <= HRESP;
            when "1000" =>
                MHRESP(3) <= HRESP;
            when others =>
                MHRESP <= "0000";
        end case;
    end process;
 
    process (MADDRSEL, masterAddrInProg, HREADYOUT)
    begin
        if ((MADDRSEL(0) and not(masterAddrInProg(0))) = '1') then
            MADDRREADY(0) <= '0';
        elsif ((MADDRSEL(0) and masterAddrInProg(0)) = '1') then
            MADDRREADY(0) <= HREADYOUT;
        else
            MADDRREADY(0) <= '1';
        end if;
    end process;
 
    process (MADDRSEL, masterAddrInProg, HREADYOUT)
    begin
        if ((MADDRSEL(1) and not(masterAddrInProg(1))) = '1') then
            MADDRREADY(1) <= '0';
        elsif ((MADDRSEL(1) and masterAddrInProg(1)) = '1') then
            MADDRREADY(1) <= HREADYOUT;
        else
            MADDRREADY(1) <= '1';
        end if;
    end process;
 
    process (MADDRSEL, masterAddrInProg, HREADYOUT)
    begin
        if ((MADDRSEL(2) and not(masterAddrInProg(2))) = '1') then
            MADDRREADY(2) <= '0';
        elsif ((MADDRSEL(2) and masterAddrInProg(2)) = '1') then
            MADDRREADY(2) <= HREADYOUT;
        else
            MADDRREADY(2) <= '1';
        end if;
    end process;
 
    process (MADDRSEL, masterAddrInProg, HREADYOUT)
    begin
        if ((MADDRSEL(3) and not(masterAddrInProg(3))) = '1') then
            MADDRREADY(3) <= '0';
        elsif ((MADDRSEL(3) and masterAddrInProg(3)) = '1') then
            MADDRREADY(3) <= HREADYOUT;
        else
            MADDRREADY(3) <= '1';
        end if;
    end process;
 
    process (MDATASEL, masterDataInProg, HREADYOUT)
    begin
        if ((MDATASEL(0) and not(masterDataInProg(0))) = '1') then
            MDATAREADY(0) <= '0';
        elsif ((MDATASEL(0) and masterDataInProg(0)) = '1') then
            MDATAREADY(0) <= HREADYOUT;
        else
            MDATAREADY(0) <= '1';
        end if;
    end process;
 
    process (MDATASEL, masterDataInProg, HREADYOUT)
    begin
        if ((MDATASEL(1) and not(masterDataInProg(1))) = '1') then
            MDATAREADY(1) <= '0';
        elsif ((MDATASEL(1) and masterDataInProg(1)) = '1') then
            MDATAREADY(1) <= HREADYOUT;
        else
            MDATAREADY(1) <= '1';
        end if;
    end process;
 
    process (MDATASEL, masterDataInProg, HREADYOUT)
    begin
        if ((MDATASEL(2) and not(masterDataInProg(2))) = '1') then
            MDATAREADY(2) <= '0';
        elsif ((MDATASEL(2) and masterDataInProg(2)) = '1') then
            MDATAREADY(2) <= HREADYOUT;
        else
            MDATAREADY(2) <= '1';
        end if;
    end process;
 
    process (MDATASEL, masterDataInProg, HREADYOUT)
    begin
        if ((MDATASEL(3) and not(masterDataInProg(3))) = '1') then
            MDATAREADY(3) <= '0';
        elsif ((MDATASEL(3) and masterDataInProg(3)) = '1') then
            MDATAREADY(3) <= HREADYOUT;
        else
            MDATAREADY(3) <= '1';
        end if;
    end process;
 
end architecture trans;

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Subversion Repositories ahbmaster

[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [component/] [Actel/] [DirectCore/] [CoreAHBLite/] [5.3.101/] [rtl/] [vhdl/] [core/] [coreahblite_slavestage.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	uson	`-- ********************************************************************/`
2			`-- Actel Corporation Proprietary and Confidential`
3			`-- Copyright 2013 Actel Corporation. All rights reserved.`
4			`--`
5			`-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN`
6			`-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED`
7			`-- IN ADVANCE IN WRITING.`
8			`--`
9			`-- Description: CoreAHBLite slave stage logic for`
10			`-- matrix (4 masters by 16 slaves),`
11			`-- instantiates the following modules:`
12			`-- COREAHBLITE_SLAVEARBITER`
13			`--`
14			`--`
15			`-- SVN Revision Information:`
16			`-- SVN $Revision: 23120 $`
17			`-- SVN $Date: 2014-07-17 19:56:23 +0530 (Thu, 17 Jul 2014) $`
18			`--`
19			`--`
20			`-- *********************************************************************/`
21			`library ieee;`
22			`use ieee.std_logic_1164.all;`
23			`use ieee.numeric_std.all;`
24			`entity COREAHBLITE_SLAVESTAGE is`
25			`generic(SYNC_RESET : integer := 0);`
26			`port (`
27			`HCLK : in std_logic;`
28			`HRESETN : in std_logic;`
29			`HREADYOUT : in std_logic;`
30			`HRESP : in std_logic;`
31			`HSEL : out std_logic;`
32			`HADDR : out std_logic_vector(31 downto 0);`
33			`HSIZE : out std_logic_vector(2 downto 0);`
34			`HTRANS : out std_logic;`
35			`HWRITE : out std_logic;`
36			`HWDATA : out std_logic_vector(31 downto 0);`
37			`HREADY_S : out std_logic;`
38			`HMASTLOCK : out std_logic;`
39			`MADDRSEL : in std_logic_vector(3 downto 0);`
40			`MDATASEL : in std_logic_vector(3 downto 0);`
41			`MPREVDATASLAVEREADY : in std_logic_vector(3 downto 0);`
42			`MADDRREADY : out std_logic_vector(3 downto 0);`
43			`MDATAREADY : out std_logic_vector(3 downto 0);`
44			`MHRESP : out std_logic_vector(3 downto 0);`
45			`M0GATEDHADDR : in std_logic_vector(31 downto 0);`
46			`M0GATEDHMASTLOCK : in std_logic;`
47			`M0GATEDHSIZE : in std_logic_vector(2 downto 0);`
48			`M0GATEDHTRANS : in std_logic;`
49			`M0GATEDHWRITE : in std_logic;`
50			`M1GATEDHADDR : in std_logic_vector(31 downto 0);`
51			`M1GATEDHMASTLOCK : in std_logic;`
52			`M1GATEDHSIZE : in std_logic_vector(2 downto 0);`
53			`M1GATEDHTRANS : in std_logic;`
54			`M1GATEDHWRITE : in std_logic;`
55			`M2GATEDHADDR : in std_logic_vector(31 downto 0);`
56			`M2GATEDHMASTLOCK : in std_logic;`
57			`M2GATEDHSIZE : in std_logic_vector(2 downto 0);`
58			`M2GATEDHTRANS : in std_logic;`
59			`M2GATEDHWRITE : in std_logic;`
60			`M3GATEDHADDR : in std_logic_vector(31 downto 0);`
61			`M3GATEDHMASTLOCK : in std_logic;`
62			`M3GATEDHSIZE : in std_logic_vector(2 downto 0);`
63			`M3GATEDHTRANS : in std_logic;`
64			`M3GATEDHWRITE : in std_logic;`
65			`HWDATA_M0 : in std_logic_vector(31 downto 0);`
66			`HWDATA_M1 : in std_logic_vector(31 downto 0);`
67			`HWDATA_M2 : in std_logic_vector(31 downto 0);`
68			`HWDATA_M3 : in std_logic_vector(31 downto 0)`
69			`);`
70			`end entity COREAHBLITE_SLAVESTAGE;`
71
72			`architecture trans of COREAHBLITE_SLAVESTAGE is`
73
74
75			`function or_v (`
76			`v : std_logic_vector) return std_logic is`
77			`variable sl : std_logic := '0';`
78			`begin`
79			`for i in v'range loop`
80			`sl := sl or v(i);`
81			`end loop;`
82			`return(sl);`
83			`end or_v;`
84
85			`constant TRN_IDLE : std_logic := '0';`
86			`constant MASTER_NONE : std_logic_vector(3 downto 0) := "0000";`
87
88
89			`component COREAHBLITE_SLAVEARBITER is`
90			`generic(SYNC_RESET : integer := 0);`
91			`port (`
92			`HCLK : in std_logic;`
93			`HRESETN : in std_logic;`
94			`MADDRSEL : in std_logic_vector(3 downto 0);`
95			`ADDRPHEND : in std_logic;`
96			`M0GATEDHMASTLOCK : in std_logic;`
97			`M1GATEDHMASTLOCK : in std_logic;`
98			`M2GATEDHMASTLOCK : in std_logic;`
99			`M3GATEDHMASTLOCK : in std_logic;`
100			`MASTERADDRINPROG : out std_logic_vector(3 downto 0)`
101			`);`
102			`end component;`
103
104			`signal masterAddrInProg : std_logic_vector(3 downto 0);`
105			`signal masterDataInProg : std_logic_vector(3 downto 0);`
106			`signal addrPhMasterHREADY : std_logic;`
107			`signal addrPhMasterDataPhComplete : std_logic;`
108			`signal preHTRANS : std_logic;`
109
110			`-- Declare intermediate signals for referenced outputs`
111			`signal HREADY_S_xhdl0 : std_logic;`
112			`signal aresetn : std_logic;`
113			`signal sresetn : std_logic;`
114
115			`begin`
116			`aresetn <= '1' WHEN (SYNC_RESET=1) ELSE HRESETN;`
117			`sresetn <= HRESETN WHEN (SYNC_RESET=1) ELSE '1';`
118			`-- Drive referenced outputs`
119			`HREADY_S <= HREADY_S_xhdl0;`
120			`process (HCLK, aresetn)`
121			`begin`
122			`if ((not(aresetn)) = '1') then`
123			`masterDataInProg <= MASTER_NONE;`
124			`elsif (HCLK'event and HCLK = '1') then`
125			`if ((not(sresetn)) = '1') then`
126			`masterDataInProg <= MASTER_NONE;`
127			`else`
128			`if (HREADY_S_xhdl0 = '1') then`
129			`masterDataInProg <= masterAddrInProg;`
130			`end if;`
131			`end if;`
132			`end if;`
133			`end process;`
134
135
136
137			`slave_arbiter : COREAHBLITE_SLAVEARBITER`
138			`generic map(SYNC_RESET => SYNC_RESET)`
139			`port map (`
140			`HCLK => HCLK,`
141			`HRESETN => HRESETN,`
142			`MADDRSEL => MADDRSEL,`
143			`ADDRPHEND => HREADY_S_xhdl0,`
144			`M0GATEDHMASTLOCK => M0GATEDHMASTLOCK,`
145			`M1GATEDHMASTLOCK => M1GATEDHMASTLOCK,`
146			`M2GATEDHMASTLOCK => M2GATEDHMASTLOCK,`
147			`M3GATEDHMASTLOCK => M3GATEDHMASTLOCK,`
148			`MASTERADDRINPROG => masterAddrInProg`
149			`);`
150			`process (masterAddrInProg,`
151			`M0GATEDHTRANS, M0GATEDHSIZE, M0GATEDHWRITE, M0GATEDHADDR, M0GATEDHMASTLOCK,`
152			`M1GATEDHTRANS, M1GATEDHSIZE, M1GATEDHWRITE, M1GATEDHADDR, M1GATEDHMASTLOCK,`
153			`M2GATEDHTRANS, M2GATEDHSIZE, M2GATEDHWRITE, M2GATEDHADDR, M2GATEDHMASTLOCK,`
154			`M3GATEDHTRANS, M3GATEDHSIZE, M3GATEDHWRITE, M3GATEDHADDR, M3GATEDHMASTLOCK,`
155			`MPREVDATASLAVEREADY)`
156			`begin`
157			`case masterAddrInProg is`
158			`when "0001" =>`
159			`HSEL <= '1';`
160			`preHTRANS <= M0GATEDHTRANS;`
161			`HSIZE <= M0GATEDHSIZE;`
162			`HWRITE <= M0GATEDHWRITE;`
163			`HADDR <= M0GATEDHADDR;`
164			`HMASTLOCK <= M0GATEDHMASTLOCK;`
165			`addrPhMasterHREADY <= MPREVDATASLAVEREADY(0);`
166			`when "0010" =>`
167			`HSEL <= '1';`
168			`preHTRANS <= M1GATEDHTRANS;`
169			`HSIZE <= M1GATEDHSIZE;`
170			`HWRITE <= M1GATEDHWRITE;`
171			`HADDR <= M1GATEDHADDR;`
172			`HMASTLOCK <= M1GATEDHMASTLOCK;`
173			`addrPhMasterHREADY <= MPREVDATASLAVEREADY(1);`
174			`when "0100" =>`
175			`HSEL <= '1';`
176			`preHTRANS <= M2GATEDHTRANS;`
177			`HSIZE <= M2GATEDHSIZE;`
178			`HWRITE <= M2GATEDHWRITE;`
179			`HADDR <= M2GATEDHADDR;`
180			`HMASTLOCK <= M2GATEDHMASTLOCK;`
181			`addrPhMasterHREADY <= MPREVDATASLAVEREADY(2);`
182			`when "1000" =>`
183			`HSEL <= '1';`
184			`preHTRANS <= M3GATEDHTRANS;`
185			`HSIZE <= M3GATEDHSIZE;`
186			`HWRITE <= M3GATEDHWRITE;`
187			`HADDR <= M3GATEDHADDR;`
188			`HMASTLOCK <= M3GATEDHMASTLOCK;`
189			`addrPhMasterHREADY <= MPREVDATASLAVEREADY(3);`
190			`when others =>`
191			`HSEL <= '0';`
192			`preHTRANS <= TRN_IDLE;`
193			`HSIZE <= "000";`
194			`HWRITE <= '0';`
195			`HADDR <= "00000000000000000000000000000000";`
196			`HMASTLOCK <= '0';`
197			`addrPhMasterHREADY <= '1';`
198			`end case;`
199			`end process;`
200
201			`addrPhMasterDataPhComplete <= or_v((masterAddrInProg and MDATASEL));`
202			`HTRANS <= preHTRANS and (addrPhMasterHREADY or addrPhMasterDataPhComplete);`
203			`HREADY_S_xhdl0 <= HREADYOUT;`
204			`process (masterDataInProg, HWDATA_M0, HWDATA_M1, HWDATA_M2, HWDATA_M3)`
205			`begin`
206			`case masterDataInProg is`
207			`when "0001" =>`
208			`HWDATA <= HWDATA_M0;`
209			`when "0010" =>`
210			`HWDATA <= HWDATA_M1;`
211			`when "0100" =>`
212			`HWDATA <= HWDATA_M2;`
213			`when "1000" =>`
214			`HWDATA <= HWDATA_M3;`
215			`when others =>`
216			`HWDATA <= "00000000000000000000000000000000";`
217			`end case;`
218			`end process;`
219
220			`process (masterDataInProg, HRESP)`
221			`begin`
222			`MHRESP <= "0000";`
223			`case masterDataInProg is`
224			`when "0001" =>`
225			`MHRESP(0) <= HRESP;`
226			`when "0010" =>`
227			`MHRESP(1) <= HRESP;`
228			`when "0100" =>`
229			`MHRESP(2) <= HRESP;`
230			`when "1000" =>`
231			`MHRESP(3) <= HRESP;`
232			`when others =>`
233			`MHRESP <= "0000";`
234			`end case;`
235			`end process;`
236
237			`process (MADDRSEL, masterAddrInProg, HREADYOUT)`
238			`begin`
239			`if ((MADDRSEL(0) and not(masterAddrInProg(0))) = '1') then`
240			`MADDRREADY(0) <= '0';`
241			`elsif ((MADDRSEL(0) and masterAddrInProg(0)) = '1') then`
242			`MADDRREADY(0) <= HREADYOUT;`
243			`else`
244			`MADDRREADY(0) <= '1';`
245			`end if;`
246			`end process;`
247
248			`process (MADDRSEL, masterAddrInProg, HREADYOUT)`
249			`begin`
250			`if ((MADDRSEL(1) and not(masterAddrInProg(1))) = '1') then`
251			`MADDRREADY(1) <= '0';`
252			`elsif ((MADDRSEL(1) and masterAddrInProg(1)) = '1') then`
253			`MADDRREADY(1) <= HREADYOUT;`
254			`else`
255			`MADDRREADY(1) <= '1';`
256			`end if;`
257			`end process;`
258
259			`process (MADDRSEL, masterAddrInProg, HREADYOUT)`
260			`begin`
261			`if ((MADDRSEL(2) and not(masterAddrInProg(2))) = '1') then`
262			`MADDRREADY(2) <= '0';`
263			`elsif ((MADDRSEL(2) and masterAddrInProg(2)) = '1') then`
264			`MADDRREADY(2) <= HREADYOUT;`
265			`else`
266			`MADDRREADY(2) <= '1';`
267			`end if;`
268			`end process;`
269
270			`process (MADDRSEL, masterAddrInProg, HREADYOUT)`
271			`begin`
272			`if ((MADDRSEL(3) and not(masterAddrInProg(3))) = '1') then`
273			`MADDRREADY(3) <= '0';`
274			`elsif ((MADDRSEL(3) and masterAddrInProg(3)) = '1') then`
275			`MADDRREADY(3) <= HREADYOUT;`
276			`else`
277			`MADDRREADY(3) <= '1';`
278			`end if;`
279			`end process;`
280
281			`process (MDATASEL, masterDataInProg, HREADYOUT)`
282			`begin`
283			`if ((MDATASEL(0) and not(masterDataInProg(0))) = '1') then`
284			`MDATAREADY(0) <= '0';`
285			`elsif ((MDATASEL(0) and masterDataInProg(0)) = '1') then`
286			`MDATAREADY(0) <= HREADYOUT;`
287			`else`
288			`MDATAREADY(0) <= '1';`
289			`end if;`
290			`end process;`
291
292			`process (MDATASEL, masterDataInProg, HREADYOUT)`
293			`begin`
294			`if ((MDATASEL(1) and not(masterDataInProg(1))) = '1') then`
295			`MDATAREADY(1) <= '0';`
296			`elsif ((MDATASEL(1) and masterDataInProg(1)) = '1') then`
297			`MDATAREADY(1) <= HREADYOUT;`
298			`else`
299			`MDATAREADY(1) <= '1';`
300			`end if;`
301			`end process;`
302
303			`process (MDATASEL, masterDataInProg, HREADYOUT)`
304			`begin`
305			`if ((MDATASEL(2) and not(masterDataInProg(2))) = '1') then`
306			`MDATAREADY(2) <= '0';`
307			`elsif ((MDATASEL(2) and masterDataInProg(2)) = '1') then`
308			`MDATAREADY(2) <= HREADYOUT;`
309			`else`
310			`MDATAREADY(2) <= '1';`
311			`end if;`
312			`end process;`
313
314			`process (MDATASEL, masterDataInProg, HREADYOUT)`
315			`begin`
316			`if ((MDATASEL(3) and not(masterDataInProg(3))) = '1') then`
317			`MDATAREADY(3) <= '0';`
318			`elsif ((MDATASEL(3) and masterDataInProg(3)) = '1') then`
319			`MDATAREADY(3) <= HREADYOUT;`
320			`else`
321			`MDATAREADY(3) <= '1';`
322			`end if;`
323			`end process;`
324
325			`end architecture trans;`