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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [component/] [Actel/] [DirectCore/] [CoreAPB/] [1.1.101/] [rtl/] [vhdl/] [o/] [CoreAPB.vhd] - Blame information for rev 3

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library IEEe;
use IEEE.std_lOGIC_1164.all;
entity COREAPB is
generic (APBSLOT0Enable: inTEGER := 1;
APBSLOT1Enable: integer := 1;
ApbSlot2EnaBLE: intEGER := 1;
ApbSlOT3ENABLe: INTEGer := 1;
APBSLOT4Enable: INteger := 1;
APBSLOT5Enable: Integer := 1;
ApbSlot6ENABLE: INTEGER := 1;
APBSLOt7Enable: Integer := 1;
ApbSlot8EnABLE: inTEGER := 1;
ApbSlot9ENABLE: intEGER := 1;
ApbSLOT10Enable: INTeger := 1;
APbSlot11EnabLE: inteGER := 1;
ApbSLOT12ENable: Integer := 1;
APBSlot13Enable: integer := 1;
ApbSlot14ENABLE: INTEGER := 1;
ApbSlot15EnABLE: inTEGER := 1); port (PADDR: in STD_Logic_vector(23 downto 0);
PWRITE: in std_logic;
PENABLE: in std_logIC;
PWDATA: in STD_LOgic_vector(31 downto 0);
PRDATA: out STD_logic_vectOR(31 downto 0);
PSELECT: in STD_logic_vectOR(15 downto 0);
PADDRS: out stD_LOGIC_vector(23 downto 0);
PWRITES: out STD_logic;
PENABLES: out STD_Logic;
PWDATAS: out std_LOGIC_VEctor(31 downto 0);
PSELS0: out std_logic;
PSELS1: out std_logic;
PSELS2: out STD_LOGic;
PSELS3: out STD_logic;
PSELS4: out STD_Logic;
PSELS5: out std_lOGIC;
PSELS6: out STD_LOgic;
PSELS7: out Std_logic;
PSELS8: out std_logic;
PSELS9: out STD_logic;
PSELS10: out std_logic;
PSELS11: out std_LOGIC;
PSELS12: out std_logiC;
PSELS13: out STD_LOGIc;
PSELS14: out std_loGIC;
PSELS15: out stD_LOGIC;
PRDATAS0: in std_lOGIC_VECtor(31 downto 0);
PRDATAS1: in std_logic_veCTOR(31 downto 0);
PRDATAS2: in sTD_LOGIC_vector(31 downto 0);
PRDATAS3: in STD_LOGic_vector(31 downto 0);
PRDATAS4: in STD_LOGIc_vector(31 downto 0);
PRDATAS5: in STD_LOGIc_vector(31 downto 0);
PRDATAS6: in STD_Logic_vectoR(31 downto 0);
PRDATAS7: in STD_LOgic_vector(31 downto 0);
PRDATAS8: in std_logIC_VECTor(31 downto 0);
PRDATAS9: in std_logic_VECTOR(31 downto 0);
PRDATAS10: in std_logIC_VECTOr(31 downto 0);
PRDATAS11: in Std_logic_vECTOR(31 downto 0);
PRDATAS12: in STD_logic_vectOR(31 downto 0);
PRDATAS13: in STD_LOGic_vector(31 downto 0);
PRDATAS14: in sTD_LOGIC_vector(31 downto 0);
PRDATAS15: in STD_logic_vectoR(31 downto 0));
end CoreAPB;
 
architecture CoreAPB_O of CoreAPB is
 
component CoreAPB_L
port (PSELS0: in STD_logic;
PSELS1: in STD_LOGIc;
PSELS2: in std_logic;
PSELS3: in STD_logic;
PSELS4: in STD_logic;
PSELS5: in stD_LOGIC;
PSELS6: in std_logIC;
PSELS7: in std_logic;
PSELS8: in std_logic;
PSELS9: in Std_logic;
PSELS10: in STD_logic;
PSELS11: in std_logic;
PSELS12: in std_logIC;
PSELS13: in std_logiC;
PSELS14: in STD_logic;
PSELS15: in STD_LOGic;
PRDATAS0: in std_LOGIC_vector(31 downto 0);
PRDATAS1: in std_logic_vECTOR(31 downto 0);
PRDATAS2: in STD_LOGic_vector(31 downto 0);
PRDATAS3: in std_logic_VECTOR(31 downto 0);
PRDATAS4: in std_loGIC_VECTor(31 downto 0);
PRDATAS5: in STD_logic_vectOR(31 downto 0);
PRDATAS6: in STD_logic_vectOR(31 downto 0);
PRDATAS7: in stD_LOGIC_vector(31 downto 0);
PRDATAS8: in STD_logic_vectOR(31 downto 0);
PRDATAS9: in stD_LOGIC_vector(31 downto 0);
PRDATAS10: in std_logic_VECTOR(31 downto 0);
PRDATAS11: in STD_logic_vectOR(31 downto 0);
PRDATAS12: in Std_logic_veCTOR(31 downto 0);
PRDATAS13: in STd_logic_veCTOR(31 downto 0);
PRDATAS14: in std_logic_VECTOR(31 downto 0);
PRDATAS15: in STD_LOGic_vector(31 downto 0);
PRDATA: out STD_logic_vectOR(31 downto 0));
end component;
 
signal COREAPB_i: sTD_LOGic_vector(31 downto 0);
 
signal COREAPB_ol: stD_LOGIC_vector(31 downto 0);
 
signal COREAPB_ll: sTD_LOGIC_vector(31 downto 0);
 
signal CoreAPB_il: STD_LOgic_vector(31 downto 0);
 
signal COREAPB_oi: std_LOGIC_VEctor(31 downto 0);
 
signal CoreAPB_LI: std_logic_vECTOR(31 downto 0);
 
signal COREAPB_ii: sTD_LOGIC_vector(31 downto 0);
 
signal COREAPB_o0: std_lOGIC_VEctor(31 downto 0);
 
signal COREAPB_l0: sTD_LOGIC_vector(31 downto 0);
 
signal CoreAPB_i0: STD_Logic_vector(31 downto 0);
 
signal CoREAPB_O1: stD_LOGIC_vector(31 downto 0);
 
signal CoreAPB_l1: STD_logic_vectOR(31 downto 0);
 
signal COREAPB_i1: std_logIC_VECTOr(31 downto 0);
 
signal CoREAPB_OOl: std_logIC_VECTOr(31 downto 0);
 
signal CoreAPB_lol: STD_logic_vecTOR(31 downto 0);
 
signal CoreAPB_ioL: STD_logic_vectOR(31 downto 0);
 
signal CoREAPB_Oll: std_LOGIC_VEctor(31 downto 0);
 
begin
CoreAPB_olL <= ( others => '0');
PADDRS <= PADDR;
PWRITES <= PWRITE;
PENABLES <= PENABLE;
PWDATAS <= PWDATA;
PSELS0 <= PSELECT(0);
PSELS1 <= PSELECT(1);
PSELS2 <= PSELECT(2);
PSELS3 <= PSELECT(3);
PSELS4 <= PSELECT(4);
PSELS5 <= PSELECT(5);
PSELS6 <= PSELECT(6);
PSELS7 <= PSELECT(7);
PSELS8 <= PSELECT(8);
PSELS9 <= PSELECT(9);
PSELS10 <= PSELECT(10);
PSELS11 <= PSELECT(11);
PSELS12 <= PSELECT(12);
PSELS13 <= PSELECT(13);
PSELS14 <= PSELECT(14);
PSELS15 <= PSELECT(15);
CoreAPB_LLL:
if (APBSlot0Enable = 1)
generate
begin
CoreAPB_I <= PRDATAS0;
end generate CoreAPB_llL;
CoreAPB_ilL:
if (APbSlot0EnablE = 0)
generate
begin
COREAPB_i <= COREAPB_oll;
end generate COREAPB_ill;
COReAPB_oil:
if (ApbSlot1EnaBLE = 1)
generate
begin
CoreAPB_ol <= PRDATAS1;
end generate CoreAPB_OIL;
CoreAPB_LIL:
if (APbSlot1EnablE = 0)
generate
begin
COREAPB_ol <= COREAPB_oll;
end generate COReAPB_lil;
COREAPB_iil:
if (ApbSlot2EnabLE = 1)
generate
begin
CoreAPB_ll <= PRDATAS2;
end generate COREAPB_iil;
COREAPB_o0l:
if (APBSLOT2Enable = 0)
generate
begin
COREAPB_ll <= CoreAPB_OLL;
end generate COREAPB_o0l;
COREAPB_l0l:
if (APBSlot3Enable = 1)
generate
begin
COReAPB_il <= PRDATAS3;
end generate COREAPB_l0l;
COREAPB_i0l:
if (ApBSLOT3Enable = 0)
generate
begin
CoreAPB_IL <= CoREAPB_Oll;
end generate COREAPB_i0l;
CoreAPB_O1L:
if (ApbSlot4EnaBLE = 1)
generate
begin
CoreAPB_oi <= PRDATAS4;
end generate CoreAPB_O1L;
CoreAPB_l1L:
if (ApbSlot4EnABLE = 0)
generate
begin
COReAPB_oi <= COreAPB_oll;
end generate CoreAPB_l1L;
COREAPB_i1l:
if (ApbSlot5EnaBLE = 1)
generate
begin
CoreAPB_li <= PRDATAS5;
end generate CoreAPB_i1L;
CoreAPB_ooi:
if (APBSLOT5Enable = 0)
generate
begin
CoreAPB_LI <= CoreAPB_OLL;
end generate CoreAPB_OOI;
CoreAPB_loi:
if (ApbSlot6ENABLE = 1)
generate
begin
CoreAPB_II <= PRDATAS6;
end generate CoreAPB_lOI;
CoreAPB_IOI:
if (APBSlot6Enable = 0)
generate
begin
CoreAPB_II <= CoreAPB_oLL;
end generate CoreAPB_IOI;
COREAPB_oli:
if (APbSlot7EnablE = 1)
generate
begin
COREAPB_O0 <= PRDATAS7;
end generate CoreAPB_OLI;
CoreAPB_LLI:
if (APBSLOT7Enable = 0)
generate
begin
COREAPB_o0 <= COReAPB_oll;
end generate CoreAPB_lli;
CoreAPB_ili:
if (ApbSlot8EnABLE = 1)
generate
begin
COREAPB_l0 <= PRDATAS8;
end generate COREAPB_ili;
COREAPB_oii:
if (ApbSloT8ENABLe = 0)
generate
begin
CoreAPB_l0 <= CoreAPB_oll;
end generate CoreAPB_OII;
COREAPB_lii:
if (ApbSlot9EnaBLE = 1)
generate
begin
COreAPB_i0 <= PRDATAS9;
end generate CoreAPB_liI;
CoreAPB_III:
if (APBSlot9Enable = 0)
generate
begin
CoreAPB_I0 <= CoreAPB_olL;
end generate CoreAPB_III;
CoreAPB_o0i:
if (APBSLOT10Enable = 1)
generate
begin
CorEAPB_O1 <= PRDATAS10;
end generate COReAPB_o0i;
CoreAPB_l0i:
if (APBSLOT10Enable = 0)
generate
begin
COREAPB_o1 <= COREAPB_oll;
end generate COREAPB_l0i;
CoreAPB_i0I:
if (ApbSlot11EnABLE = 1)
generate
begin
CoreAPB_l1 <= PRDATAS11;
end generate COREAPB_i0i;
COReAPB_o1i:
if (ApbSlot11ENABLE = 0)
generate
begin
COREAPB_l1 <= COREAPB_oll;
end generate COReAPB_o1i;
COREAPB_l1i:
if (ApbSlot12ENABLE = 1)
generate
begin
CoREAPB_I1 <= PRDATAS12;
end generate CoreAPB_l1I;
COREAPB_i1i:
if (APBSLOT12Enable = 0)
generate
begin
CoreAPB_I1 <= CoreAPB_olL;
end generate CoreAPB_i1I;
COReAPB_oo0:
if (APBSLOT13Enable = 1)
generate
begin
COREAPB_ool <= PRDATAS13;
end generate CoreAPB_oo0;
CoreAPB_LO0:
if (ApbSlot13ENABLE = 0)
generate
begin
CoreAPB_ool <= COREAPB_oll;
end generate CoreAPB_lo0;
COREAPB_io0:
if (APBSLOT14Enable = 1)
generate
begin
CoreAPB_LOL <= PRDATAS14;
end generate CorEAPB_IO0;
CoREAPB_Ol0:
if (ApbSlot14ENABLE = 0)
generate
begin
CoreAPB_lol <= COreAPB_oll;
end generate COreAPB_ol0;
COReAPB_ll0:
if (ApbSloT15ENABle = 1)
generate
begin
COREAPB_iol <= PRDATAS15;
end generate CoreAPB_ll0;
CoreAPB_il0:
if (ApbSlot15ENABLE = 0)
generate
begin
COREAPB_iol <= CoreAPB_OLL;
end generate CoreAPB_IL0;
COREAPB_oi0: COREAPB_l
port map (PSELS0 => PSELECT(0),
PSELS1 => PSELECT(1),
PSELS2 => PSELECT(2),
PSELS3 => PSELECT(3),
PSELS4 => PSELECT(4),
PSELS5 => PSELECT(5),
PSELS6 => PSELECT(6),
PSELS7 => PSELECT(7),
PSELS8 => PSELECT(8),
PSELS9 => PSELECT(9),
PSELS10 => PSELECT(10),
PSELS11 => PSELECT(11),
PSELS12 => PSELECT(12),
PSELS13 => PSELECT(13),
PSELS14 => PSELECT(14),
PSELS15 => PSELECT(15),
PRDATAS0 => COREAPB_i,
PRDATAS1 => COREAPB_ol,
PRDATAS2 => CoreAPB_ll,
PRDATAS3 => CoreAPB_iL,
PRDATAS4 => COREAPB_oi,
PRDATAS5 => CoreAPB_LI,
PRDATAS6 => COReAPB_ii,
PRDATAS7 => CoreAPB_O0,
PRDATAS8 => CoreAPB_l0,
PRDATAS9 => COREAPB_i0,
PRDATAS10 => COREAPB_O1,
PRDATAS11 => CoreAPB_L1,
PRDATAS12 => COREAPB_i1,
PRDATAS13 => CorEAPB_OOl,
PRDATAS14 => COReAPB_lol,
PRDATAS15 => CoreAPB_ioL,
PRDATA => PRDATA);
end COreAPB_o;

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Subversion Repositories ahbmaster

[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [component/] [Actel/] [DirectCore/] [CoreAPB/] [1.1.101/] [rtl/] [vhdl/] [o/] [CoreAPB.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	uson	`library IEEe;`
2			`use IEEE.std_lOGIC_1164.all;`
3			`entity COREAPB is`
4			`generic (APBSLOT0Enable: inTEGER := 1;`
5			`APBSLOT1Enable: integer := 1;`
6			`ApbSlot2EnaBLE: intEGER := 1;`
7			`ApbSlOT3ENABLe: INTEGer := 1;`
8			`APBSLOT4Enable: INteger := 1;`
9			`APBSLOT5Enable: Integer := 1;`
10			`ApbSlot6ENABLE: INTEGER := 1;`
11			`APBSLOt7Enable: Integer := 1;`
12			`ApbSlot8EnABLE: inTEGER := 1;`
13			`ApbSlot9ENABLE: intEGER := 1;`
14			`ApbSLOT10Enable: INTeger := 1;`
15			`APbSlot11EnabLE: inteGER := 1;`
16			`ApbSLOT12ENable: Integer := 1;`
17			`APBSlot13Enable: integer := 1;`
18			`ApbSlot14ENABLE: INTEGER := 1;`
19			`ApbSlot15EnABLE: inTEGER := 1); port (PADDR: in STD_Logic_vector(23 downto 0);`
20			`PWRITE: in std_logic;`
21			`PENABLE: in std_logIC;`
22			`PWDATA: in STD_LOgic_vector(31 downto 0);`
23			`PRDATA: out STD_logic_vectOR(31 downto 0);`
24			`PSELECT: in STD_logic_vectOR(15 downto 0);`
25			`PADDRS: out stD_LOGIC_vector(23 downto 0);`
26			`PWRITES: out STD_logic;`
27			`PENABLES: out STD_Logic;`
28			`PWDATAS: out std_LOGIC_VEctor(31 downto 0);`
29			`PSELS0: out std_logic;`
30			`PSELS1: out std_logic;`
31			`PSELS2: out STD_LOGic;`
32			`PSELS3: out STD_logic;`
33			`PSELS4: out STD_Logic;`
34			`PSELS5: out std_lOGIC;`
35			`PSELS6: out STD_LOgic;`
36			`PSELS7: out Std_logic;`
37			`PSELS8: out std_logic;`
38			`PSELS9: out STD_logic;`
39			`PSELS10: out std_logic;`
40			`PSELS11: out std_LOGIC;`
41			`PSELS12: out std_logiC;`
42			`PSELS13: out STD_LOGIc;`
43			`PSELS14: out std_loGIC;`
44			`PSELS15: out stD_LOGIC;`
45			`PRDATAS0: in std_lOGIC_VECtor(31 downto 0);`
46			`PRDATAS1: in std_logic_veCTOR(31 downto 0);`
47			`PRDATAS2: in sTD_LOGIC_vector(31 downto 0);`
48			`PRDATAS3: in STD_LOGic_vector(31 downto 0);`
49			`PRDATAS4: in STD_LOGIc_vector(31 downto 0);`
50			`PRDATAS5: in STD_LOGIc_vector(31 downto 0);`
51			`PRDATAS6: in STD_Logic_vectoR(31 downto 0);`
52			`PRDATAS7: in STD_LOgic_vector(31 downto 0);`
53			`PRDATAS8: in std_logIC_VECTor(31 downto 0);`
54			`PRDATAS9: in std_logic_VECTOR(31 downto 0);`
55			`PRDATAS10: in std_logIC_VECTOr(31 downto 0);`
56			`PRDATAS11: in Std_logic_vECTOR(31 downto 0);`
57			`PRDATAS12: in STD_logic_vectOR(31 downto 0);`
58			`PRDATAS13: in STD_LOGic_vector(31 downto 0);`
59			`PRDATAS14: in sTD_LOGIC_vector(31 downto 0);`
60			`PRDATAS15: in STD_logic_vectoR(31 downto 0));`
61			`end CoreAPB;`
62
63			`architecture CoreAPB_O of CoreAPB is`
64
65			`component CoreAPB_L`
66			`port (PSELS0: in STD_logic;`
67			`PSELS1: in STD_LOGIc;`
68			`PSELS2: in std_logic;`
69			`PSELS3: in STD_logic;`
70			`PSELS4: in STD_logic;`
71			`PSELS5: in stD_LOGIC;`
72			`PSELS6: in std_logIC;`
73			`PSELS7: in std_logic;`
74			`PSELS8: in std_logic;`
75			`PSELS9: in Std_logic;`
76			`PSELS10: in STD_logic;`
77			`PSELS11: in std_logic;`
78			`PSELS12: in std_logIC;`
79			`PSELS13: in std_logiC;`
80			`PSELS14: in STD_logic;`
81			`PSELS15: in STD_LOGic;`
82			`PRDATAS0: in std_LOGIC_vector(31 downto 0);`
83			`PRDATAS1: in std_logic_vECTOR(31 downto 0);`
84			`PRDATAS2: in STD_LOGic_vector(31 downto 0);`
85			`PRDATAS3: in std_logic_VECTOR(31 downto 0);`
86			`PRDATAS4: in std_loGIC_VECTor(31 downto 0);`
87			`PRDATAS5: in STD_logic_vectOR(31 downto 0);`
88			`PRDATAS6: in STD_logic_vectOR(31 downto 0);`
89			`PRDATAS7: in stD_LOGIC_vector(31 downto 0);`
90			`PRDATAS8: in STD_logic_vectOR(31 downto 0);`
91			`PRDATAS9: in stD_LOGIC_vector(31 downto 0);`
92			`PRDATAS10: in std_logic_VECTOR(31 downto 0);`
93			`PRDATAS11: in STD_logic_vectOR(31 downto 0);`
94			`PRDATAS12: in Std_logic_veCTOR(31 downto 0);`
95			`PRDATAS13: in STd_logic_veCTOR(31 downto 0);`
96			`PRDATAS14: in std_logic_VECTOR(31 downto 0);`
97			`PRDATAS15: in STD_LOGic_vector(31 downto 0);`
98			`PRDATA: out STD_logic_vectOR(31 downto 0));`
99			`end component;`
100
101			`signal COREAPB_i: sTD_LOGic_vector(31 downto 0);`
102
103			`signal COREAPB_ol: stD_LOGIC_vector(31 downto 0);`
104
105			`signal COREAPB_ll: sTD_LOGIC_vector(31 downto 0);`
106
107			`signal CoreAPB_il: STD_LOgic_vector(31 downto 0);`
108
109			`signal COREAPB_oi: std_LOGIC_VEctor(31 downto 0);`
110
111			`signal CoreAPB_LI: std_logic_vECTOR(31 downto 0);`
112
113			`signal COREAPB_ii: sTD_LOGIC_vector(31 downto 0);`
114
115			`signal COREAPB_o0: std_lOGIC_VEctor(31 downto 0);`
116
117			`signal COREAPB_l0: sTD_LOGIC_vector(31 downto 0);`
118
119			`signal CoreAPB_i0: STD_Logic_vector(31 downto 0);`
120
121			`signal CoREAPB_O1: stD_LOGIC_vector(31 downto 0);`
122
123			`signal CoreAPB_l1: STD_logic_vectOR(31 downto 0);`
124
125			`signal COREAPB_i1: std_logIC_VECTOr(31 downto 0);`
126
127			`signal CoREAPB_OOl: std_logIC_VECTOr(31 downto 0);`
128
129			`signal CoreAPB_lol: STD_logic_vecTOR(31 downto 0);`
130
131			`signal CoreAPB_ioL: STD_logic_vectOR(31 downto 0);`
132
133			`signal CoREAPB_Oll: std_LOGIC_VEctor(31 downto 0);`
134
135			`begin`
136			`CoreAPB_olL <= ( others => '0');`
137			`PADDRS <= PADDR;`
138			`PWRITES <= PWRITE;`
139			`PENABLES <= PENABLE;`
140			`PWDATAS <= PWDATA;`
141			`PSELS0 <= PSELECT(0);`
142			`PSELS1 <= PSELECT(1);`
143			`PSELS2 <= PSELECT(2);`
144			`PSELS3 <= PSELECT(3);`
145			`PSELS4 <= PSELECT(4);`
146			`PSELS5 <= PSELECT(5);`
147			`PSELS6 <= PSELECT(6);`
148			`PSELS7 <= PSELECT(7);`
149			`PSELS8 <= PSELECT(8);`
150			`PSELS9 <= PSELECT(9);`
151			`PSELS10 <= PSELECT(10);`
152			`PSELS11 <= PSELECT(11);`
153			`PSELS12 <= PSELECT(12);`
154			`PSELS13 <= PSELECT(13);`
155			`PSELS14 <= PSELECT(14);`
156			`PSELS15 <= PSELECT(15);`
157			`CoreAPB_LLL:`
158			`if (APBSlot0Enable = 1)`
159			`generate`
160			`begin`
161			`CoreAPB_I <= PRDATAS0;`
162			`end generate CoreAPB_llL;`
163			`CoreAPB_ilL:`
164			`if (APbSlot0EnablE = 0)`
165			`generate`
166			`begin`
167			`COREAPB_i <= COREAPB_oll;`
168			`end generate COREAPB_ill;`
169			`COReAPB_oil:`
170			`if (ApbSlot1EnaBLE = 1)`
171			`generate`
172			`begin`
173			`CoreAPB_ol <= PRDATAS1;`
174			`end generate CoreAPB_OIL;`
175			`CoreAPB_LIL:`
176			`if (APbSlot1EnablE = 0)`
177			`generate`
178			`begin`
179			`COREAPB_ol <= COREAPB_oll;`
180			`end generate COReAPB_lil;`
181			`COREAPB_iil:`
182			`if (ApbSlot2EnabLE = 1)`
183			`generate`
184			`begin`
185			`CoreAPB_ll <= PRDATAS2;`
186			`end generate COREAPB_iil;`
187			`COREAPB_o0l:`
188			`if (APBSLOT2Enable = 0)`
189			`generate`
190			`begin`
191			`COREAPB_ll <= CoreAPB_OLL;`
192			`end generate COREAPB_o0l;`
193			`COREAPB_l0l:`
194			`if (APBSlot3Enable = 1)`
195			`generate`
196			`begin`
197			`COReAPB_il <= PRDATAS3;`
198			`end generate COREAPB_l0l;`
199			`COREAPB_i0l:`
200			`if (ApBSLOT3Enable = 0)`
201			`generate`
202			`begin`
203			`CoreAPB_IL <= CoREAPB_Oll;`
204			`end generate COREAPB_i0l;`
205			`CoreAPB_O1L:`
206			`if (ApbSlot4EnaBLE = 1)`
207			`generate`
208			`begin`
209			`CoreAPB_oi <= PRDATAS4;`
210			`end generate CoreAPB_O1L;`
211			`CoreAPB_l1L:`
212			`if (ApbSlot4EnABLE = 0)`
213			`generate`
214			`begin`
215			`COReAPB_oi <= COreAPB_oll;`
216			`end generate CoreAPB_l1L;`
217			`COREAPB_i1l:`
218			`if (ApbSlot5EnaBLE = 1)`
219			`generate`
220			`begin`
221			`CoreAPB_li <= PRDATAS5;`
222			`end generate CoreAPB_i1L;`
223			`CoreAPB_ooi:`
224			`if (APBSLOT5Enable = 0)`
225			`generate`
226			`begin`
227			`CoreAPB_LI <= CoreAPB_OLL;`
228			`end generate CoreAPB_OOI;`
229			`CoreAPB_loi:`
230			`if (ApbSlot6ENABLE = 1)`
231			`generate`
232			`begin`
233			`CoreAPB_II <= PRDATAS6;`
234			`end generate CoreAPB_lOI;`
235			`CoreAPB_IOI:`
236			`if (APBSlot6Enable = 0)`
237			`generate`
238			`begin`
239			`CoreAPB_II <= CoreAPB_oLL;`
240			`end generate CoreAPB_IOI;`
241			`COREAPB_oli:`
242			`if (APbSlot7EnablE = 1)`
243			`generate`
244			`begin`
245			`COREAPB_O0 <= PRDATAS7;`
246			`end generate CoreAPB_OLI;`
247			`CoreAPB_LLI:`
248			`if (APBSLOT7Enable = 0)`
249			`generate`
250			`begin`
251			`COREAPB_o0 <= COReAPB_oll;`
252			`end generate CoreAPB_lli;`
253			`CoreAPB_ili:`
254			`if (ApbSlot8EnABLE = 1)`
255			`generate`
256			`begin`
257			`COREAPB_l0 <= PRDATAS8;`
258			`end generate COREAPB_ili;`
259			`COREAPB_oii:`
260			`if (ApbSloT8ENABLe = 0)`
261			`generate`
262			`begin`
263			`CoreAPB_l0 <= CoreAPB_oll;`
264			`end generate CoreAPB_OII;`
265			`COREAPB_lii:`
266			`if (ApbSlot9EnaBLE = 1)`
267			`generate`
268			`begin`
269			`COreAPB_i0 <= PRDATAS9;`
270			`end generate CoreAPB_liI;`
271			`CoreAPB_III:`
272			`if (APBSlot9Enable = 0)`
273			`generate`
274			`begin`
275			`CoreAPB_I0 <= CoreAPB_olL;`
276			`end generate CoreAPB_III;`
277			`CoreAPB_o0i:`
278			`if (APBSLOT10Enable = 1)`
279			`generate`
280			`begin`
281			`CorEAPB_O1 <= PRDATAS10;`
282			`end generate COReAPB_o0i;`
283			`CoreAPB_l0i:`
284			`if (APBSLOT10Enable = 0)`
285			`generate`
286			`begin`
287			`COREAPB_o1 <= COREAPB_oll;`
288			`end generate COREAPB_l0i;`
289			`CoreAPB_i0I:`
290			`if (ApbSlot11EnABLE = 1)`
291			`generate`
292			`begin`
293			`CoreAPB_l1 <= PRDATAS11;`
294			`end generate COREAPB_i0i;`
295			`COReAPB_o1i:`
296			`if (ApbSlot11ENABLE = 0)`
297			`generate`
298			`begin`
299			`COREAPB_l1 <= COREAPB_oll;`
300			`end generate COReAPB_o1i;`
301			`COREAPB_l1i:`
302			`if (ApbSlot12ENABLE = 1)`
303			`generate`
304			`begin`
305			`CoREAPB_I1 <= PRDATAS12;`
306			`end generate CoreAPB_l1I;`
307			`COREAPB_i1i:`
308			`if (APBSLOT12Enable = 0)`
309			`generate`
310			`begin`
311			`CoreAPB_I1 <= CoreAPB_olL;`
312			`end generate CoreAPB_i1I;`
313			`COReAPB_oo0:`
314			`if (APBSLOT13Enable = 1)`
315			`generate`
316			`begin`
317			`COREAPB_ool <= PRDATAS13;`
318			`end generate CoreAPB_oo0;`
319			`CoreAPB_LO0:`
320			`if (ApbSlot13ENABLE = 0)`
321			`generate`
322			`begin`
323			`CoreAPB_ool <= COREAPB_oll;`
324			`end generate CoreAPB_lo0;`
325			`COREAPB_io0:`
326			`if (APBSLOT14Enable = 1)`
327			`generate`
328			`begin`
329			`CoreAPB_LOL <= PRDATAS14;`
330			`end generate CorEAPB_IO0;`
331			`CoREAPB_Ol0:`
332			`if (ApbSlot14ENABLE = 0)`
333			`generate`
334			`begin`
335			`CoreAPB_lol <= COreAPB_oll;`
336			`end generate COreAPB_ol0;`
337			`COReAPB_ll0:`
338			`if (ApbSloT15ENABle = 1)`
339			`generate`
340			`begin`
341			`COREAPB_iol <= PRDATAS15;`
342			`end generate CoreAPB_ll0;`
343			`CoreAPB_il0:`
344			`if (ApbSlot15ENABLE = 0)`
345			`generate`
346			`begin`
347			`COREAPB_iol <= CoreAPB_OLL;`
348			`end generate CoreAPB_IL0;`
349			`COREAPB_oi0: COREAPB_l`
350			`port map (PSELS0 => PSELECT(0),`
351			`PSELS1 => PSELECT(1),`
352			`PSELS2 => PSELECT(2),`
353			`PSELS3 => PSELECT(3),`
354			`PSELS4 => PSELECT(4),`
355			`PSELS5 => PSELECT(5),`
356			`PSELS6 => PSELECT(6),`
357			`PSELS7 => PSELECT(7),`
358			`PSELS8 => PSELECT(8),`
359			`PSELS9 => PSELECT(9),`
360			`PSELS10 => PSELECT(10),`
361			`PSELS11 => PSELECT(11),`
362			`PSELS12 => PSELECT(12),`
363			`PSELS13 => PSELECT(13),`
364			`PSELS14 => PSELECT(14),`
365			`PSELS15 => PSELECT(15),`
366			`PRDATAS0 => COREAPB_i,`
367			`PRDATAS1 => COREAPB_ol,`
368			`PRDATAS2 => CoreAPB_ll,`
369			`PRDATAS3 => CoreAPB_iL,`
370			`PRDATAS4 => COREAPB_oi,`
371			`PRDATAS5 => CoreAPB_LI,`
372			`PRDATAS6 => COReAPB_ii,`
373			`PRDATAS7 => CoreAPB_O0,`
374			`PRDATAS8 => CoreAPB_l0,`
375			`PRDATAS9 => COREAPB_i0,`
376			`PRDATAS10 => COREAPB_O1,`
377			`PRDATAS11 => CoreAPB_L1,`
378			`PRDATAS12 => COREAPB_i1,`
379			`PRDATAS13 => CorEAPB_OOl,`
380			`PRDATAS14 => COReAPB_lol,`
381			`PRDATAS15 => CoreAPB_ioL,`
382			`PRDATA => PRDATA);`
383			`end COreAPB_o;`