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library ieee;

use ieee.std_logiC_1164.all;

entity COReAPB_l is

port (PSELS0: in STD_LOgic;

PSELS1: in stD_LOGIC;

PSELS2: in STD_logic;

PSELS3: in sTD_LOGIC;

PSELS4: in sTD_LOGIC;

PSELS5: in STD_logic;

PSELS6: in STD_logic;

PSELS7: in Std_logic;

PSELS8: in Std_logic;

PSELS9: in STD_Logic;

PSELS10: in STD_Logic;

PSELS11: in STD_Logic;

PSELS12: in STD_LOGic;

PSELS13: in std_LOGIC;

PSELS14: in std_LOGIC;

PSELS15: in std_logic;

PRDATAS0: in STD_LOGIc_vector(31 downto 0);

PRDATAS1: in Std_logic_vECTOR(31 downto 0);

PRDATAS2: in STD_LOgic_vector(31 downto 0);

PRDATAS3: in std_logic_vECTOR(31 downto 0);

PRDATAS4: in STD_logic_vectOR(31 downto 0);

PRDATAS5: in std_LOGIC_VEctor(31 downto 0);

PRDATAS6: in std_LOGIC_VEctor(31 downto 0);

PRDATAS7: in std_lOGIC_VECtor(31 downto 0);

PRDATAS8: in STD_logic_vectOR(31 downto 0);

PRDATAS9: in std_logIC_VECTOr(31 downto 0);

PRDATAS10: in Std_logic_vECTOR(31 downto 0);

PRDATAS11: in std_logiC_VECTOR(31 downto 0);

PRDATAS12: in Std_logic_veCTOR(31 downto 0);

PRDATAS13: in std_logic_vECTOR(31 downto 0);

PRDATAS14: in STD_logic_vectOR(31 downto 0);

PRDATAS15: in STD_logic_vectOR(31 downto 0);

PRDATA: out STD_LOgic_vector(31 downto 0));

end COREAPB_l;

architecture CoREAPB_Li0 of COREAPB_l is

constant CoreAPB_II0: STD_Logic_vector(3 downto 0) := "0000";

constant CoreAPB_o00: STd_logic_vecTOR(3 downto 0) := "0001";

constant COreAPB_l00: STd_logic_vecTOR(3 downto 0) := "0010";

constant CoreAPB_I00: stD_LOGIC_vector(3 downto 0) := "0011";

constant CoreAPB_o10: std_loGIC_VECTor(3 downto 0) := "0100";

constant CoreAPB_L10: std_LOGIC_vector(3 downto 0) := "0101";

constant COREAPB_i10: STD_logic_vectOR(3 downto 0) := "0110";

constant CoreAPB_oo1: Std_logic_veCTOR(3 downto 0) := "0111";

constant CoreAPB_LO1: std_LOGIC_VEctor(3 downto 0) := "1000";

constant COREAPB_io1: STD_logic_vectOR(3 downto 0) := "1001";

constant CoreAPB_OL1: std_lOGIC_VECtor(3 downto 0) := "1010";

constant COreAPB_ll1: Std_logic_vecTOR(3 downto 0) := "1011";

constant CoreAPB_il1: STD_logic_vectOR(3 downto 0) := "1100";

constant CoreAPB_oi1: STD_logic_vectOR(3 downto 0) := "1101";

constant CoreAPB_li1: Std_logic_vECTOR(3 downto 0) := "1110";

constant CoreAPB_II1: sTD_LOGIC_vector(3 downto 0) := "1111";

signal COreAPB_o01: Std_logic_veCTOR(3 downto 0);

begin

CorEAPB_O01(3) <= PSELS15 or PSELS14

or PSELS13

or PSELS12

or PSELS11

or PSELS10

or PSELS9

or PSELS8;

COReAPB_o01(2) <= PSELS15 or PSELS14

or PSELS13

or PSELS12

or PSELS7

or PSELS6

or PSELS5

or PSELS4;

CoreAPB_o01(1) <= PSELS15 or PSELS14

or PSELS11

or PSELS10

or PSELS7

or PSELS6

or PSELS3

or PSELS2;

COREAPB_o01(0) <= PSELS15 or PSELS13

or PSELS11

or PSELS9

or PSELS7

or PSELS5

or PSELS3

or PSELS1;

CoreAPB_L01:

process (CoreAPB_O01,PRDATAS0,PRDATAS1,PRDATAS2,PRDATAS3,PRDATAS4,PRDATAS5,PRDATAS6,PRDATAS7,PRDATAS8,PRDATAS9,PRDATAS10,PRDATAS11,PRDATAS12,PRDATAS13,PRDATAS14,PRDATAS15,PSELS0)

begin

case CoreAPB_o01 is

when CoreAPB_iI0 =>

if (PSELS0 = '1') then

PRDATA <= PRDATAS0;

else

PRDATA <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";

end if;

when CoreAPB_o00 =>

PRDATA <= PRDATAS1;

when COREAPB_l00 =>

PRDATA <= PRDATAS2;

when COREAPB_i00 =>

PRDATA <= PRDATAS3;

when COREAPB_o10 =>

PRDATA <= PRDATAS4;

when CoreAPB_l10 =>

PRDATA <= PRDATAS5;

when COReAPB_i10 =>

PRDATA <= PRDATAS6;

when CoreAPB_oO1 =>

PRDATA <= PRDATAS7;

when COreAPB_lo1 =>

PRDATA <= PRDATAS8;

when CoreAPB_IO1 =>

PRDATA <= PRDATAS9;

when COREAPB_ol1 =>

PRDATA <= PRDATAS10;

when COreAPB_ll1 =>

PRDATA <= PRDATAS11;

when COreAPB_il1 =>

PRDATA <= PRDATAS12;

when CoreAPB_OI1 =>

PRDATA <= PRDATAS13;

when CoreAPB_li1 =>

PRDATA <= PRDATAS14;

when COREAPB_ii1 =>

PRDATA <= PRDATAS15;

when others =>

PRDATA <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";

end case;

end process CoreAPB_l01;

end COREAPB_li0;