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-- Created by SmartDesign Sat Jun 02 22:52:43 2018

-- Version: v11.8 SP3 11.8.3.6

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-- Libraries

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library ieee;

use ieee.std_logic_1164.all;

library proasic3;

use proasic3.all;

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-- tb_top entity declaration

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entity tb_top is

    -- Port list

    port(

        -- Outputs

        DATAOUT  : out std_logic_vector(31 downto 0);

        RESP_err : out std_logic_vector(1 downto 0);

        TX       : out std_logic;

        ahb_busy : out std_logic

        );

end tb_top;

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-- tb_top architecture body

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architecture RTL of tb_top is

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-- Component declarations

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-- tb_clk

component tb_clk

    -- Port list

    port(

        -- Outputs

        HCLK  : out std_logic;

        HRSTn : out std_logic

        );

end component;

-- top

component top

    -- Port list

    port(

        -- Inputs

        ADDR     : in  std_logic_vector(31 downto 0);

        DATAIN   : in  std_logic_vector(31 downto 0);

        HCLK     : in  std_logic;

        HRESETn  : in  std_logic;

        LREAD    : in  std_logic;

        LWRITE   : in  std_logic;

        -- Outputs

        DATAOUT  : out std_logic_vector(31 downto 0);

        RESP_err : out std_logic_vector(1 downto 0);

        TX       : out std_logic;

        ahb_busy : out std_logic

        );

end component;

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-- Signal declarations

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signal ahb_busy_net_0 : std_logic;

signal DATAOUT_net_0  : std_logic_vector(31 downto 0);

signal RESP_err_net_0 : std_logic_vector(1 downto 0);

signal tb_clk_0_HCLK  : std_logic;

signal tb_clk_0_HRSTn : std_logic;

signal TX_net_0       : std_logic;

signal ahb_busy_net_1 : std_logic;

signal DATAOUT_net_1  : std_logic_vector(31 downto 0);

signal RESP_err_net_1 : std_logic_vector(1 downto 0);

signal TX_net_1       : std_logic;

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-- TiedOff Signals

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signal GND_net        : std_logic;

signal VCC_net        : std_logic;

signal ADDR_const_net_0: std_logic_vector(31 downto 0);

signal DATAIN_const_net_0: std_logic_vector(31 downto 0);

begin

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-- Constant assignments

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 GND_net            <= '0';

 VCC_net            <= '1';

 ADDR_const_net_0   <= B"00000000000000000000000000000000";

 DATAIN_const_net_0 <= B"00000000000000000000000010101010";

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-- Top level output port assignments

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 ahb_busy_net_1       <= ahb_busy_net_0;

 ahb_busy             <= ahb_busy_net_1;

 DATAOUT_net_1        <= DATAOUT_net_0;

 DATAOUT(31 downto 0) <= DATAOUT_net_1;

 RESP_err_net_1       <= RESP_err_net_0;

 RESP_err(1 downto 0) <= RESP_err_net_1;

 TX_net_1             <= TX_net_0;

 TX                   <= TX_net_1;

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-- Component instances

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-- tb_clk_0

tb_clk_0 : tb_clk

    port map(

        -- Outputs

        HCLK  => tb_clk_0_HCLK,

        HRSTn => tb_clk_0_HRSTn

        );

-- top_0

top_0 : top

    port map(

        -- Inputs

        HCLK     => tb_clk_0_HCLK,

        HRESETn  => tb_clk_0_HRSTn,

        LREAD    => GND_net,

        LWRITE   => VCC_net,

        ADDR     => ADDR_const_net_0,

        DATAIN   => DATAIN_const_net_0,

        -- Outputs

        ahb_busy => ahb_busy_net_0,

        DATAOUT  => DATAOUT_net_0,

        RESP_err => RESP_err_net_0,

        TX       => TX_net_0

        );

end RTL;