OpenCores
URL https://opencores.org/ocsvn/ahbmaster/ahbmaster/trunk

Subversion Repositories ahbmaster

[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [component/] [work/] [top/] [CoreAHBLite_0/] [rtl/] [vhdl/] [core/] [components.vhd] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 uson 
-- ********************************************************************/
2 
-- Actel Corporation Proprietary and Confidential
3 
-- Copyright 2013 Actel Corporation.  All rights reserved.
4 
--
5 
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
6 
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
7 
-- IN ADVANCE IN WRITING.
8 
--
9 
-- Description: CoreAHBLite - components package
10 
--
11 
--
12 
-- SVN Revision Information:
13 
-- SVN $Revision: 29810 $
14 
-- SVN $Date: 2017-05-12 15:15:00 +0530 (Fri, 12 May 2017) $
15 
--
16 
--
17 
-- *********************************************************************/
18 
library ieee;
19 
use ieee.std_logic_1164.all;
20 
 
21 
package top_CoreAHBLite_0_components is
22 
 
23 
component top_CoreAHBLite_0_CoreAHBLite
24 
generic (
25 
FAMILY                                  : integer range 0 to 99  := 17;
26 
MEMSPACE                                : integer range 0 to 6   := 0;
27 
HADDR_SHG_CFG                   : integer range 0 to 1   := 1;
28 
SC_0                    : integer range 0 to 1   := 1;
29 
SC_1                    : integer range 0 to 1   := 0;
30 
SC_2                    : integer range 0 to 1   := 0;
31 
SC_3                    : integer range 0 to 1   := 0;
32 
SC_4                    : integer range 0 to 1   := 0;
33 
SC_5                    : integer range 0 to 1   := 0;
34 
SC_6                    : integer range 0 to 1   := 0;
35 
SC_7                    : integer range 0 to 1   := 0;
36 
SC_8                    : integer range 0 to 1   := 0;
37 
SC_9                    : integer range 0 to 1   := 0;
38 
SC_10                   : integer range 0 to 1   := 0;
39 
SC_11                   : integer range 0 to 1   := 0;
40 
SC_12                   : integer range 0 to 1   := 0;
41 
SC_13                   : integer range 0 to 1   := 0;
42 
SC_14                   : integer range 0 to 1   := 0;
43 
SC_15                   : integer range 0 to 1   := 0;
44 
M0_AHBSLOT0ENABLE       : integer range 0 to 1   := 1;
45 
M0_AHBSLOT1ENABLE       : integer range 0 to 1   := 0;
46 
M0_AHBSLOT2ENABLE       : integer range 0 to 1   := 0;
47 
M0_AHBSLOT3ENABLE       : integer range 0 to 1   := 0;
48 
M0_AHBSLOT4ENABLE       : integer range 0 to 1   := 0;
49 
M0_AHBSLOT5ENABLE       : integer range 0 to 1   := 0;
50 
M0_AHBSLOT6ENABLE       : integer range 0 to 1   := 0;
51 
M0_AHBSLOT7ENABLE       : integer range 0 to 1   := 0;
52 
M0_AHBSLOT8ENABLE       : integer range 0 to 1   := 0;
53 
M0_AHBSLOT9ENABLE       : integer range 0 to 1   := 0;
54 
M0_AHBSLOT10ENABLE      : integer range 0 to 1   := 0;
55 
M0_AHBSLOT11ENABLE      : integer range 0 to 1   := 0;
56 
M0_AHBSLOT12ENABLE      : integer range 0 to 1   := 0;
57 
M0_AHBSLOT13ENABLE      : integer range 0 to 1   := 0;
58 
M0_AHBSLOT14ENABLE      : integer range 0 to 1   := 0;
59 
M0_AHBSLOT15ENABLE      : integer range 0 to 1   := 0;
60 
M0_AHBSLOT16ENABLE      : integer range 0 to 1   := 0;
61 
M1_AHBSLOT0ENABLE       : integer range 0 to 1   := 0;
62 
M1_AHBSLOT1ENABLE       : integer range 0 to 1   := 1;
63 
M1_AHBSLOT2ENABLE       : integer range 0 to 1   := 0;
64 
M1_AHBSLOT3ENABLE       : integer range 0 to 1   := 0;
65 
M1_AHBSLOT4ENABLE       : integer range 0 to 1   := 0;
66 
M1_AHBSLOT5ENABLE       : integer range 0 to 1   := 0;
67 
M1_AHBSLOT6ENABLE       : integer range 0 to 1   := 0;
68 
M1_AHBSLOT7ENABLE       : integer range 0 to 1   := 0;
69 
M1_AHBSLOT8ENABLE       : integer range 0 to 1   := 0;
70 
M1_AHBSLOT9ENABLE       : integer range 0 to 1   := 0;
71 
M1_AHBSLOT10ENABLE      : integer range 0 to 1   := 0;
72 
M1_AHBSLOT11ENABLE      : integer range 0 to 1   := 0;
73 
M1_AHBSLOT12ENABLE      : integer range 0 to 1   := 0;
74 
M1_AHBSLOT13ENABLE      : integer range 0 to 1   := 0;
75 
M1_AHBSLOT14ENABLE      : integer range 0 to 1   := 0;
76 
M1_AHBSLOT15ENABLE      : integer range 0 to 1   := 0;
77 
M1_AHBSLOT16ENABLE      : integer range 0 to 1   := 0;
78 
M2_AHBSLOT0ENABLE       : integer range 0 to 1   := 1;
79 
M2_AHBSLOT1ENABLE       : integer range 0 to 1   := 0;
80 
M2_AHBSLOT2ENABLE       : integer range 0 to 1   := 0;
81 
M2_AHBSLOT3ENABLE       : integer range 0 to 1   := 0;
82 
M2_AHBSLOT4ENABLE       : integer range 0 to 1   := 0;
83 
M2_AHBSLOT5ENABLE       : integer range 0 to 1   := 0;
84 
M2_AHBSLOT6ENABLE       : integer range 0 to 1   := 0;
85 
M2_AHBSLOT7ENABLE       : integer range 0 to 1   := 0;
86 
M2_AHBSLOT8ENABLE       : integer range 0 to 1   := 0;
87 
M2_AHBSLOT9ENABLE       : integer range 0 to 1   := 0;
88 
M2_AHBSLOT10ENABLE      : integer range 0 to 1   := 0;
89 
M2_AHBSLOT11ENABLE      : integer range 0 to 1   := 0;
90 
M2_AHBSLOT12ENABLE      : integer range 0 to 1   := 0;
91 
M2_AHBSLOT13ENABLE      : integer range 0 to 1   := 0;
92 
M2_AHBSLOT14ENABLE      : integer range 0 to 1   := 0;
93 
M2_AHBSLOT15ENABLE      : integer range 0 to 1   := 0;
94 
M2_AHBSLOT16ENABLE      : integer range 0 to 1   := 0;
95 
M3_AHBSLOT0ENABLE       : integer range 0 to 1   := 0;
96 
M3_AHBSLOT1ENABLE       : integer range 0 to 1   := 1;
97 
M3_AHBSLOT2ENABLE       : integer range 0 to 1   := 0;
98 
M3_AHBSLOT3ENABLE       : integer range 0 to 1   := 0;
99 
M3_AHBSLOT4ENABLE       : integer range 0 to 1   := 0;
100 
M3_AHBSLOT5ENABLE       : integer range 0 to 1   := 0;
101 
M3_AHBSLOT6ENABLE       : integer range 0 to 1   := 0;
102 
M3_AHBSLOT7ENABLE       : integer range 0 to 1   := 0;
103 
M3_AHBSLOT8ENABLE       : integer range 0 to 1   := 0;
104 
M3_AHBSLOT9ENABLE       : integer range 0 to 1   := 0;
105 
M3_AHBSLOT10ENABLE      : integer range 0 to 1   := 0;
106 
M3_AHBSLOT11ENABLE      : integer range 0 to 1   := 0;
107 
M3_AHBSLOT12ENABLE      : integer range 0 to 1   := 0;
108 
M3_AHBSLOT13ENABLE      : integer range 0 to 1   := 0;
109 
M3_AHBSLOT14ENABLE      : integer range 0 to 1   := 0;
110 
M3_AHBSLOT15ENABLE      : integer range 0 to 1   := 0;
111 
M3_AHBSLOT16ENABLE      : integer range 0 to 1   := 0
112 
);
113 
port (
114 
HCLK                : in std_logic;
115 
HRESETN             : in std_logic;
116 
REMAP_M0            : in std_logic;
117 
HADDR_M0            : in std_logic_vector(31 downto 0);
118 
HMASTLOCK_M0        : in std_logic;
119 
HSIZE_M0            : in std_logic_vector(2 downto 0);
120 
HTRANS_M0           : in std_logic_vector(1 downto 0);
121 
HWRITE_M0           : in std_logic;
122 
HWDATA_M0           : in std_logic_vector(31 downto 0);
123 
HBURST_M0           : in std_logic_vector(2 downto 0);
124 
HPROT_M0            : in std_logic_vector(3 downto 0);
125 
HRESP_M0            : out std_logic_vector(1 downto 0);
126 
HRDATA_M0           : out std_logic_vector(31 downto 0);
127 
HREADY_M0           : out std_logic;
128 
HADDR_M1            : in std_logic_vector(31 downto 0);
129 
HMASTLOCK_M1        : in std_logic;
130 
HSIZE_M1            : in std_logic_vector(2 downto 0);
131 
HTRANS_M1           : in std_logic_vector(1 downto 0);
132 
HWRITE_M1           : in std_logic;
133 
HWDATA_M1           : in std_logic_vector(31 downto 0);
134 
HBURST_M1           : in std_logic_vector(2 downto 0);
135 
HPROT_M1            : in std_logic_vector(3 downto 0);
136 
HRESP_M1            : out std_logic_vector(1 downto 0);
137 
HRDATA_M1           : out std_logic_vector(31 downto 0);
138 
HREADY_M1           : out std_logic;
139 
HADDR_M2            : in std_logic_vector(31 downto 0);
140 
HMASTLOCK_M2        : in std_logic;
141 
HSIZE_M2            : in std_logic_vector(2 downto 0);
142 
HTRANS_M2           : in std_logic_vector(1 downto 0);
143 
HWRITE_M2           : in std_logic;
144 
HWDATA_M2           : in std_logic_vector(31 downto 0);
145 
HBURST_M2           : in std_logic_vector(2 downto 0);
146 
HPROT_M2            : in std_logic_vector(3 downto 0);
147 
HRESP_M2            : out std_logic_vector(1 downto 0);
148 
HRDATA_M2           : out std_logic_vector(31 downto 0);
149 
HREADY_M2           : out std_logic;
150 
HADDR_M3            : in std_logic_vector(31 downto 0);
151 
HMASTLOCK_M3        : in std_logic;
152 
HSIZE_M3            : in std_logic_vector(2 downto 0);
153 
HTRANS_M3           : in std_logic_vector(1 downto 0);
154 
HWRITE_M3           : in std_logic;
155 
HWDATA_M3           : in std_logic_vector(31 downto 0);
156 
HBURST_M3           : in std_logic_vector(2 downto 0);
157 
HPROT_M3            : in std_logic_vector(3 downto 0);
158 
HRESP_M3            : out std_logic_vector(1 downto 0);
159 
HRDATA_M3           : out std_logic_vector(31 downto 0);
160 
HREADY_M3           : out std_logic;
161 
HRDATA_S0           : in std_logic_vector(31 downto 0);
162 
HREADYOUT_S0        : in std_logic;
163 
HRESP_S0            : in std_logic_vector(1 downto 0);
164 
HSEL_S0             : out std_logic;
165 
HADDR_S0            : out std_logic_vector(31 downto 0);
166 
HSIZE_S0            : out std_logic_vector(2 downto 0);
167 
HTRANS_S0           : out std_logic_vector(1 downto 0);
168 
HWRITE_S0           : out std_logic;
169 
HWDATA_S0           : out std_logic_vector(31 downto 0);
170 
HREADY_S0           : out std_logic;
171 
HMASTLOCK_S0        : out std_logic;
172 
HBURST_S0           : out std_logic_vector(2 downto 0);
173 
HPROT_S0            : out std_logic_vector(3 downto 0);
174 
HRDATA_S1           : in std_logic_vector(31 downto 0);
175 
HREADYOUT_S1        : in std_logic;
176 
HRESP_S1            : in std_logic_vector(1 downto 0);
177 
HSEL_S1             : out std_logic;
178 
HADDR_S1            : out std_logic_vector(31 downto 0);
179 
HSIZE_S1            : out std_logic_vector(2 downto 0);
180 
HTRANS_S1           : out std_logic_vector(1 downto 0);
181 
HWRITE_S1           : out std_logic;
182 
HWDATA_S1           : out std_logic_vector(31 downto 0);
183 
HREADY_S1           : out std_logic;
184 
HMASTLOCK_S1        : out std_logic;
185 
HBURST_S1           : out std_logic_vector(2 downto 0);
186 
HPROT_S1            : out std_logic_vector(3 downto 0);
187 
HRDATA_S2           : in std_logic_vector(31 downto 0);
188 
HREADYOUT_S2        : in std_logic;
189 
HRESP_S2            : in std_logic_vector(1 downto 0);
190 
HSEL_S2             : out std_logic;
191 
HADDR_S2            : out std_logic_vector(31 downto 0);
192 
HSIZE_S2            : out std_logic_vector(2 downto 0);
193 
HTRANS_S2           : out std_logic_vector(1 downto 0);
194 
HWRITE_S2           : out std_logic;
195 
HWDATA_S2           : out std_logic_vector(31 downto 0);
196 
HREADY_S2           : out std_logic;
197 
HMASTLOCK_S2        : out std_logic;
198 
HBURST_S2           : out std_logic_vector(2 downto 0);
199 
HPROT_S2            : out std_logic_vector(3 downto 0);
200 
HRDATA_S3           : in std_logic_vector(31 downto 0);
201 
HREADYOUT_S3        : in std_logic;
202 
HRESP_S3            : in std_logic_vector(1 downto 0);
203 
HSEL_S3             : out std_logic;
204 
HADDR_S3            : out std_logic_vector(31 downto 0);
205 
HSIZE_S3            : out std_logic_vector(2 downto 0);
206 
HTRANS_S3           : out std_logic_vector(1 downto 0);
207 
HWRITE_S3           : out std_logic;
208 
HWDATA_S3           : out std_logic_vector(31 downto 0);
209 
HREADY_S3           : out std_logic;
210 
HMASTLOCK_S3        : out std_logic;
211 
HBURST_S3           : out std_logic_vector(2 downto 0);
212 
HPROT_S3            : out std_logic_vector(3 downto 0);
213 
HRDATA_S4           : in std_logic_vector(31 downto 0);
214 
HREADYOUT_S4        : in std_logic;
215 
HRESP_S4            : in std_logic_vector(1 downto 0);
216 
HSEL_S4             : out std_logic;
217 
HADDR_S4            : out std_logic_vector(31 downto 0);
218 
HSIZE_S4            : out std_logic_vector(2 downto 0);
219 
HTRANS_S4           : out std_logic_vector(1 downto 0);
220 
HWRITE_S4           : out std_logic;
221 
HWDATA_S4           : out std_logic_vector(31 downto 0);
222 
HREADY_S4           : out std_logic;
223 
HMASTLOCK_S4        : out std_logic;
224 
HBURST_S4           : out std_logic_vector(2 downto 0);
225 
HPROT_S4            : out std_logic_vector(3 downto 0);
226 
HRDATA_S5           : in std_logic_vector(31 downto 0);
227 
HREADYOUT_S5        : in std_logic;
228 
HRESP_S5            : in std_logic_vector(1 downto 0);
229 
HSEL_S5             : out std_logic;
230 
HADDR_S5            : out std_logic_vector(31 downto 0);
231 
HSIZE_S5            : out std_logic_vector(2 downto 0);
232 
HTRANS_S5           : out std_logic_vector(1 downto 0);
233 
HWRITE_S5           : out std_logic;
234 
HWDATA_S5           : out std_logic_vector(31 downto 0);
235 
HREADY_S5           : out std_logic;
236 
HMASTLOCK_S5        : out std_logic;
237 
HBURST_S5           : out std_logic_vector(2 downto 0);
238 
HPROT_S5            : out std_logic_vector(3 downto 0);
239 
HRDATA_S6           : in std_logic_vector(31 downto 0);
240 
HREADYOUT_S6        : in std_logic;
241 
HRESP_S6            : in std_logic_vector(1 downto 0);
242 
HSEL_S6             : out std_logic;
243 
HADDR_S6            : out std_logic_vector(31 downto 0);
244 
HSIZE_S6            : out std_logic_vector(2 downto 0);
245 
HTRANS_S6           : out std_logic_vector(1 downto 0);
246 
HWRITE_S6           : out std_logic;
247 
HWDATA_S6           : out std_logic_vector(31 downto 0);
248 
HREADY_S6           : out std_logic;
249 
HMASTLOCK_S6        : out std_logic;
250 
HBURST_S6           : out std_logic_vector(2 downto 0);
251 
HPROT_S6            : out std_logic_vector(3 downto 0);
252 
HRDATA_S7           : in std_logic_vector(31 downto 0);
253 
HREADYOUT_S7        : in std_logic;
254 
HRESP_S7            : in std_logic_vector(1 downto 0);
255 
HSEL_S7             : out std_logic;
256 
HADDR_S7            : out std_logic_vector(31 downto 0);
257 
HSIZE_S7            : out std_logic_vector(2 downto 0);
258 
HTRANS_S7           : out std_logic_vector(1 downto 0);
259 
HWRITE_S7           : out std_logic;
260 
HWDATA_S7           : out std_logic_vector(31 downto 0);
261 
HREADY_S7           : out std_logic;
262 
HMASTLOCK_S7        : out std_logic;
263 
HBURST_S7           : out std_logic_vector(2 downto 0);
264 
HPROT_S7            : out std_logic_vector(3 downto 0);
265 
HRDATA_S8           : in std_logic_vector(31 downto 0);
266 
HREADYOUT_S8        : in std_logic;
267 
HRESP_S8            : in std_logic_vector(1 downto 0);
268 
HSEL_S8             : out std_logic;
269 
HADDR_S8            : out std_logic_vector(31 downto 0);
270 
HSIZE_S8            : out std_logic_vector(2 downto 0);
271 
HTRANS_S8           : out std_logic_vector(1 downto 0);
272 
HWRITE_S8           : out std_logic;
273 
HWDATA_S8           : out std_logic_vector(31 downto 0);
274 
HREADY_S8           : out std_logic;
275 
HMASTLOCK_S8        : out std_logic;
276 
HBURST_S8           : out std_logic_vector(2 downto 0);
277 
HPROT_S8            : out std_logic_vector(3 downto 0);
278 
HRDATA_S9           : in std_logic_vector(31 downto 0);
279 
HREADYOUT_S9        : in std_logic;
280 
HRESP_S9            : in std_logic_vector(1 downto 0);
281 
HSEL_S9             : out std_logic;
282 
HADDR_S9            : out std_logic_vector(31 downto 0);
283 
HSIZE_S9            : out std_logic_vector(2 downto 0);
284 
HTRANS_S9           : out std_logic_vector(1 downto 0);
285 
HWRITE_S9           : out std_logic;
286 
HWDATA_S9           : out std_logic_vector(31 downto 0);
287 
HREADY_S9           : out std_logic;
288 
HMASTLOCK_S9        : out std_logic;
289 
HBURST_S9           : out std_logic_vector(2 downto 0);
290 
HPROT_S9            : out std_logic_vector(3 downto 0);
291 
HRDATA_S10          : in std_logic_vector(31 downto 0);
292 
HREADYOUT_S10       : in std_logic;
293 
HRESP_S10           : in std_logic_vector(1 downto 0);
294 
HSEL_S10            : out std_logic;
295 
HADDR_S10           : out std_logic_vector(31 downto 0);
296 
HSIZE_S10           : out std_logic_vector(2 downto 0);
297 
HTRANS_S10          : out std_logic_vector(1 downto 0);
298 
HWRITE_S10          : out std_logic;
299 
HWDATA_S10          : out std_logic_vector(31 downto 0);
300 
HREADY_S10          : out std_logic;
301 
HMASTLOCK_S10       : out std_logic;
302 
HBURST_S10          : out std_logic_vector(2 downto 0);
303 
HPROT_S10           : out std_logic_vector(3 downto 0);
304 
HRDATA_S11          : in std_logic_vector(31 downto 0);
305 
HREADYOUT_S11       : in std_logic;
306 
HRESP_S11           : in std_logic_vector(1 downto 0);
307 
HSEL_S11            : out std_logic;
308 
HADDR_S11           : out std_logic_vector(31 downto 0);
309 
HSIZE_S11           : out std_logic_vector(2 downto 0);
310 
HTRANS_S11          : out std_logic_vector(1 downto 0);
311 
HWRITE_S11          : out std_logic;
312 
HWDATA_S11          : out std_logic_vector(31 downto 0);
313 
HREADY_S11          : out std_logic;
314 
HMASTLOCK_S11       : out std_logic;
315 
HBURST_S11          : out std_logic_vector(2 downto 0);
316 
HPROT_S11           : out std_logic_vector(3 downto 0);
317 
HRDATA_S12          : in std_logic_vector(31 downto 0);
318 
HREADYOUT_S12       : in std_logic;
319 
HRESP_S12           : in std_logic_vector(1 downto 0);
320 
HSEL_S12            : out std_logic;
321 
HADDR_S12           : out std_logic_vector(31 downto 0);
322 
HSIZE_S12           : out std_logic_vector(2 downto 0);
323 
HTRANS_S12          : out std_logic_vector(1 downto 0);
324 
HWRITE_S12          : out std_logic;
325 
HWDATA_S12          : out std_logic_vector(31 downto 0);
326 
HREADY_S12          : out std_logic;
327 
HMASTLOCK_S12       : out std_logic;
328 
HBURST_S12          : out std_logic_vector(2 downto 0);
329 
HPROT_S12           : out std_logic_vector(3 downto 0);
330 
HRDATA_S13          : in std_logic_vector(31 downto 0);
331 
HREADYOUT_S13       : in std_logic;
332 
HRESP_S13           : in std_logic_vector(1 downto 0);
333 
HSEL_S13            : out std_logic;
334 
HADDR_S13           : out std_logic_vector(31 downto 0);
335 
HSIZE_S13           : out std_logic_vector(2 downto 0);
336 
HTRANS_S13          : out std_logic_vector(1 downto 0);
337 
HWRITE_S13          : out std_logic;
338 
HWDATA_S13          : out std_logic_vector(31 downto 0);
339 
HREADY_S13          : out std_logic;
340 
HMASTLOCK_S13       : out std_logic;
341 
HBURST_S13          : out std_logic_vector(2 downto 0);
342 
HPROT_S13           : out std_logic_vector(3 downto 0);
343 
HRDATA_S14          : in std_logic_vector(31 downto 0);
344 
HREADYOUT_S14       : in std_logic;
345 
HRESP_S14           : in std_logic_vector(1 downto 0);
346 
HSEL_S14            : out std_logic;
347 
HADDR_S14           : out std_logic_vector(31 downto 0);
348 
HSIZE_S14           : out std_logic_vector(2 downto 0);
349 
HTRANS_S14          : out std_logic_vector(1 downto 0);
350 
HWRITE_S14          : out std_logic;
351 
HWDATA_S14          : out std_logic_vector(31 downto 0);
352 
HREADY_S14          : out std_logic;
353 
HMASTLOCK_S14       : out std_logic;
354 
HBURST_S14          : out std_logic_vector(2 downto 0);
355 
HPROT_S14           : out std_logic_vector(3 downto 0);
356 
HRDATA_S15          : in std_logic_vector(31 downto 0);
357 
HREADYOUT_S15       : in std_logic;
358 
HRESP_S15           : in std_logic_vector(1 downto 0);
359 
HSEL_S15            : out std_logic;
360 
HADDR_S15           : out std_logic_vector(31 downto 0);
361 
HSIZE_S15           : out std_logic_vector(2 downto 0);
362 
HTRANS_S15          : out std_logic_vector(1 downto 0);
363 
HWRITE_S15          : out std_logic;
364 
HWDATA_S15          : out std_logic_vector(31 downto 0);
365 
HREADY_S15          : out std_logic;
366 
HMASTLOCK_S15       : out std_logic;
367 
HBURST_S15          : out std_logic_vector(2 downto 0);
368 
HPROT_S15           : out std_logic_vector(3 downto 0);
369 
HRDATA_S16          : in std_logic_vector(31 downto 0);
370 
HREADYOUT_S16       : in std_logic;
371 
HRESP_S16           : in std_logic_vector(1 downto 0);
372 
HSEL_S16            : out std_logic;
373 
HADDR_S16           : out std_logic_vector(31 downto 0);
374 
HSIZE_S16           : out std_logic_vector(2 downto 0);
375 
HTRANS_S16          : out std_logic_vector(1 downto 0);
376 
HWRITE_S16          : out std_logic;
377 
HWDATA_S16          : out std_logic_vector(31 downto 0);
378 
HREADY_S16          : out std_logic;
379 
HMASTLOCK_S16       : out std_logic;
380 
HBURST_S16          : out std_logic_vector(2 downto 0);
381 
HPROT_S16           : out std_logic_vector(3 downto 0)
382 
);
383 
end component;
384 
 
385 
end top_CoreAHBLite_0_components;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.