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-- ********************************************************************/
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-- Actel Corporation Proprietary and Confidential
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-- Copyright 2010 Actel Corporation. All rights reserved.
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--
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-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
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-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
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-- IN ADVANCE IN WRITING.
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--
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-- Description: CoreAHBLite - multi-master (up to 2) AHBLite
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-- bus interface.
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--
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-- Instantiates the following modules:
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-- COREAHBLITE_MATRIX2X16
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--
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--
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-- SVN Revision Information:
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-- SVN $Revision: 29811 $
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-- SVN $Date: 2017-05-12 15:15:17 +0530 (Fri, 12 May 2017) $
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--
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--
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-- *********************************************************************/
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.coreahblite_pkg.all;
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entity top_CoreAHBLite_0_CoreAHBLite is
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generic (
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FAMILY : integer range 0 to 99 := 17;
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MEMSPACE : integer range 0 to 6 := 0;
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HADDR_SHG_CFG : integer range 0 to 1 := 1;
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SC_0 : integer range 0 to 1 := 1;
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SC_1 : integer range 0 to 1 := 0;
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SC_2 : integer range 0 to 1 := 0;
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SC_3 : integer range 0 to 1 := 0;
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SC_4 : integer range 0 to 1 := 0;
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SC_5 : integer range 0 to 1 := 0;
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SC_6 : integer range 0 to 1 := 0;
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SC_7 : integer range 0 to 1 := 0;
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SC_8 : integer range 0 to 1 := 0;
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SC_9 : integer range 0 to 1 := 0;
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SC_10 : integer range 0 to 1 := 0;
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SC_11 : integer range 0 to 1 := 0;
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SC_12 : integer range 0 to 1 := 0;
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SC_13 : integer range 0 to 1 := 0;
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SC_14 : integer range 0 to 1 := 0;
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SC_15 : integer range 0 to 1 := 0;
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M0_AHBSLOT0ENABLE : integer range 0 to 1 := 1;
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M0_AHBSLOT1ENABLE : integer range 0 to 1 := 0;
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M0_AHBSLOT2ENABLE : integer range 0 to 1 := 0;
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M0_AHBSLOT3ENABLE : integer range 0 to 1 := 0;
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M0_AHBSLOT4ENABLE : integer range 0 to 1 := 0;
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M0_AHBSLOT5ENABLE : integer range 0 to 1 := 0;
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M0_AHBSLOT6ENABLE : integer range 0 to 1 := 0;
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M0_AHBSLOT7ENABLE : integer range 0 to 1 := 0;
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M0_AHBSLOT8ENABLE : integer range 0 to 1 := 0;
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M0_AHBSLOT9ENABLE : integer range 0 to 1 := 0;
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M0_AHBSLOT10ENABLE : integer range 0 to 1 := 0;
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M0_AHBSLOT11ENABLE : integer range 0 to 1 := 0;
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M0_AHBSLOT12ENABLE : integer range 0 to 1 := 0;
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M0_AHBSLOT13ENABLE : integer range 0 to 1 := 0;
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M0_AHBSLOT14ENABLE : integer range 0 to 1 := 0;
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M0_AHBSLOT15ENABLE : integer range 0 to 1 := 0;
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M0_AHBSLOT16ENABLE : integer range 0 to 1 := 0;
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M1_AHBSLOT0ENABLE : integer range 0 to 1 := 0;
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M1_AHBSLOT1ENABLE : integer range 0 to 1 := 1;
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M1_AHBSLOT2ENABLE : integer range 0 to 1 := 0;
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M1_AHBSLOT3ENABLE : integer range 0 to 1 := 0;
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M1_AHBSLOT4ENABLE : integer range 0 to 1 := 0;
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M1_AHBSLOT5ENABLE : integer range 0 to 1 := 0;
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M1_AHBSLOT6ENABLE : integer range 0 to 1 := 0;
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M1_AHBSLOT7ENABLE : integer range 0 to 1 := 0;
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M1_AHBSLOT8ENABLE : integer range 0 to 1 := 0;
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M1_AHBSLOT9ENABLE : integer range 0 to 1 := 0;
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M1_AHBSLOT10ENABLE : integer range 0 to 1 := 0;
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M1_AHBSLOT11ENABLE : integer range 0 to 1 := 0;
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M1_AHBSLOT12ENABLE : integer range 0 to 1 := 0;
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M1_AHBSLOT13ENABLE : integer range 0 to 1 := 0;
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M1_AHBSLOT14ENABLE : integer range 0 to 1 := 0;
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M1_AHBSLOT15ENABLE : integer range 0 to 1 := 0;
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M1_AHBSLOT16ENABLE : integer range 0 to 1 := 0;
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M2_AHBSLOT0ENABLE : integer range 0 to 1 := 1;
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M2_AHBSLOT1ENABLE : integer range 0 to 1 := 0;
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M2_AHBSLOT2ENABLE : integer range 0 to 1 := 0;
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M2_AHBSLOT3ENABLE : integer range 0 to 1 := 0;
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M2_AHBSLOT4ENABLE : integer range 0 to 1 := 0;
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M2_AHBSLOT5ENABLE : integer range 0 to 1 := 0;
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M2_AHBSLOT6ENABLE : integer range 0 to 1 := 0;
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M2_AHBSLOT7ENABLE : integer range 0 to 1 := 0;
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M2_AHBSLOT8ENABLE : integer range 0 to 1 := 0;
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M2_AHBSLOT9ENABLE : integer range 0 to 1 := 0;
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M2_AHBSLOT10ENABLE : integer range 0 to 1 := 0;
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M2_AHBSLOT11ENABLE : integer range 0 to 1 := 0;
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M2_AHBSLOT12ENABLE : integer range 0 to 1 := 0;
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M2_AHBSLOT13ENABLE : integer range 0 to 1 := 0;
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M2_AHBSLOT14ENABLE : integer range 0 to 1 := 0;
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M2_AHBSLOT15ENABLE : integer range 0 to 1 := 0;
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M2_AHBSLOT16ENABLE : integer range 0 to 1 := 0;
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M3_AHBSLOT0ENABLE : integer range 0 to 1 := 0;
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M3_AHBSLOT1ENABLE : integer range 0 to 1 := 1;
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M3_AHBSLOT2ENABLE : integer range 0 to 1 := 0;
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M3_AHBSLOT3ENABLE : integer range 0 to 1 := 0;
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M3_AHBSLOT4ENABLE : integer range 0 to 1 := 0;
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M3_AHBSLOT5ENABLE : integer range 0 to 1 := 0;
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M3_AHBSLOT6ENABLE : integer range 0 to 1 := 0;
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M3_AHBSLOT7ENABLE : integer range 0 to 1 := 0;
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M3_AHBSLOT8ENABLE : integer range 0 to 1 := 0;
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M3_AHBSLOT9ENABLE : integer range 0 to 1 := 0;
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M3_AHBSLOT10ENABLE : integer range 0 to 1 := 0;
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M3_AHBSLOT11ENABLE : integer range 0 to 1 := 0;
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M3_AHBSLOT12ENABLE : integer range 0 to 1 := 0;
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M3_AHBSLOT13ENABLE : integer range 0 to 1 := 0;
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M3_AHBSLOT14ENABLE : integer range 0 to 1 := 0;
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M3_AHBSLOT15ENABLE : integer range 0 to 1 := 0;
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M3_AHBSLOT16ENABLE : integer range 0 to 1 := 0
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);
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port (
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HCLK : in std_logic;
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HRESETN : in std_logic;
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REMAP_M0 : in std_logic;
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HADDR_M0 : in std_logic_vector(31 downto 0);
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HMASTLOCK_M0 : in std_logic;
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HSIZE_M0 : in std_logic_vector(2 downto 0);
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HTRANS_M0 : in std_logic_vector(1 downto 0);
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HWRITE_M0 : in std_logic;
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HWDATA_M0 : in std_logic_vector(31 downto 0);
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HBURST_M0 : in std_logic_vector(2 downto 0);
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HPROT_M0 : in std_logic_vector(3 downto 0);
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HRESP_M0 : out std_logic_vector(1 downto 0);
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HRDATA_M0 : out std_logic_vector(31 downto 0);
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HREADY_M0 : out std_logic;
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HADDR_M1 : in std_logic_vector(31 downto 0);
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HMASTLOCK_M1 : in std_logic;
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HSIZE_M1 : in std_logic_vector(2 downto 0);
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HTRANS_M1 : in std_logic_vector(1 downto 0);
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HWRITE_M1 : in std_logic;
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HWDATA_M1 : in std_logic_vector(31 downto 0);
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HBURST_M1 : in std_logic_vector(2 downto 0);
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HPROT_M1 : in std_logic_vector(3 downto 0);
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HRESP_M1 : out std_logic_vector(1 downto 0);
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HRDATA_M1 : out std_logic_vector(31 downto 0);
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HREADY_M1 : out std_logic;
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HADDR_M2 : in std_logic_vector(31 downto 0);
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HMASTLOCK_M2 : in std_logic;
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HSIZE_M2 : in std_logic_vector(2 downto 0);
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HTRANS_M2 : in std_logic_vector(1 downto 0);
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HWRITE_M2 : in std_logic;
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HWDATA_M2 : in std_logic_vector(31 downto 0);
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HBURST_M2 : in std_logic_vector(2 downto 0);
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HPROT_M2 : in std_logic_vector(3 downto 0);
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HRESP_M2 : out std_logic_vector(1 downto 0);
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HRDATA_M2 : out std_logic_vector(31 downto 0);
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HREADY_M2 : out std_logic;
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HADDR_M3 : in std_logic_vector(31 downto 0);
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HMASTLOCK_M3 : in std_logic;
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HSIZE_M3 : in std_logic_vector(2 downto 0);
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HTRANS_M3 : in std_logic_vector(1 downto 0);
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HWRITE_M3 : in std_logic;
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HWDATA_M3 : in std_logic_vector(31 downto 0);
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HBURST_M3 : in std_logic_vector(2 downto 0);
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HPROT_M3 : in std_logic_vector(3 downto 0);
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HRESP_M3 : out std_logic_vector(1 downto 0);
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HRDATA_M3 : out std_logic_vector(31 downto 0);
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HREADY_M3 : out std_logic;
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HRDATA_S0 : in std_logic_vector(31 downto 0);
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HREADYOUT_S0 : in std_logic;
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HRESP_S0 : in std_logic_vector(1 downto 0);
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HSEL_S0 : out std_logic;
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HADDR_S0 : out std_logic_vector(31 downto 0);
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HSIZE_S0 : out std_logic_vector(2 downto 0);
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HTRANS_S0 : out std_logic_vector(1 downto 0);
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HWRITE_S0 : out std_logic;
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HWDATA_S0 : out std_logic_vector(31 downto 0);
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HREADY_S0 : out std_logic;
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HMASTLOCK_S0 : out std_logic;
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HBURST_S0 : out std_logic_vector(2 downto 0);
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HPROT_S0 : out std_logic_vector(3 downto 0);
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HRDATA_S1 : in std_logic_vector(31 downto 0);
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HREADYOUT_S1 : in std_logic;
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HRESP_S1 : in std_logic_vector(1 downto 0);
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HSEL_S1 : out std_logic;
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HADDR_S1 : out std_logic_vector(31 downto 0);
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HSIZE_S1 : out std_logic_vector(2 downto 0);
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HTRANS_S1 : out std_logic_vector(1 downto 0);
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HWRITE_S1 : out std_logic;
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HWDATA_S1 : out std_logic_vector(31 downto 0);
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HREADY_S1 : out std_logic;
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HMASTLOCK_S1 : out std_logic;
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HBURST_S1 : out std_logic_vector(2 downto 0);
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HPROT_S1 : out std_logic_vector(3 downto 0);
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HRDATA_S2 : in std_logic_vector(31 downto 0);
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HREADYOUT_S2 : in std_logic;
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HRESP_S2 : in std_logic_vector(1 downto 0);
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HSEL_S2 : out std_logic;
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HADDR_S2 : out std_logic_vector(31 downto 0);
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HSIZE_S2 : out std_logic_vector(2 downto 0);
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HTRANS_S2 : out std_logic_vector(1 downto 0);
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HWRITE_S2 : out std_logic;
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HWDATA_S2 : out std_logic_vector(31 downto 0);
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HREADY_S2 : out std_logic;
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HMASTLOCK_S2 : out std_logic;
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HBURST_S2 : out std_logic_vector(2 downto 0);
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HPROT_S2 : out std_logic_vector(3 downto 0);
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HRDATA_S3 : in std_logic_vector(31 downto 0);
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HREADYOUT_S3 : in std_logic;
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HRESP_S3 : in std_logic_vector(1 downto 0);
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HSEL_S3 : out std_logic;
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HADDR_S3 : out std_logic_vector(31 downto 0);
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HSIZE_S3 : out std_logic_vector(2 downto 0);
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HTRANS_S3 : out std_logic_vector(1 downto 0);
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HWRITE_S3 : out std_logic;
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HWDATA_S3 : out std_logic_vector(31 downto 0);
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HREADY_S3 : out std_logic;
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HMASTLOCK_S3 : out std_logic;
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HBURST_S3 : out std_logic_vector(2 downto 0);
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HPROT_S3 : out std_logic_vector(3 downto 0);
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HRDATA_S4 : in std_logic_vector(31 downto 0);
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HREADYOUT_S4 : in std_logic;
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HRESP_S4 : in std_logic_vector(1 downto 0);
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HSEL_S4 : out std_logic;
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HADDR_S4 : out std_logic_vector(31 downto 0);
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HSIZE_S4 : out std_logic_vector(2 downto 0);
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HTRANS_S4 : out std_logic_vector(1 downto 0);
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HWRITE_S4 : out std_logic;
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HWDATA_S4 : out std_logic_vector(31 downto 0);
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HREADY_S4 : out std_logic;
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HMASTLOCK_S4 : out std_logic;
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HBURST_S4 : out std_logic_vector(2 downto 0);
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HPROT_S4 : out std_logic_vector(3 downto 0);
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HRDATA_S5 : in std_logic_vector(31 downto 0);
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HREADYOUT_S5 : in std_logic;
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HRESP_S5 : in std_logic_vector(1 downto 0);
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HSEL_S5 : out std_logic;
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HADDR_S5 : out std_logic_vector(31 downto 0);
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HSIZE_S5 : out std_logic_vector(2 downto 0);
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HTRANS_S5 : out std_logic_vector(1 downto 0);
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HWRITE_S5 : out std_logic;
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HWDATA_S5 : out std_logic_vector(31 downto 0);
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HREADY_S5 : out std_logic;
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HMASTLOCK_S5 : out std_logic;
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HBURST_S5 : out std_logic_vector(2 downto 0);
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HPROT_S5 : out std_logic_vector(3 downto 0);
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HRDATA_S6 : in std_logic_vector(31 downto 0);
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HREADYOUT_S6 : in std_logic;
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HRESP_S6 : in std_logic_vector(1 downto 0);
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HSEL_S6 : out std_logic;
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HADDR_S6 : out std_logic_vector(31 downto 0);
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HSIZE_S6 : out std_logic_vector(2 downto 0);
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HTRANS_S6 : out std_logic_vector(1 downto 0);
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HWRITE_S6 : out std_logic;
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HWDATA_S6 : out std_logic_vector(31 downto 0);
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HREADY_S6 : out std_logic;
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HMASTLOCK_S6 : out std_logic;
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HBURST_S6 : out std_logic_vector(2 downto 0);
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HPROT_S6 : out std_logic_vector(3 downto 0);
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HRDATA_S7 : in std_logic_vector(31 downto 0);
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HREADYOUT_S7 : in std_logic;
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HRESP_S7 : in std_logic_vector(1 downto 0);
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HSEL_S7 : out std_logic;
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HADDR_S7 : out std_logic_vector(31 downto 0);
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HSIZE_S7 : out std_logic_vector(2 downto 0);
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HTRANS_S7 : out std_logic_vector(1 downto 0);
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HWRITE_S7 : out std_logic;
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HWDATA_S7 : out std_logic_vector(31 downto 0);
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HREADY_S7 : out std_logic;
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HMASTLOCK_S7 : out std_logic;
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HBURST_S7 : out std_logic_vector(2 downto 0);
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HPROT_S7 : out std_logic_vector(3 downto 0);
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HRDATA_S8 : in std_logic_vector(31 downto 0);
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HREADYOUT_S8 : in std_logic;
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|
|
HRESP_S8 : in std_logic_vector(1 downto 0);
|
272 |
|
|
HSEL_S8 : out std_logic;
|
273 |
|
|
HADDR_S8 : out std_logic_vector(31 downto 0);
|
274 |
|
|
HSIZE_S8 : out std_logic_vector(2 downto 0);
|
275 |
|
|
HTRANS_S8 : out std_logic_vector(1 downto 0);
|
276 |
|
|
HWRITE_S8 : out std_logic;
|
277 |
|
|
HWDATA_S8 : out std_logic_vector(31 downto 0);
|
278 |
|
|
HREADY_S8 : out std_logic;
|
279 |
|
|
HMASTLOCK_S8 : out std_logic;
|
280 |
|
|
HBURST_S8 : out std_logic_vector(2 downto 0);
|
281 |
|
|
HPROT_S8 : out std_logic_vector(3 downto 0);
|
282 |
|
|
HRDATA_S9 : in std_logic_vector(31 downto 0);
|
283 |
|
|
HREADYOUT_S9 : in std_logic;
|
284 |
|
|
HRESP_S9 : in std_logic_vector(1 downto 0);
|
285 |
|
|
HSEL_S9 : out std_logic;
|
286 |
|
|
HADDR_S9 : out std_logic_vector(31 downto 0);
|
287 |
|
|
HSIZE_S9 : out std_logic_vector(2 downto 0);
|
288 |
|
|
HTRANS_S9 : out std_logic_vector(1 downto 0);
|
289 |
|
|
HWRITE_S9 : out std_logic;
|
290 |
|
|
HWDATA_S9 : out std_logic_vector(31 downto 0);
|
291 |
|
|
HREADY_S9 : out std_logic;
|
292 |
|
|
HMASTLOCK_S9 : out std_logic;
|
293 |
|
|
HBURST_S9 : out std_logic_vector(2 downto 0);
|
294 |
|
|
HPROT_S9 : out std_logic_vector(3 downto 0);
|
295 |
|
|
HRDATA_S10 : in std_logic_vector(31 downto 0);
|
296 |
|
|
HREADYOUT_S10 : in std_logic;
|
297 |
|
|
HRESP_S10 : in std_logic_vector(1 downto 0);
|
298 |
|
|
HSEL_S10 : out std_logic;
|
299 |
|
|
HADDR_S10 : out std_logic_vector(31 downto 0);
|
300 |
|
|
HSIZE_S10 : out std_logic_vector(2 downto 0);
|
301 |
|
|
HTRANS_S10 : out std_logic_vector(1 downto 0);
|
302 |
|
|
HWRITE_S10 : out std_logic;
|
303 |
|
|
HWDATA_S10 : out std_logic_vector(31 downto 0);
|
304 |
|
|
HREADY_S10 : out std_logic;
|
305 |
|
|
HMASTLOCK_S10 : out std_logic;
|
306 |
|
|
HBURST_S10 : out std_logic_vector(2 downto 0);
|
307 |
|
|
HPROT_S10 : out std_logic_vector(3 downto 0);
|
308 |
|
|
HRDATA_S11 : in std_logic_vector(31 downto 0);
|
309 |
|
|
HREADYOUT_S11 : in std_logic;
|
310 |
|
|
HRESP_S11 : in std_logic_vector(1 downto 0);
|
311 |
|
|
HSEL_S11 : out std_logic;
|
312 |
|
|
HADDR_S11 : out std_logic_vector(31 downto 0);
|
313 |
|
|
HSIZE_S11 : out std_logic_vector(2 downto 0);
|
314 |
|
|
HTRANS_S11 : out std_logic_vector(1 downto 0);
|
315 |
|
|
HWRITE_S11 : out std_logic;
|
316 |
|
|
HWDATA_S11 : out std_logic_vector(31 downto 0);
|
317 |
|
|
HREADY_S11 : out std_logic;
|
318 |
|
|
HMASTLOCK_S11 : out std_logic;
|
319 |
|
|
HBURST_S11 : out std_logic_vector(2 downto 0);
|
320 |
|
|
HPROT_S11 : out std_logic_vector(3 downto 0);
|
321 |
|
|
HRDATA_S12 : in std_logic_vector(31 downto 0);
|
322 |
|
|
HREADYOUT_S12 : in std_logic;
|
323 |
|
|
HRESP_S12 : in std_logic_vector(1 downto 0);
|
324 |
|
|
HSEL_S12 : out std_logic;
|
325 |
|
|
HADDR_S12 : out std_logic_vector(31 downto 0);
|
326 |
|
|
HSIZE_S12 : out std_logic_vector(2 downto 0);
|
327 |
|
|
HTRANS_S12 : out std_logic_vector(1 downto 0);
|
328 |
|
|
HWRITE_S12 : out std_logic;
|
329 |
|
|
HWDATA_S12 : out std_logic_vector(31 downto 0);
|
330 |
|
|
HREADY_S12 : out std_logic;
|
331 |
|
|
HMASTLOCK_S12 : out std_logic;
|
332 |
|
|
HBURST_S12 : out std_logic_vector(2 downto 0);
|
333 |
|
|
HPROT_S12 : out std_logic_vector(3 downto 0);
|
334 |
|
|
HRDATA_S13 : in std_logic_vector(31 downto 0);
|
335 |
|
|
HREADYOUT_S13 : in std_logic;
|
336 |
|
|
HRESP_S13 : in std_logic_vector(1 downto 0);
|
337 |
|
|
HSEL_S13 : out std_logic;
|
338 |
|
|
HADDR_S13 : out std_logic_vector(31 downto 0);
|
339 |
|
|
HSIZE_S13 : out std_logic_vector(2 downto 0);
|
340 |
|
|
HTRANS_S13 : out std_logic_vector(1 downto 0);
|
341 |
|
|
HWRITE_S13 : out std_logic;
|
342 |
|
|
HWDATA_S13 : out std_logic_vector(31 downto 0);
|
343 |
|
|
HREADY_S13 : out std_logic;
|
344 |
|
|
HMASTLOCK_S13 : out std_logic;
|
345 |
|
|
HBURST_S13 : out std_logic_vector(2 downto 0);
|
346 |
|
|
HPROT_S13 : out std_logic_vector(3 downto 0);
|
347 |
|
|
HRDATA_S14 : in std_logic_vector(31 downto 0);
|
348 |
|
|
HREADYOUT_S14 : in std_logic;
|
349 |
|
|
HRESP_S14 : in std_logic_vector(1 downto 0);
|
350 |
|
|
HSEL_S14 : out std_logic;
|
351 |
|
|
HADDR_S14 : out std_logic_vector(31 downto 0);
|
352 |
|
|
HSIZE_S14 : out std_logic_vector(2 downto 0);
|
353 |
|
|
HTRANS_S14 : out std_logic_vector(1 downto 0);
|
354 |
|
|
HWRITE_S14 : out std_logic;
|
355 |
|
|
HWDATA_S14 : out std_logic_vector(31 downto 0);
|
356 |
|
|
HREADY_S14 : out std_logic;
|
357 |
|
|
HMASTLOCK_S14 : out std_logic;
|
358 |
|
|
HBURST_S14 : out std_logic_vector(2 downto 0);
|
359 |
|
|
HPROT_S14 : out std_logic_vector(3 downto 0);
|
360 |
|
|
HRDATA_S15 : in std_logic_vector(31 downto 0);
|
361 |
|
|
HREADYOUT_S15 : in std_logic;
|
362 |
|
|
HRESP_S15 : in std_logic_vector(1 downto 0);
|
363 |
|
|
HSEL_S15 : out std_logic;
|
364 |
|
|
HADDR_S15 : out std_logic_vector(31 downto 0);
|
365 |
|
|
HSIZE_S15 : out std_logic_vector(2 downto 0);
|
366 |
|
|
HTRANS_S15 : out std_logic_vector(1 downto 0);
|
367 |
|
|
HWRITE_S15 : out std_logic;
|
368 |
|
|
HWDATA_S15 : out std_logic_vector(31 downto 0);
|
369 |
|
|
HREADY_S15 : out std_logic;
|
370 |
|
|
HMASTLOCK_S15 : out std_logic;
|
371 |
|
|
HBURST_S15 : out std_logic_vector(2 downto 0);
|
372 |
|
|
HPROT_S15 : out std_logic_vector(3 downto 0);
|
373 |
|
|
HRDATA_S16 : in std_logic_vector(31 downto 0);
|
374 |
|
|
HREADYOUT_S16 : in std_logic;
|
375 |
|
|
HRESP_S16 : in std_logic_vector(1 downto 0);
|
376 |
|
|
HSEL_S16 : out std_logic;
|
377 |
|
|
HADDR_S16 : out std_logic_vector(31 downto 0);
|
378 |
|
|
HSIZE_S16 : out std_logic_vector(2 downto 0);
|
379 |
|
|
HTRANS_S16 : out std_logic_vector(1 downto 0);
|
380 |
|
|
HWRITE_S16 : out std_logic;
|
381 |
|
|
HWDATA_S16 : out std_logic_vector(31 downto 0);
|
382 |
|
|
HREADY_S16 : out std_logic;
|
383 |
|
|
HMASTLOCK_S16 : out std_logic;
|
384 |
|
|
HBURST_S16 : out std_logic_vector(2 downto 0);
|
385 |
|
|
HPROT_S16 : out std_logic_vector(3 downto 0)
|
386 |
|
|
);
|
387 |
|
|
end entity top_CoreAHBLite_0_CoreAHBLite;
|
388 |
|
|
|
389 |
|
|
architecture CoreAHBLite_arch of top_CoreAHBLite_0_CoreAHBLite is
|
390 |
|
|
|
391 |
|
|
constant SYNC_RESET : integer := SYNC_MODE_SEL(FAMILY);
|
392 |
|
|
|
393 |
|
|
constant M0_AHBSLOTENABLE : integer :=
|
394 |
|
|
(M0_AHBSLOT16ENABLE * (2**16)) +
|
395 |
|
|
(M0_AHBSLOT15ENABLE * (2**15)) +
|
396 |
|
|
(M0_AHBSLOT14ENABLE * (2**14)) +
|
397 |
|
|
(M0_AHBSLOT13ENABLE * (2**13)) +
|
398 |
|
|
(M0_AHBSLOT12ENABLE * (2**12)) +
|
399 |
|
|
(M0_AHBSLOT11ENABLE * (2**11)) +
|
400 |
|
|
(M0_AHBSLOT10ENABLE * (2**10)) +
|
401 |
|
|
(M0_AHBSLOT9ENABLE * (2**9)) +
|
402 |
|
|
(M0_AHBSLOT8ENABLE * (2**8)) +
|
403 |
|
|
(M0_AHBSLOT7ENABLE * (2**7)) +
|
404 |
|
|
(M0_AHBSLOT6ENABLE * (2**6)) +
|
405 |
|
|
(M0_AHBSLOT5ENABLE * (2**5)) +
|
406 |
|
|
(M0_AHBSLOT4ENABLE * (2**4)) +
|
407 |
|
|
(M0_AHBSLOT3ENABLE * (2**3)) +
|
408 |
|
|
(M0_AHBSLOT2ENABLE * (2**2)) +
|
409 |
|
|
(M0_AHBSLOT1ENABLE * (2**1)) +
|
410 |
|
|
(M0_AHBSLOT0ENABLE * (2**0)) ;
|
411 |
|
|
|
412 |
|
|
constant M1_AHBSLOTENABLE : integer :=
|
413 |
|
|
(M1_AHBSLOT16ENABLE * (2**16)) +
|
414 |
|
|
(M1_AHBSLOT15ENABLE * (2**15)) +
|
415 |
|
|
(M1_AHBSLOT14ENABLE * (2**14)) +
|
416 |
|
|
(M1_AHBSLOT13ENABLE * (2**13)) +
|
417 |
|
|
(M1_AHBSLOT12ENABLE * (2**12)) +
|
418 |
|
|
(M1_AHBSLOT11ENABLE * (2**11)) +
|
419 |
|
|
(M1_AHBSLOT10ENABLE * (2**10)) +
|
420 |
|
|
(M1_AHBSLOT9ENABLE * (2**9)) +
|
421 |
|
|
(M1_AHBSLOT8ENABLE * (2**8)) +
|
422 |
|
|
(M1_AHBSLOT7ENABLE * (2**7)) +
|
423 |
|
|
(M1_AHBSLOT6ENABLE * (2**6)) +
|
424 |
|
|
(M1_AHBSLOT5ENABLE * (2**5)) +
|
425 |
|
|
(M1_AHBSLOT4ENABLE * (2**4)) +
|
426 |
|
|
(M1_AHBSLOT3ENABLE * (2**3)) +
|
427 |
|
|
(M1_AHBSLOT2ENABLE * (2**2)) +
|
428 |
|
|
(M1_AHBSLOT1ENABLE * (2**1)) +
|
429 |
|
|
(M1_AHBSLOT0ENABLE * (2**0)) ;
|
430 |
|
|
|
431 |
|
|
constant M2_AHBSLOTENABLE : integer :=
|
432 |
|
|
(M2_AHBSLOT16ENABLE * (2**16)) +
|
433 |
|
|
(M2_AHBSLOT15ENABLE * (2**15)) +
|
434 |
|
|
(M2_AHBSLOT14ENABLE * (2**14)) +
|
435 |
|
|
(M2_AHBSLOT13ENABLE * (2**13)) +
|
436 |
|
|
(M2_AHBSLOT12ENABLE * (2**12)) +
|
437 |
|
|
(M2_AHBSLOT11ENABLE * (2**11)) +
|
438 |
|
|
(M2_AHBSLOT10ENABLE * (2**10)) +
|
439 |
|
|
(M2_AHBSLOT9ENABLE * (2**9)) +
|
440 |
|
|
(M2_AHBSLOT8ENABLE * (2**8)) +
|
441 |
|
|
(M2_AHBSLOT7ENABLE * (2**7)) +
|
442 |
|
|
(M2_AHBSLOT6ENABLE * (2**6)) +
|
443 |
|
|
(M2_AHBSLOT5ENABLE * (2**5)) +
|
444 |
|
|
(M2_AHBSLOT4ENABLE * (2**4)) +
|
445 |
|
|
(M2_AHBSLOT3ENABLE * (2**3)) +
|
446 |
|
|
(M2_AHBSLOT2ENABLE * (2**2)) +
|
447 |
|
|
(M2_AHBSLOT1ENABLE * (2**1)) +
|
448 |
|
|
(M2_AHBSLOT0ENABLE * (2**0)) ;
|
449 |
|
|
|
450 |
|
|
constant M3_AHBSLOTENABLE : integer :=
|
451 |
|
|
(M3_AHBSLOT16ENABLE * (2**16)) +
|
452 |
|
|
(M3_AHBSLOT15ENABLE * (2**15)) +
|
453 |
|
|
(M3_AHBSLOT14ENABLE * (2**14)) +
|
454 |
|
|
(M3_AHBSLOT13ENABLE * (2**13)) +
|
455 |
|
|
(M3_AHBSLOT12ENABLE * (2**12)) +
|
456 |
|
|
(M3_AHBSLOT11ENABLE * (2**11)) +
|
457 |
|
|
(M3_AHBSLOT10ENABLE * (2**10)) +
|
458 |
|
|
(M3_AHBSLOT9ENABLE * (2**9)) +
|
459 |
|
|
(M3_AHBSLOT8ENABLE * (2**8)) +
|
460 |
|
|
(M3_AHBSLOT7ENABLE * (2**7)) +
|
461 |
|
|
(M3_AHBSLOT6ENABLE * (2**6)) +
|
462 |
|
|
(M3_AHBSLOT5ENABLE * (2**5)) +
|
463 |
|
|
(M3_AHBSLOT4ENABLE * (2**4)) +
|
464 |
|
|
(M3_AHBSLOT3ENABLE * (2**3)) +
|
465 |
|
|
(M3_AHBSLOT2ENABLE * (2**2)) +
|
466 |
|
|
(M3_AHBSLOT1ENABLE * (2**1)) +
|
467 |
|
|
(M3_AHBSLOT0ENABLE * (2**0)) ;
|
468 |
|
|
|
469 |
|
|
constant SC : integer :=
|
470 |
|
|
(SC_15 * (2**15)) +
|
471 |
|
|
(SC_14 * (2**14)) +
|
472 |
|
|
(SC_13 * (2**13)) +
|
473 |
|
|
(SC_12 * (2**12)) +
|
474 |
|
|
(SC_11 * (2**11)) +
|
475 |
|
|
(SC_10 * (2**10)) +
|
476 |
|
|
(SC_9 * (2**9)) +
|
477 |
|
|
(SC_8 * (2**8)) +
|
478 |
|
|
(SC_7 * (2**7)) +
|
479 |
|
|
(SC_6 * (2**6)) +
|
480 |
|
|
(SC_5 * (2**5)) +
|
481 |
|
|
(SC_4 * (2**4)) +
|
482 |
|
|
(SC_3 * (2**3)) +
|
483 |
|
|
(SC_2 * (2**2)) +
|
484 |
|
|
(SC_1 * (2**1)) +
|
485 |
|
|
(SC_0 * (2**0)) ;
|
486 |
|
|
|
487 |
|
|
|
488 |
|
|
component COREAHBLITE_MATRIX4X16 is
|
489 |
|
|
generic (
|
490 |
|
|
MEMSPACE : integer range 0 to 6:= 0;
|
491 |
|
|
HADDR_SHG_CFG : integer range 0 to 1:= 0;
|
492 |
|
|
M0_AHBSLOTENABLE : integer range 0 to (2**17)-1:= (2**17)-1;
|
493 |
|
|
M1_AHBSLOTENABLE : integer range 0 to (2**17)-1:= (2**17)-1;
|
494 |
|
|
M2_AHBSLOTENABLE : integer range 0 to (2**17)-1:= (2**17)-1;
|
495 |
|
|
M3_AHBSLOTENABLE : integer range 0 to (2**17)-1:= (2**17)-1;
|
496 |
|
|
SC : integer range 0 to (2**16)-1:= 0;
|
497 |
|
|
SYNC_RESET : integer := 0
|
498 |
|
|
);
|
499 |
|
|
port (
|
500 |
|
|
HCLK : in std_logic;
|
501 |
|
|
HRESETN : in std_logic;
|
502 |
|
|
REMAP_M0 : in std_logic;
|
503 |
|
|
HADDR_M0 : in std_logic_vector(31 downto 0);
|
504 |
|
|
HMASTLOCK_M0 : in std_logic;
|
505 |
|
|
HSIZE_M0 : in std_logic_vector(2 downto 0);
|
506 |
|
|
HTRANS_M0 : in std_logic;
|
507 |
|
|
HWRITE_M0 : in std_logic;
|
508 |
|
|
HWDATA_M0 : in std_logic_vector(31 downto 0);
|
509 |
|
|
HRESP_M0 : out std_logic;
|
510 |
|
|
HRDATA_M0 : out std_logic_vector(31 downto 0);
|
511 |
|
|
HREADY_M0 : out std_logic;
|
512 |
|
|
HADDR_M1 : in std_logic_vector(31 downto 0);
|
513 |
|
|
HMASTLOCK_M1 : in std_logic;
|
514 |
|
|
HSIZE_M1 : in std_logic_vector(2 downto 0);
|
515 |
|
|
HTRANS_M1 : in std_logic;
|
516 |
|
|
HWRITE_M1 : in std_logic;
|
517 |
|
|
HWDATA_M1 : in std_logic_vector(31 downto 0);
|
518 |
|
|
HRESP_M1 : out std_logic;
|
519 |
|
|
HRDATA_M1 : out std_logic_vector(31 downto 0);
|
520 |
|
|
HREADY_M1 : out std_logic;
|
521 |
|
|
HADDR_M2 : in std_logic_vector(31 downto 0);
|
522 |
|
|
HMASTLOCK_M2 : in std_logic;
|
523 |
|
|
HSIZE_M2 : in std_logic_vector(2 downto 0);
|
524 |
|
|
HTRANS_M2 : in std_logic;
|
525 |
|
|
HWRITE_M2 : in std_logic;
|
526 |
|
|
HWDATA_M2 : in std_logic_vector(31 downto 0);
|
527 |
|
|
HRESP_M2 : out std_logic;
|
528 |
|
|
HRDATA_M2 : out std_logic_vector(31 downto 0);
|
529 |
|
|
HREADY_M2 : out std_logic;
|
530 |
|
|
HADDR_M3 : in std_logic_vector(31 downto 0);
|
531 |
|
|
HMASTLOCK_M3 : in std_logic;
|
532 |
|
|
HSIZE_M3 : in std_logic_vector(2 downto 0);
|
533 |
|
|
HTRANS_M3 : in std_logic;
|
534 |
|
|
HWRITE_M3 : in std_logic;
|
535 |
|
|
HWDATA_M3 : in std_logic_vector(31 downto 0);
|
536 |
|
|
HRESP_M3 : out std_logic;
|
537 |
|
|
HRDATA_M3 : out std_logic_vector(31 downto 0);
|
538 |
|
|
HREADY_M3 : out std_logic;
|
539 |
|
|
HRDATA_S0 : in std_logic_vector(31 downto 0);
|
540 |
|
|
HREADYOUT_S0 : in std_logic;
|
541 |
|
|
HRESP_S0 : in std_logic;
|
542 |
|
|
HSEL_S0 : out std_logic;
|
543 |
|
|
HADDR_S0 : out std_logic_vector(31 downto 0);
|
544 |
|
|
HSIZE_S0 : out std_logic_vector(2 downto 0);
|
545 |
|
|
HTRANS_S0 : out std_logic;
|
546 |
|
|
HWRITE_S0 : out std_logic;
|
547 |
|
|
HWDATA_S0 : out std_logic_vector(31 downto 0);
|
548 |
|
|
HREADY_S0 : out std_logic;
|
549 |
|
|
HMASTLOCK_S0 : out std_logic;
|
550 |
|
|
HRDATA_S1 : in std_logic_vector(31 downto 0);
|
551 |
|
|
HREADYOUT_S1 : in std_logic;
|
552 |
|
|
HRESP_S1 : in std_logic;
|
553 |
|
|
HSEL_S1 : out std_logic;
|
554 |
|
|
HADDR_S1 : out std_logic_vector(31 downto 0);
|
555 |
|
|
HSIZE_S1 : out std_logic_vector(2 downto 0);
|
556 |
|
|
HTRANS_S1 : out std_logic;
|
557 |
|
|
HWRITE_S1 : out std_logic;
|
558 |
|
|
HWDATA_S1 : out std_logic_vector(31 downto 0);
|
559 |
|
|
HREADY_S1 : out std_logic;
|
560 |
|
|
HMASTLOCK_S1 : out std_logic;
|
561 |
|
|
HRDATA_S2 : in std_logic_vector(31 downto 0);
|
562 |
|
|
HREADYOUT_S2 : in std_logic;
|
563 |
|
|
HRESP_S2 : in std_logic;
|
564 |
|
|
HSEL_S2 : out std_logic;
|
565 |
|
|
HADDR_S2 : out std_logic_vector(31 downto 0);
|
566 |
|
|
HSIZE_S2 : out std_logic_vector(2 downto 0);
|
567 |
|
|
HTRANS_S2 : out std_logic;
|
568 |
|
|
HWRITE_S2 : out std_logic;
|
569 |
|
|
HWDATA_S2 : out std_logic_vector(31 downto 0);
|
570 |
|
|
HREADY_S2 : out std_logic;
|
571 |
|
|
HMASTLOCK_S2 : out std_logic;
|
572 |
|
|
HRDATA_S3 : in std_logic_vector(31 downto 0);
|
573 |
|
|
HREADYOUT_S3 : in std_logic;
|
574 |
|
|
HRESP_S3 : in std_logic;
|
575 |
|
|
HSEL_S3 : out std_logic;
|
576 |
|
|
HADDR_S3 : out std_logic_vector(31 downto 0);
|
577 |
|
|
HSIZE_S3 : out std_logic_vector(2 downto 0);
|
578 |
|
|
HTRANS_S3 : out std_logic;
|
579 |
|
|
HWRITE_S3 : out std_logic;
|
580 |
|
|
HWDATA_S3 : out std_logic_vector(31 downto 0);
|
581 |
|
|
HREADY_S3 : out std_logic;
|
582 |
|
|
HMASTLOCK_S3 : out std_logic;
|
583 |
|
|
HRDATA_S4 : in std_logic_vector(31 downto 0);
|
584 |
|
|
HREADYOUT_S4 : in std_logic;
|
585 |
|
|
HRESP_S4 : in std_logic;
|
586 |
|
|
HSEL_S4 : out std_logic;
|
587 |
|
|
HADDR_S4 : out std_logic_vector(31 downto 0);
|
588 |
|
|
HSIZE_S4 : out std_logic_vector(2 downto 0);
|
589 |
|
|
HTRANS_S4 : out std_logic;
|
590 |
|
|
HWRITE_S4 : out std_logic;
|
591 |
|
|
HWDATA_S4 : out std_logic_vector(31 downto 0);
|
592 |
|
|
HREADY_S4 : out std_logic;
|
593 |
|
|
HMASTLOCK_S4 : out std_logic;
|
594 |
|
|
HRDATA_S5 : in std_logic_vector(31 downto 0);
|
595 |
|
|
HREADYOUT_S5 : in std_logic;
|
596 |
|
|
HRESP_S5 : in std_logic;
|
597 |
|
|
HSEL_S5 : out std_logic;
|
598 |
|
|
HADDR_S5 : out std_logic_vector(31 downto 0);
|
599 |
|
|
HSIZE_S5 : out std_logic_vector(2 downto 0);
|
600 |
|
|
HTRANS_S5 : out std_logic;
|
601 |
|
|
HWRITE_S5 : out std_logic;
|
602 |
|
|
HWDATA_S5 : out std_logic_vector(31 downto 0);
|
603 |
|
|
HREADY_S5 : out std_logic;
|
604 |
|
|
HMASTLOCK_S5 : out std_logic;
|
605 |
|
|
HRDATA_S6 : in std_logic_vector(31 downto 0);
|
606 |
|
|
HREADYOUT_S6 : in std_logic;
|
607 |
|
|
HRESP_S6 : in std_logic;
|
608 |
|
|
HSEL_S6 : out std_logic;
|
609 |
|
|
HADDR_S6 : out std_logic_vector(31 downto 0);
|
610 |
|
|
HSIZE_S6 : out std_logic_vector(2 downto 0);
|
611 |
|
|
HTRANS_S6 : out std_logic;
|
612 |
|
|
HWRITE_S6 : out std_logic;
|
613 |
|
|
HWDATA_S6 : out std_logic_vector(31 downto 0);
|
614 |
|
|
HREADY_S6 : out std_logic;
|
615 |
|
|
HMASTLOCK_S6 : out std_logic;
|
616 |
|
|
HRDATA_S7 : in std_logic_vector(31 downto 0);
|
617 |
|
|
HREADYOUT_S7 : in std_logic;
|
618 |
|
|
HRESP_S7 : in std_logic;
|
619 |
|
|
HSEL_S7 : out std_logic;
|
620 |
|
|
HADDR_S7 : out std_logic_vector(31 downto 0);
|
621 |
|
|
HSIZE_S7 : out std_logic_vector(2 downto 0);
|
622 |
|
|
HTRANS_S7 : out std_logic;
|
623 |
|
|
HWRITE_S7 : out std_logic;
|
624 |
|
|
HWDATA_S7 : out std_logic_vector(31 downto 0);
|
625 |
|
|
HREADY_S7 : out std_logic;
|
626 |
|
|
HMASTLOCK_S7 : out std_logic;
|
627 |
|
|
HRDATA_S8 : in std_logic_vector(31 downto 0);
|
628 |
|
|
HREADYOUT_S8 : in std_logic;
|
629 |
|
|
HRESP_S8 : in std_logic;
|
630 |
|
|
HSEL_S8 : out std_logic;
|
631 |
|
|
HADDR_S8 : out std_logic_vector(31 downto 0);
|
632 |
|
|
HSIZE_S8 : out std_logic_vector(2 downto 0);
|
633 |
|
|
HTRANS_S8 : out std_logic;
|
634 |
|
|
HWRITE_S8 : out std_logic;
|
635 |
|
|
HWDATA_S8 : out std_logic_vector(31 downto 0);
|
636 |
|
|
HREADY_S8 : out std_logic;
|
637 |
|
|
HMASTLOCK_S8 : out std_logic;
|
638 |
|
|
HRDATA_S9 : in std_logic_vector(31 downto 0);
|
639 |
|
|
HREADYOUT_S9 : in std_logic;
|
640 |
|
|
HRESP_S9 : in std_logic;
|
641 |
|
|
HSEL_S9 : out std_logic;
|
642 |
|
|
HADDR_S9 : out std_logic_vector(31 downto 0);
|
643 |
|
|
HSIZE_S9 : out std_logic_vector(2 downto 0);
|
644 |
|
|
HTRANS_S9 : out std_logic;
|
645 |
|
|
HWRITE_S9 : out std_logic;
|
646 |
|
|
HWDATA_S9 : out std_logic_vector(31 downto 0);
|
647 |
|
|
HREADY_S9 : out std_logic;
|
648 |
|
|
HMASTLOCK_S9 : out std_logic;
|
649 |
|
|
HRDATA_S10 : in std_logic_vector(31 downto 0);
|
650 |
|
|
HREADYOUT_S10 : in std_logic;
|
651 |
|
|
HRESP_S10 : in std_logic;
|
652 |
|
|
HSEL_S10 : out std_logic;
|
653 |
|
|
HADDR_S10 : out std_logic_vector(31 downto 0);
|
654 |
|
|
HSIZE_S10 : out std_logic_vector(2 downto 0);
|
655 |
|
|
HTRANS_S10 : out std_logic;
|
656 |
|
|
HWRITE_S10 : out std_logic;
|
657 |
|
|
HWDATA_S10 : out std_logic_vector(31 downto 0);
|
658 |
|
|
HREADY_S10 : out std_logic;
|
659 |
|
|
HMASTLOCK_S10 : out std_logic;
|
660 |
|
|
HRDATA_S11 : in std_logic_vector(31 downto 0);
|
661 |
|
|
HREADYOUT_S11 : in std_logic;
|
662 |
|
|
HRESP_S11 : in std_logic;
|
663 |
|
|
HSEL_S11 : out std_logic;
|
664 |
|
|
HADDR_S11 : out std_logic_vector(31 downto 0);
|
665 |
|
|
HSIZE_S11 : out std_logic_vector(2 downto 0);
|
666 |
|
|
HTRANS_S11 : out std_logic;
|
667 |
|
|
HWRITE_S11 : out std_logic;
|
668 |
|
|
HWDATA_S11 : out std_logic_vector(31 downto 0);
|
669 |
|
|
HREADY_S11 : out std_logic;
|
670 |
|
|
HMASTLOCK_S11 : out std_logic;
|
671 |
|
|
HRDATA_S12 : in std_logic_vector(31 downto 0);
|
672 |
|
|
HREADYOUT_S12 : in std_logic;
|
673 |
|
|
HRESP_S12 : in std_logic;
|
674 |
|
|
HSEL_S12 : out std_logic;
|
675 |
|
|
HADDR_S12 : out std_logic_vector(31 downto 0);
|
676 |
|
|
HSIZE_S12 : out std_logic_vector(2 downto 0);
|
677 |
|
|
HTRANS_S12 : out std_logic;
|
678 |
|
|
HWRITE_S12 : out std_logic;
|
679 |
|
|
HWDATA_S12 : out std_logic_vector(31 downto 0);
|
680 |
|
|
HREADY_S12 : out std_logic;
|
681 |
|
|
HMASTLOCK_S12 : out std_logic;
|
682 |
|
|
HRDATA_S13 : in std_logic_vector(31 downto 0);
|
683 |
|
|
HREADYOUT_S13 : in std_logic;
|
684 |
|
|
HRESP_S13 : in std_logic;
|
685 |
|
|
HSEL_S13 : out std_logic;
|
686 |
|
|
HADDR_S13 : out std_logic_vector(31 downto 0);
|
687 |
|
|
HSIZE_S13 : out std_logic_vector(2 downto 0);
|
688 |
|
|
HTRANS_S13 : out std_logic;
|
689 |
|
|
HWRITE_S13 : out std_logic;
|
690 |
|
|
HWDATA_S13 : out std_logic_vector(31 downto 0);
|
691 |
|
|
HREADY_S13 : out std_logic;
|
692 |
|
|
HMASTLOCK_S13 : out std_logic;
|
693 |
|
|
HRDATA_S14 : in std_logic_vector(31 downto 0);
|
694 |
|
|
HREADYOUT_S14 : in std_logic;
|
695 |
|
|
HRESP_S14 : in std_logic;
|
696 |
|
|
HSEL_S14 : out std_logic;
|
697 |
|
|
HADDR_S14 : out std_logic_vector(31 downto 0);
|
698 |
|
|
HSIZE_S14 : out std_logic_vector(2 downto 0);
|
699 |
|
|
HTRANS_S14 : out std_logic;
|
700 |
|
|
HWRITE_S14 : out std_logic;
|
701 |
|
|
HWDATA_S14 : out std_logic_vector(31 downto 0);
|
702 |
|
|
HREADY_S14 : out std_logic;
|
703 |
|
|
HMASTLOCK_S14 : out std_logic;
|
704 |
|
|
HRDATA_S15 : in std_logic_vector(31 downto 0);
|
705 |
|
|
HREADYOUT_S15 : in std_logic;
|
706 |
|
|
HRESP_S15 : in std_logic;
|
707 |
|
|
HSEL_S15 : out std_logic;
|
708 |
|
|
HADDR_S15 : out std_logic_vector(31 downto 0);
|
709 |
|
|
HSIZE_S15 : out std_logic_vector(2 downto 0);
|
710 |
|
|
HTRANS_S15 : out std_logic;
|
711 |
|
|
HWRITE_S15 : out std_logic;
|
712 |
|
|
HWDATA_S15 : out std_logic_vector(31 downto 0);
|
713 |
|
|
HREADY_S15 : out std_logic;
|
714 |
|
|
HMASTLOCK_S15 : out std_logic;
|
715 |
|
|
HRDATA_S16 : in std_logic_vector(31 downto 0);
|
716 |
|
|
HREADYOUT_S16 : in std_logic;
|
717 |
|
|
HRESP_S16 : in std_logic;
|
718 |
|
|
HSEL_S16 : out std_logic;
|
719 |
|
|
HADDR_S16 : out std_logic_vector(31 downto 0);
|
720 |
|
|
HSIZE_S16 : out std_logic_vector(2 downto 0);
|
721 |
|
|
HTRANS_S16 : out std_logic;
|
722 |
|
|
HWRITE_S16 : out std_logic;
|
723 |
|
|
HWDATA_S16 : out std_logic_vector(31 downto 0);
|
724 |
|
|
HREADY_S16 : out std_logic;
|
725 |
|
|
HMASTLOCK_S16 : out std_logic
|
726 |
|
|
);
|
727 |
|
|
end component;
|
728 |
|
|
|
729 |
|
|
-- Declare intermediate signals for referenced outputs
|
730 |
|
|
signal HRESP_M0_xhdl54 : std_logic_vector(1 downto 0);
|
731 |
|
|
signal HRDATA_M0_xhdl33 : std_logic_vector(31 downto 0);
|
732 |
|
|
signal HREADY_M0_xhdl35 : std_logic;
|
733 |
|
|
signal HRESP_M1_xhdl55 : std_logic_vector(1 downto 0);
|
734 |
|
|
signal HRDATA_M1_xhdl34 : std_logic_vector(31 downto 0);
|
735 |
|
|
signal HREADY_M1_xhdl36 : std_logic;
|
736 |
|
|
signal HRESP_M2_xhdl54 : std_logic_vector(1 downto 0);
|
737 |
|
|
signal HRDATA_M2_xhdl33 : std_logic_vector(31 downto 0);
|
738 |
|
|
signal HREADY_M2_xhdl35 : std_logic;
|
739 |
|
|
signal HRESP_M3_xhdl55 : std_logic_vector(1 downto 0);
|
740 |
|
|
signal HRDATA_M3_xhdl34 : std_logic_vector(31 downto 0);
|
741 |
|
|
signal HREADY_M3_xhdl36 : std_logic;
|
742 |
|
|
signal HSEL_S0_xhdl56 : std_logic;
|
743 |
|
|
signal HADDR_S0_xhdl0 : std_logic_vector(31 downto 0);
|
744 |
|
|
signal HSIZE_S0_xhdl73 : std_logic_vector(2 downto 0);
|
745 |
|
|
signal HTRANS_S0_xhdl90 : std_logic_vector(1 downto 0);
|
746 |
|
|
signal HWRITE_S0_xhdl124 : std_logic;
|
747 |
|
|
signal HWDATA_S0_xhdl107 : std_logic_vector(31 downto 0);
|
748 |
|
|
signal HREADY_S0_xhdl37 : std_logic;
|
749 |
|
|
signal HMASTLOCK_S0_xhdl16 : std_logic;
|
750 |
|
|
signal HSEL_S1_xhdl57 : std_logic;
|
751 |
|
|
signal HADDR_S1_xhdl1 : std_logic_vector(31 downto 0);
|
752 |
|
|
signal HSIZE_S1_xhdl74 : std_logic_vector(2 downto 0);
|
753 |
|
|
signal HTRANS_S1_xhdl91 : std_logic_vector(1 downto 0);
|
754 |
|
|
signal HWRITE_S1_xhdl125 : std_logic;
|
755 |
|
|
signal HWDATA_S1_xhdl108 : std_logic_vector(31 downto 0);
|
756 |
|
|
signal HREADY_S1_xhdl38 : std_logic;
|
757 |
|
|
signal HMASTLOCK_S1_xhdl17 : std_logic;
|
758 |
|
|
signal HSEL_S2_xhdl64 : std_logic;
|
759 |
|
|
signal HADDR_S2_xhdl8 : std_logic_vector(31 downto 0);
|
760 |
|
|
signal HSIZE_S2_xhdl81 : std_logic_vector(2 downto 0);
|
761 |
|
|
signal HTRANS_S2_xhdl98 : std_logic_vector(1 downto 0);
|
762 |
|
|
signal HWRITE_S2_xhdl132 : std_logic;
|
763 |
|
|
signal HWDATA_S2_xhdl115 : std_logic_vector(31 downto 0);
|
764 |
|
|
signal HREADY_S2_xhdl45 : std_logic;
|
765 |
|
|
signal HMASTLOCK_S2_xhdl24 : std_logic;
|
766 |
|
|
signal HSEL_S3_xhdl65 : std_logic;
|
767 |
|
|
signal HADDR_S3_xhdl9 : std_logic_vector(31 downto 0);
|
768 |
|
|
signal HSIZE_S3_xhdl82 : std_logic_vector(2 downto 0);
|
769 |
|
|
signal HTRANS_S3_xhdl99 : std_logic_vector(1 downto 0);
|
770 |
|
|
signal HWRITE_S3_xhdl133 : std_logic;
|
771 |
|
|
signal HWDATA_S3_xhdl116 : std_logic_vector(31 downto 0);
|
772 |
|
|
signal HREADY_S3_xhdl46 : std_logic;
|
773 |
|
|
signal HMASTLOCK_S3_xhdl25 : std_logic;
|
774 |
|
|
signal HSEL_S4_xhdl66 : std_logic;
|
775 |
|
|
signal HADDR_S4_xhdl10 : std_logic_vector(31 downto 0);
|
776 |
|
|
signal HSIZE_S4_xhdl83 : std_logic_vector(2 downto 0);
|
777 |
|
|
signal HTRANS_S4_xhdl100 : std_logic_vector(1 downto 0);
|
778 |
|
|
signal HWRITE_S4_xhdl134 : std_logic;
|
779 |
|
|
signal HWDATA_S4_xhdl117 : std_logic_vector(31 downto 0);
|
780 |
|
|
signal HREADY_S4_xhdl47 : std_logic;
|
781 |
|
|
signal HMASTLOCK_S4_xhdl26 : std_logic;
|
782 |
|
|
signal HSEL_S5_xhdl67 : std_logic;
|
783 |
|
|
signal HADDR_S5_xhdl11 : std_logic_vector(31 downto 0);
|
784 |
|
|
signal HSIZE_S5_xhdl84 : std_logic_vector(2 downto 0);
|
785 |
|
|
signal HTRANS_S5_xhdl101 : std_logic_vector(1 downto 0);
|
786 |
|
|
signal HWRITE_S5_xhdl135 : std_logic;
|
787 |
|
|
signal HWDATA_S5_xhdl118 : std_logic_vector(31 downto 0);
|
788 |
|
|
signal HREADY_S5_xhdl48 : std_logic;
|
789 |
|
|
signal HMASTLOCK_S5_xhdl27 : std_logic;
|
790 |
|
|
signal HSEL_S6_xhdl68 : std_logic;
|
791 |
|
|
signal HADDR_S6_xhdl12 : std_logic_vector(31 downto 0);
|
792 |
|
|
signal HSIZE_S6_xhdl85 : std_logic_vector(2 downto 0);
|
793 |
|
|
signal HTRANS_S6_xhdl102 : std_logic_vector(1 downto 0);
|
794 |
|
|
signal HWRITE_S6_xhdl136 : std_logic;
|
795 |
|
|
signal HWDATA_S6_xhdl119 : std_logic_vector(31 downto 0);
|
796 |
|
|
signal HREADY_S6_xhdl49 : std_logic;
|
797 |
|
|
signal HMASTLOCK_S6_xhdl28 : std_logic;
|
798 |
|
|
signal HSEL_S7_xhdl69 : std_logic;
|
799 |
|
|
signal HADDR_S7_xhdl13 : std_logic_vector(31 downto 0);
|
800 |
|
|
signal HSIZE_S7_xhdl86 : std_logic_vector(2 downto 0);
|
801 |
|
|
signal HTRANS_S7_xhdl103 : std_logic_vector(1 downto 0);
|
802 |
|
|
signal HWRITE_S7_xhdl137 : std_logic;
|
803 |
|
|
signal HWDATA_S7_xhdl120 : std_logic_vector(31 downto 0);
|
804 |
|
|
signal HREADY_S7_xhdl50 : std_logic;
|
805 |
|
|
signal HMASTLOCK_S7_xhdl29 : std_logic;
|
806 |
|
|
signal HSEL_S8_xhdl70 : std_logic;
|
807 |
|
|
signal HADDR_S8_xhdl14 : std_logic_vector(31 downto 0);
|
808 |
|
|
signal HSIZE_S8_xhdl87 : std_logic_vector(2 downto 0);
|
809 |
|
|
signal HTRANS_S8_xhdl104 : std_logic_vector(1 downto 0);
|
810 |
|
|
signal HWRITE_S8_xhdl138 : std_logic;
|
811 |
|
|
signal HWDATA_S8_xhdl121 : std_logic_vector(31 downto 0);
|
812 |
|
|
signal HREADY_S8_xhdl51 : std_logic;
|
813 |
|
|
signal HMASTLOCK_S8_xhdl30 : std_logic;
|
814 |
|
|
signal HSEL_S9_xhdl71 : std_logic;
|
815 |
|
|
signal HADDR_S9_xhdl15 : std_logic_vector(31 downto 0);
|
816 |
|
|
signal HSIZE_S9_xhdl88 : std_logic_vector(2 downto 0);
|
817 |
|
|
signal HTRANS_S9_xhdl105 : std_logic_vector(1 downto 0);
|
818 |
|
|
signal HWRITE_S9_xhdl139 : std_logic;
|
819 |
|
|
signal HWDATA_S9_xhdl122 : std_logic_vector(31 downto 0);
|
820 |
|
|
signal HREADY_S9_xhdl52 : std_logic;
|
821 |
|
|
signal HMASTLOCK_S9_xhdl31 : std_logic;
|
822 |
|
|
signal HSEL_S10_xhdl58 : std_logic;
|
823 |
|
|
signal HADDR_S10_xhdl2 : std_logic_vector(31 downto 0);
|
824 |
|
|
signal HSIZE_S10_xhdl75 : std_logic_vector(2 downto 0);
|
825 |
|
|
signal HTRANS_S10_xhdl92 : std_logic_vector(1 downto 0);
|
826 |
|
|
signal HWRITE_S10_xhdl126 : std_logic;
|
827 |
|
|
signal HWDATA_S10_xhdl109 : std_logic_vector(31 downto 0);
|
828 |
|
|
signal HREADY_S10_xhdl39 : std_logic;
|
829 |
|
|
signal HMASTLOCK_S10_xhdl18 : std_logic;
|
830 |
|
|
signal HSEL_S11_xhdl59 : std_logic;
|
831 |
|
|
signal HADDR_S11_xhdl3 : std_logic_vector(31 downto 0);
|
832 |
|
|
signal HSIZE_S11_xhdl76 : std_logic_vector(2 downto 0);
|
833 |
|
|
signal HTRANS_S11_xhdl93 : std_logic_vector(1 downto 0);
|
834 |
|
|
signal HWRITE_S11_xhdl127 : std_logic;
|
835 |
|
|
signal HWDATA_S11_xhdl110 : std_logic_vector(31 downto 0);
|
836 |
|
|
signal HREADY_S11_xhdl40 : std_logic;
|
837 |
|
|
signal HMASTLOCK_S11_xhdl19 : std_logic;
|
838 |
|
|
signal HSEL_S12_xhdl60 : std_logic;
|
839 |
|
|
signal HADDR_S12_xhdl4 : std_logic_vector(31 downto 0);
|
840 |
|
|
signal HSIZE_S12_xhdl77 : std_logic_vector(2 downto 0);
|
841 |
|
|
signal HTRANS_S12_xhdl94 : std_logic_vector(1 downto 0);
|
842 |
|
|
signal HWRITE_S12_xhdl128 : std_logic;
|
843 |
|
|
signal HWDATA_S12_xhdl111 : std_logic_vector(31 downto 0);
|
844 |
|
|
signal HREADY_S12_xhdl41 : std_logic;
|
845 |
|
|
signal HMASTLOCK_S12_xhdl20 : std_logic;
|
846 |
|
|
signal HSEL_S13_xhdl61 : std_logic;
|
847 |
|
|
signal HADDR_S13_xhdl5 : std_logic_vector(31 downto 0);
|
848 |
|
|
signal HSIZE_S13_xhdl78 : std_logic_vector(2 downto 0);
|
849 |
|
|
signal HTRANS_S13_xhdl95 : std_logic_vector(1 downto 0);
|
850 |
|
|
signal HWRITE_S13_xhdl129 : std_logic;
|
851 |
|
|
signal HWDATA_S13_xhdl112 : std_logic_vector(31 downto 0);
|
852 |
|
|
signal HREADY_S13_xhdl42 : std_logic;
|
853 |
|
|
signal HMASTLOCK_S13_xhdl21 : std_logic;
|
854 |
|
|
signal HSEL_S14_xhdl62 : std_logic;
|
855 |
|
|
signal HADDR_S14_xhdl6 : std_logic_vector(31 downto 0);
|
856 |
|
|
signal HSIZE_S14_xhdl79 : std_logic_vector(2 downto 0);
|
857 |
|
|
signal HTRANS_S14_xhdl96 : std_logic_vector(1 downto 0);
|
858 |
|
|
signal HWRITE_S14_xhdl130 : std_logic;
|
859 |
|
|
signal HWDATA_S14_xhdl113 : std_logic_vector(31 downto 0);
|
860 |
|
|
signal HREADY_S14_xhdl43 : std_logic;
|
861 |
|
|
signal HMASTLOCK_S14_xhdl22 : std_logic;
|
862 |
|
|
signal HSEL_S15_xhdl63 : std_logic;
|
863 |
|
|
signal HADDR_S15_xhdl7 : std_logic_vector(31 downto 0);
|
864 |
|
|
signal HSIZE_S15_xhdl80 : std_logic_vector(2 downto 0);
|
865 |
|
|
signal HTRANS_S15_xhdl97 : std_logic_vector(1 downto 0);
|
866 |
|
|
signal HWRITE_S15_xhdl131 : std_logic;
|
867 |
|
|
signal HWDATA_S15_xhdl114 : std_logic_vector(31 downto 0);
|
868 |
|
|
signal HREADY_S15_xhdl44 : std_logic;
|
869 |
|
|
signal HMASTLOCK_S15_xhdl23 : std_logic;
|
870 |
|
|
signal HSEL_S16_xhdl72 : std_logic;
|
871 |
|
|
signal HSIZE_S16_xhdl89 : std_logic_vector(2 downto 0);
|
872 |
|
|
signal HTRANS_S16_xhdl106 : std_logic_vector(1 downto 0);
|
873 |
|
|
signal HWRITE_S16_xhdl140 : std_logic;
|
874 |
|
|
signal HWDATA_S16_xhdl123 : std_logic_vector(31 downto 0);
|
875 |
|
|
signal HREADY_S16_xhdl53 : std_logic;
|
876 |
|
|
signal HMASTLOCK_S16_xhdl32 : std_logic;
|
877 |
|
|
begin
|
878 |
|
|
-- Drive referenced outputs
|
879 |
|
|
HRESP_M0 <= HRESP_M0_xhdl54;
|
880 |
|
|
HRDATA_M0 <= HRDATA_M0_xhdl33;
|
881 |
|
|
HREADY_M0 <= HREADY_M0_xhdl35;
|
882 |
|
|
HRESP_M1 <= HRESP_M1_xhdl55;
|
883 |
|
|
HRDATA_M1 <= HRDATA_M1_xhdl34;
|
884 |
|
|
HREADY_M1 <= HREADY_M1_xhdl36;
|
885 |
|
|
HRESP_M2 <= HRESP_M2_xhdl54;
|
886 |
|
|
HRDATA_M2 <= HRDATA_M2_xhdl33;
|
887 |
|
|
HREADY_M2 <= HREADY_M2_xhdl35;
|
888 |
|
|
HRESP_M3 <= HRESP_M3_xhdl55;
|
889 |
|
|
HRDATA_M3 <= HRDATA_M3_xhdl34;
|
890 |
|
|
HREADY_M3 <= HREADY_M3_xhdl36;
|
891 |
|
|
HSEL_S0 <= HSEL_S0_xhdl56;
|
892 |
|
|
HADDR_S0 <= HADDR_S0_xhdl0;
|
893 |
|
|
HSIZE_S0 <= HSIZE_S0_xhdl73;
|
894 |
|
|
HTRANS_S0 <= HTRANS_S0_xhdl90;
|
895 |
|
|
HWRITE_S0 <= HWRITE_S0_xhdl124;
|
896 |
|
|
HWDATA_S0 <= HWDATA_S0_xhdl107;
|
897 |
|
|
HREADY_S0 <= HREADY_S0_xhdl37;
|
898 |
|
|
HMASTLOCK_S0 <= HMASTLOCK_S0_xhdl16;
|
899 |
|
|
HSEL_S1 <= HSEL_S1_xhdl57;
|
900 |
|
|
HADDR_S1 <= HADDR_S1_xhdl1;
|
901 |
|
|
HSIZE_S1 <= HSIZE_S1_xhdl74;
|
902 |
|
|
HTRANS_S1 <= HTRANS_S1_xhdl91;
|
903 |
|
|
HWRITE_S1 <= HWRITE_S1_xhdl125;
|
904 |
|
|
HWDATA_S1 <= HWDATA_S1_xhdl108;
|
905 |
|
|
HREADY_S1 <= HREADY_S1_xhdl38;
|
906 |
|
|
HMASTLOCK_S1 <= HMASTLOCK_S1_xhdl17;
|
907 |
|
|
HSEL_S2 <= HSEL_S2_xhdl64;
|
908 |
|
|
HADDR_S2 <= HADDR_S2_xhdl8;
|
909 |
|
|
HSIZE_S2 <= HSIZE_S2_xhdl81;
|
910 |
|
|
HTRANS_S2 <= HTRANS_S2_xhdl98;
|
911 |
|
|
HWRITE_S2 <= HWRITE_S2_xhdl132;
|
912 |
|
|
HWDATA_S2 <= HWDATA_S2_xhdl115;
|
913 |
|
|
HREADY_S2 <= HREADY_S2_xhdl45;
|
914 |
|
|
HMASTLOCK_S2 <= HMASTLOCK_S2_xhdl24;
|
915 |
|
|
HSEL_S3 <= HSEL_S3_xhdl65;
|
916 |
|
|
HADDR_S3 <= HADDR_S3_xhdl9;
|
917 |
|
|
HSIZE_S3 <= HSIZE_S3_xhdl82;
|
918 |
|
|
HTRANS_S3 <= HTRANS_S3_xhdl99;
|
919 |
|
|
HWRITE_S3 <= HWRITE_S3_xhdl133;
|
920 |
|
|
HWDATA_S3 <= HWDATA_S3_xhdl116;
|
921 |
|
|
HREADY_S3 <= HREADY_S3_xhdl46;
|
922 |
|
|
HMASTLOCK_S3 <= HMASTLOCK_S3_xhdl25;
|
923 |
|
|
HSEL_S4 <= HSEL_S4_xhdl66;
|
924 |
|
|
HADDR_S4 <= HADDR_S4_xhdl10;
|
925 |
|
|
HSIZE_S4 <= HSIZE_S4_xhdl83;
|
926 |
|
|
HTRANS_S4 <= HTRANS_S4_xhdl100;
|
927 |
|
|
HWRITE_S4 <= HWRITE_S4_xhdl134;
|
928 |
|
|
HWDATA_S4 <= HWDATA_S4_xhdl117;
|
929 |
|
|
HREADY_S4 <= HREADY_S4_xhdl47;
|
930 |
|
|
HMASTLOCK_S4 <= HMASTLOCK_S4_xhdl26;
|
931 |
|
|
HSEL_S5 <= HSEL_S5_xhdl67;
|
932 |
|
|
HADDR_S5 <= HADDR_S5_xhdl11;
|
933 |
|
|
HSIZE_S5 <= HSIZE_S5_xhdl84;
|
934 |
|
|
HTRANS_S5 <= HTRANS_S5_xhdl101;
|
935 |
|
|
HWRITE_S5 <= HWRITE_S5_xhdl135;
|
936 |
|
|
HWDATA_S5 <= HWDATA_S5_xhdl118;
|
937 |
|
|
HREADY_S5 <= HREADY_S5_xhdl48;
|
938 |
|
|
HMASTLOCK_S5 <= HMASTLOCK_S5_xhdl27;
|
939 |
|
|
HSEL_S6 <= HSEL_S6_xhdl68;
|
940 |
|
|
HADDR_S6 <= HADDR_S6_xhdl12;
|
941 |
|
|
HSIZE_S6 <= HSIZE_S6_xhdl85;
|
942 |
|
|
HTRANS_S6 <= HTRANS_S6_xhdl102;
|
943 |
|
|
HWRITE_S6 <= HWRITE_S6_xhdl136;
|
944 |
|
|
HWDATA_S6 <= HWDATA_S6_xhdl119;
|
945 |
|
|
HREADY_S6 <= HREADY_S6_xhdl49;
|
946 |
|
|
HMASTLOCK_S6 <= HMASTLOCK_S6_xhdl28;
|
947 |
|
|
HSEL_S7 <= HSEL_S7_xhdl69;
|
948 |
|
|
HADDR_S7 <= HADDR_S7_xhdl13;
|
949 |
|
|
HSIZE_S7 <= HSIZE_S7_xhdl86;
|
950 |
|
|
HTRANS_S7 <= HTRANS_S7_xhdl103;
|
951 |
|
|
HWRITE_S7 <= HWRITE_S7_xhdl137;
|
952 |
|
|
HWDATA_S7 <= HWDATA_S7_xhdl120;
|
953 |
|
|
HREADY_S7 <= HREADY_S7_xhdl50;
|
954 |
|
|
HMASTLOCK_S7 <= HMASTLOCK_S7_xhdl29;
|
955 |
|
|
HSEL_S8 <= HSEL_S8_xhdl70;
|
956 |
|
|
HADDR_S8 <= HADDR_S8_xhdl14;
|
957 |
|
|
HSIZE_S8 <= HSIZE_S8_xhdl87;
|
958 |
|
|
HTRANS_S8 <= HTRANS_S8_xhdl104;
|
959 |
|
|
HWRITE_S8 <= HWRITE_S8_xhdl138;
|
960 |
|
|
HWDATA_S8 <= HWDATA_S8_xhdl121;
|
961 |
|
|
HREADY_S8 <= HREADY_S8_xhdl51;
|
962 |
|
|
HMASTLOCK_S8 <= HMASTLOCK_S8_xhdl30;
|
963 |
|
|
HSEL_S9 <= HSEL_S9_xhdl71;
|
964 |
|
|
HADDR_S9 <= HADDR_S9_xhdl15;
|
965 |
|
|
HSIZE_S9 <= HSIZE_S9_xhdl88;
|
966 |
|
|
HTRANS_S9 <= HTRANS_S9_xhdl105;
|
967 |
|
|
HWRITE_S9 <= HWRITE_S9_xhdl139;
|
968 |
|
|
HWDATA_S9 <= HWDATA_S9_xhdl122;
|
969 |
|
|
HREADY_S9 <= HREADY_S9_xhdl52;
|
970 |
|
|
HMASTLOCK_S9 <= HMASTLOCK_S9_xhdl31;
|
971 |
|
|
HSEL_S10 <= HSEL_S10_xhdl58;
|
972 |
|
|
HADDR_S10 <= HADDR_S10_xhdl2;
|
973 |
|
|
HSIZE_S10 <= HSIZE_S10_xhdl75;
|
974 |
|
|
HTRANS_S10 <= HTRANS_S10_xhdl92;
|
975 |
|
|
HWRITE_S10 <= HWRITE_S10_xhdl126;
|
976 |
|
|
HWDATA_S10 <= HWDATA_S10_xhdl109;
|
977 |
|
|
HREADY_S10 <= HREADY_S10_xhdl39;
|
978 |
|
|
HMASTLOCK_S10 <= HMASTLOCK_S10_xhdl18;
|
979 |
|
|
HSEL_S11 <= HSEL_S11_xhdl59;
|
980 |
|
|
HADDR_S11 <= HADDR_S11_xhdl3;
|
981 |
|
|
HSIZE_S11 <= HSIZE_S11_xhdl76;
|
982 |
|
|
HTRANS_S11 <= HTRANS_S11_xhdl93;
|
983 |
|
|
HWRITE_S11 <= HWRITE_S11_xhdl127;
|
984 |
|
|
HWDATA_S11 <= HWDATA_S11_xhdl110;
|
985 |
|
|
HREADY_S11 <= HREADY_S11_xhdl40;
|
986 |
|
|
HMASTLOCK_S11 <= HMASTLOCK_S11_xhdl19;
|
987 |
|
|
HSEL_S12 <= HSEL_S12_xhdl60;
|
988 |
|
|
HADDR_S12 <= HADDR_S12_xhdl4;
|
989 |
|
|
HSIZE_S12 <= HSIZE_S12_xhdl77;
|
990 |
|
|
HTRANS_S12 <= HTRANS_S12_xhdl94;
|
991 |
|
|
HWRITE_S12 <= HWRITE_S12_xhdl128;
|
992 |
|
|
HWDATA_S12 <= HWDATA_S12_xhdl111;
|
993 |
|
|
HREADY_S12 <= HREADY_S12_xhdl41;
|
994 |
|
|
HMASTLOCK_S12 <= HMASTLOCK_S12_xhdl20;
|
995 |
|
|
HSEL_S13 <= HSEL_S13_xhdl61;
|
996 |
|
|
HADDR_S13 <= HADDR_S13_xhdl5;
|
997 |
|
|
HSIZE_S13 <= HSIZE_S13_xhdl78;
|
998 |
|
|
HTRANS_S13 <= HTRANS_S13_xhdl95;
|
999 |
|
|
HWRITE_S13 <= HWRITE_S13_xhdl129;
|
1000 |
|
|
HWDATA_S13 <= HWDATA_S13_xhdl112;
|
1001 |
|
|
HREADY_S13 <= HREADY_S13_xhdl42;
|
1002 |
|
|
HMASTLOCK_S13 <= HMASTLOCK_S13_xhdl21;
|
1003 |
|
|
HSEL_S14 <= HSEL_S14_xhdl62;
|
1004 |
|
|
HADDR_S14 <= HADDR_S14_xhdl6;
|
1005 |
|
|
HSIZE_S14 <= HSIZE_S14_xhdl79;
|
1006 |
|
|
HTRANS_S14 <= HTRANS_S14_xhdl96;
|
1007 |
|
|
HWRITE_S14 <= HWRITE_S14_xhdl130;
|
1008 |
|
|
HWDATA_S14 <= HWDATA_S14_xhdl113;
|
1009 |
|
|
HREADY_S14 <= HREADY_S14_xhdl43;
|
1010 |
|
|
HMASTLOCK_S14 <= HMASTLOCK_S14_xhdl22;
|
1011 |
|
|
HSEL_S15 <= HSEL_S15_xhdl63;
|
1012 |
|
|
HADDR_S15 <= HADDR_S15_xhdl7;
|
1013 |
|
|
HSIZE_S15 <= HSIZE_S15_xhdl80;
|
1014 |
|
|
HTRANS_S15 <= HTRANS_S15_xhdl97;
|
1015 |
|
|
HWRITE_S15 <= HWRITE_S15_xhdl131;
|
1016 |
|
|
HWDATA_S15 <= HWDATA_S15_xhdl114;
|
1017 |
|
|
HREADY_S15 <= HREADY_S15_xhdl44;
|
1018 |
|
|
HMASTLOCK_S15 <= HMASTLOCK_S15_xhdl23;
|
1019 |
|
|
HSEL_S16 <= HSEL_S16_xhdl72;
|
1020 |
|
|
HSIZE_S16 <= HSIZE_S16_xhdl89;
|
1021 |
|
|
HTRANS_S16 <= HTRANS_S16_xhdl106;
|
1022 |
|
|
HWRITE_S16 <= HWRITE_S16_xhdl140;
|
1023 |
|
|
HWDATA_S16 <= HWDATA_S16_xhdl123;
|
1024 |
|
|
HREADY_S16 <= HREADY_S16_xhdl53;
|
1025 |
|
|
HMASTLOCK_S16 <= HMASTLOCK_S16_xhdl32;
|
1026 |
|
|
HTRANS_S0_xhdl90(0) <= '0';
|
1027 |
|
|
HTRANS_S1_xhdl91(0) <= '0';
|
1028 |
|
|
HTRANS_S2_xhdl98(0) <= '0';
|
1029 |
|
|
HTRANS_S3_xhdl99(0) <= '0';
|
1030 |
|
|
HTRANS_S4_xhdl100(0) <= '0';
|
1031 |
|
|
HTRANS_S5_xhdl101(0) <= '0';
|
1032 |
|
|
HTRANS_S6_xhdl102(0) <= '0';
|
1033 |
|
|
HTRANS_S7_xhdl103(0) <= '0';
|
1034 |
|
|
HTRANS_S8_xhdl104(0) <= '0';
|
1035 |
|
|
HTRANS_S9_xhdl105(0) <= '0';
|
1036 |
|
|
HTRANS_S10_xhdl92(0) <= '0';
|
1037 |
|
|
HTRANS_S11_xhdl93(0) <= '0';
|
1038 |
|
|
HTRANS_S12_xhdl94(0) <= '0';
|
1039 |
|
|
HTRANS_S13_xhdl95(0) <= '0';
|
1040 |
|
|
HTRANS_S14_xhdl96(0) <= '0';
|
1041 |
|
|
HTRANS_S15_xhdl97(0) <= '0';
|
1042 |
|
|
HTRANS_S16_xhdl106(0) <= '0';
|
1043 |
|
|
HRESP_M0_xhdl54(1) <= '0';
|
1044 |
|
|
HRESP_M1_xhdl55(1) <= '0';
|
1045 |
|
|
HRESP_M2_xhdl54(1) <= '0';
|
1046 |
|
|
HRESP_M3_xhdl55(1) <= '0';
|
1047 |
|
|
HBURST_S0 <= "000";
|
1048 |
|
|
HBURST_S1 <= "000";
|
1049 |
|
|
HBURST_S2 <= "000";
|
1050 |
|
|
HBURST_S3 <= "000";
|
1051 |
|
|
HBURST_S4 <= "000";
|
1052 |
|
|
HBURST_S5 <= "000";
|
1053 |
|
|
HBURST_S6 <= "000";
|
1054 |
|
|
HBURST_S7 <= "000";
|
1055 |
|
|
HBURST_S8 <= "000";
|
1056 |
|
|
HBURST_S9 <= "000";
|
1057 |
|
|
HBURST_S10 <= "000";
|
1058 |
|
|
HBURST_S11 <= "000";
|
1059 |
|
|
HBURST_S12 <= "000";
|
1060 |
|
|
HBURST_S13 <= "000";
|
1061 |
|
|
HBURST_S14 <= "000";
|
1062 |
|
|
HBURST_S15 <= "000";
|
1063 |
|
|
HBURST_S16 <= "000";
|
1064 |
|
|
HPROT_S0 <= "0000";
|
1065 |
|
|
HPROT_S1 <= "0000";
|
1066 |
|
|
HPROT_S2 <= "0000";
|
1067 |
|
|
HPROT_S3 <= "0000";
|
1068 |
|
|
HPROT_S4 <= "0000";
|
1069 |
|
|
HPROT_S5 <= "0000";
|
1070 |
|
|
HPROT_S6 <= "0000";
|
1071 |
|
|
HPROT_S7 <= "0000";
|
1072 |
|
|
HPROT_S8 <= "0000";
|
1073 |
|
|
HPROT_S9 <= "0000";
|
1074 |
|
|
HPROT_S10 <= "0000";
|
1075 |
|
|
HPROT_S11 <= "0000";
|
1076 |
|
|
HPROT_S12 <= "0000";
|
1077 |
|
|
HPROT_S13 <= "0000";
|
1078 |
|
|
HPROT_S14 <= "0000";
|
1079 |
|
|
HPROT_S15 <= "0000";
|
1080 |
|
|
HPROT_S16 <= "0000";
|
1081 |
|
|
|
1082 |
|
|
|
1083 |
|
|
matrix4x16 : COREAHBLITE_MATRIX4X16
|
1084 |
|
|
generic map (
|
1085 |
|
|
MEMSPACE => MEMSPACE,
|
1086 |
|
|
HADDR_SHG_CFG => HADDR_SHG_CFG,
|
1087 |
|
|
M0_AHBSLOTENABLE => M0_AHBSLOTENABLE,
|
1088 |
|
|
M1_AHBSLOTENABLE => M1_AHBSLOTENABLE,
|
1089 |
|
|
M2_AHBSLOTENABLE => M2_AHBSLOTENABLE,
|
1090 |
|
|
M3_AHBSLOTENABLE => M3_AHBSLOTENABLE,
|
1091 |
|
|
SC => SC,
|
1092 |
|
|
SYNC_RESET => SYNC_RESET
|
1093 |
|
|
)
|
1094 |
|
|
port map (
|
1095 |
|
|
HCLK => HCLK,
|
1096 |
|
|
HRESETN => HRESETN,
|
1097 |
|
|
REMAP_M0 => REMAP_M0,
|
1098 |
|
|
HADDR_M0 => HADDR_M0,
|
1099 |
|
|
HMASTLOCK_M0 => HMASTLOCK_M0,
|
1100 |
|
|
HSIZE_M0 => HSIZE_M0,
|
1101 |
|
|
HTRANS_M0 => HTRANS_M0(1),
|
1102 |
|
|
HWRITE_M0 => HWRITE_M0,
|
1103 |
|
|
HWDATA_M0 => HWDATA_M0,
|
1104 |
|
|
HRESP_M0 => HRESP_M0_xhdl54(0),
|
1105 |
|
|
HRDATA_M0 => HRDATA_M0_xhdl33,
|
1106 |
|
|
HREADY_M0 => HREADY_M0_xhdl35,
|
1107 |
|
|
HADDR_M1 => HADDR_M1,
|
1108 |
|
|
HMASTLOCK_M1 => HMASTLOCK_M1,
|
1109 |
|
|
HSIZE_M1 => HSIZE_M1,
|
1110 |
|
|
HTRANS_M1 => HTRANS_M1(1),
|
1111 |
|
|
HWRITE_M1 => HWRITE_M1,
|
1112 |
|
|
HWDATA_M1 => HWDATA_M1,
|
1113 |
|
|
HRESP_M1 => HRESP_M1_xhdl55(0),
|
1114 |
|
|
HRDATA_M1 => HRDATA_M1_xhdl34,
|
1115 |
|
|
HREADY_M1 => HREADY_M1_xhdl36,
|
1116 |
|
|
HADDR_M2 => HADDR_M2,
|
1117 |
|
|
HMASTLOCK_M2 => HMASTLOCK_M2,
|
1118 |
|
|
HSIZE_M2 => HSIZE_M2,
|
1119 |
|
|
HTRANS_M2 => HTRANS_M2(1),
|
1120 |
|
|
HWRITE_M2 => HWRITE_M2,
|
1121 |
|
|
HWDATA_M2 => HWDATA_M2,
|
1122 |
|
|
HRESP_M2 => HRESP_M2_xhdl54(0),
|
1123 |
|
|
HRDATA_M2 => HRDATA_M2_xhdl33,
|
1124 |
|
|
HREADY_M2 => HREADY_M2_xhdl35,
|
1125 |
|
|
HADDR_M3 => HADDR_M3,
|
1126 |
|
|
HMASTLOCK_M3 => HMASTLOCK_M3,
|
1127 |
|
|
HSIZE_M3 => HSIZE_M3,
|
1128 |
|
|
HTRANS_M3 => HTRANS_M3(1),
|
1129 |
|
|
HWRITE_M3 => HWRITE_M3,
|
1130 |
|
|
HWDATA_M3 => HWDATA_M3,
|
1131 |
|
|
HRESP_M3 => HRESP_M3_xhdl55(0),
|
1132 |
|
|
HRDATA_M3 => HRDATA_M3_xhdl34,
|
1133 |
|
|
HREADY_M3 => HREADY_M3_xhdl36,
|
1134 |
|
|
HRDATA_S0 => HRDATA_S0,
|
1135 |
|
|
HREADYOUT_S0 => HREADYOUT_S0,
|
1136 |
|
|
HRESP_S0 => HRESP_S0(0),
|
1137 |
|
|
HSEL_S0 => HSEL_S0_xhdl56,
|
1138 |
|
|
HADDR_S0 => HADDR_S0_xhdl0,
|
1139 |
|
|
HSIZE_S0 => HSIZE_S0_xhdl73,
|
1140 |
|
|
HTRANS_S0 => HTRANS_S0_xhdl90(1),
|
1141 |
|
|
HWRITE_S0 => HWRITE_S0_xhdl124,
|
1142 |
|
|
HWDATA_S0 => HWDATA_S0_xhdl107,
|
1143 |
|
|
HREADY_S0 => HREADY_S0_xhdl37,
|
1144 |
|
|
HMASTLOCK_S0 => HMASTLOCK_S0_xhdl16,
|
1145 |
|
|
HRDATA_S1 => HRDATA_S1,
|
1146 |
|
|
HREADYOUT_S1 => HREADYOUT_S1,
|
1147 |
|
|
HRESP_S1 => HRESP_S1(0),
|
1148 |
|
|
HSEL_S1 => HSEL_S1_xhdl57,
|
1149 |
|
|
HADDR_S1 => HADDR_S1_xhdl1,
|
1150 |
|
|
HSIZE_S1 => HSIZE_S1_xhdl74,
|
1151 |
|
|
HTRANS_S1 => HTRANS_S1_xhdl91(1),
|
1152 |
|
|
HWRITE_S1 => HWRITE_S1_xhdl125,
|
1153 |
|
|
HWDATA_S1 => HWDATA_S1_xhdl108,
|
1154 |
|
|
HREADY_S1 => HREADY_S1_xhdl38,
|
1155 |
|
|
HMASTLOCK_S1 => HMASTLOCK_S1_xhdl17,
|
1156 |
|
|
HRDATA_S2 => HRDATA_S2,
|
1157 |
|
|
HREADYOUT_S2 => HREADYOUT_S2,
|
1158 |
|
|
HRESP_S2 => HRESP_S2(0),
|
1159 |
|
|
HSEL_S2 => HSEL_S2_xhdl64,
|
1160 |
|
|
HADDR_S2 => HADDR_S2_xhdl8,
|
1161 |
|
|
HSIZE_S2 => HSIZE_S2_xhdl81,
|
1162 |
|
|
HTRANS_S2 => HTRANS_S2_xhdl98(1),
|
1163 |
|
|
HWRITE_S2 => HWRITE_S2_xhdl132,
|
1164 |
|
|
HWDATA_S2 => HWDATA_S2_xhdl115,
|
1165 |
|
|
HREADY_S2 => HREADY_S2_xhdl45,
|
1166 |
|
|
HMASTLOCK_S2 => HMASTLOCK_S2_xhdl24,
|
1167 |
|
|
HRDATA_S3 => HRDATA_S3,
|
1168 |
|
|
HREADYOUT_S3 => HREADYOUT_S3,
|
1169 |
|
|
HRESP_S3 => HRESP_S3(0),
|
1170 |
|
|
HSEL_S3 => HSEL_S3_xhdl65,
|
1171 |
|
|
HADDR_S3 => HADDR_S3_xhdl9,
|
1172 |
|
|
HSIZE_S3 => HSIZE_S3_xhdl82,
|
1173 |
|
|
HTRANS_S3 => HTRANS_S3_xhdl99(1),
|
1174 |
|
|
HWRITE_S3 => HWRITE_S3_xhdl133,
|
1175 |
|
|
HWDATA_S3 => HWDATA_S3_xhdl116,
|
1176 |
|
|
HREADY_S3 => HREADY_S3_xhdl46,
|
1177 |
|
|
HMASTLOCK_S3 => HMASTLOCK_S3_xhdl25,
|
1178 |
|
|
HRDATA_S4 => HRDATA_S4,
|
1179 |
|
|
HREADYOUT_S4 => HREADYOUT_S4,
|
1180 |
|
|
HRESP_S4 => HRESP_S4(0),
|
1181 |
|
|
HSEL_S4 => HSEL_S4_xhdl66,
|
1182 |
|
|
HADDR_S4 => HADDR_S4_xhdl10,
|
1183 |
|
|
HSIZE_S4 => HSIZE_S4_xhdl83,
|
1184 |
|
|
HTRANS_S4 => HTRANS_S4_xhdl100(1),
|
1185 |
|
|
HWRITE_S4 => HWRITE_S4_xhdl134,
|
1186 |
|
|
HWDATA_S4 => HWDATA_S4_xhdl117,
|
1187 |
|
|
HREADY_S4 => HREADY_S4_xhdl47,
|
1188 |
|
|
HMASTLOCK_S4 => HMASTLOCK_S4_xhdl26,
|
1189 |
|
|
HRDATA_S5 => HRDATA_S5,
|
1190 |
|
|
HREADYOUT_S5 => HREADYOUT_S5,
|
1191 |
|
|
HRESP_S5 => HRESP_S5(0),
|
1192 |
|
|
HSEL_S5 => HSEL_S5_xhdl67,
|
1193 |
|
|
HADDR_S5 => HADDR_S5_xhdl11,
|
1194 |
|
|
HSIZE_S5 => HSIZE_S5_xhdl84,
|
1195 |
|
|
HTRANS_S5 => HTRANS_S5_xhdl101(1),
|
1196 |
|
|
HWRITE_S5 => HWRITE_S5_xhdl135,
|
1197 |
|
|
HWDATA_S5 => HWDATA_S5_xhdl118,
|
1198 |
|
|
HREADY_S5 => HREADY_S5_xhdl48,
|
1199 |
|
|
HMASTLOCK_S5 => HMASTLOCK_S5_xhdl27,
|
1200 |
|
|
HRDATA_S6 => HRDATA_S6,
|
1201 |
|
|
HREADYOUT_S6 => HREADYOUT_S6,
|
1202 |
|
|
HRESP_S6 => HRESP_S6(0),
|
1203 |
|
|
HSEL_S6 => HSEL_S6_xhdl68,
|
1204 |
|
|
HADDR_S6 => HADDR_S6_xhdl12,
|
1205 |
|
|
HSIZE_S6 => HSIZE_S6_xhdl85,
|
1206 |
|
|
HTRANS_S6 => HTRANS_S6_xhdl102(1),
|
1207 |
|
|
HWRITE_S6 => HWRITE_S6_xhdl136,
|
1208 |
|
|
HWDATA_S6 => HWDATA_S6_xhdl119,
|
1209 |
|
|
HREADY_S6 => HREADY_S6_xhdl49,
|
1210 |
|
|
HMASTLOCK_S6 => HMASTLOCK_S6_xhdl28,
|
1211 |
|
|
HRDATA_S7 => HRDATA_S7,
|
1212 |
|
|
HREADYOUT_S7 => HREADYOUT_S7,
|
1213 |
|
|
HRESP_S7 => HRESP_S7(0),
|
1214 |
|
|
HSEL_S7 => HSEL_S7_xhdl69,
|
1215 |
|
|
HADDR_S7 => HADDR_S7_xhdl13,
|
1216 |
|
|
HSIZE_S7 => HSIZE_S7_xhdl86,
|
1217 |
|
|
HTRANS_S7 => HTRANS_S7_xhdl103(1),
|
1218 |
|
|
HWRITE_S7 => HWRITE_S7_xhdl137,
|
1219 |
|
|
HWDATA_S7 => HWDATA_S7_xhdl120,
|
1220 |
|
|
HREADY_S7 => HREADY_S7_xhdl50,
|
1221 |
|
|
HMASTLOCK_S7 => HMASTLOCK_S7_xhdl29,
|
1222 |
|
|
HRDATA_S8 => HRDATA_S8,
|
1223 |
|
|
HREADYOUT_S8 => HREADYOUT_S8,
|
1224 |
|
|
HRESP_S8 => HRESP_S8(0),
|
1225 |
|
|
HSEL_S8 => HSEL_S8_xhdl70,
|
1226 |
|
|
HADDR_S8 => HADDR_S8_xhdl14,
|
1227 |
|
|
HSIZE_S8 => HSIZE_S8_xhdl87,
|
1228 |
|
|
HTRANS_S8 => HTRANS_S8_xhdl104(1),
|
1229 |
|
|
HWRITE_S8 => HWRITE_S8_xhdl138,
|
1230 |
|
|
HWDATA_S8 => HWDATA_S8_xhdl121,
|
1231 |
|
|
HREADY_S8 => HREADY_S8_xhdl51,
|
1232 |
|
|
HMASTLOCK_S8 => HMASTLOCK_S8_xhdl30,
|
1233 |
|
|
HRDATA_S9 => HRDATA_S9,
|
1234 |
|
|
HREADYOUT_S9 => HREADYOUT_S9,
|
1235 |
|
|
HRESP_S9 => HRESP_S9(0),
|
1236 |
|
|
HSEL_S9 => HSEL_S9_xhdl71,
|
1237 |
|
|
HADDR_S9 => HADDR_S9_xhdl15,
|
1238 |
|
|
HSIZE_S9 => HSIZE_S9_xhdl88,
|
1239 |
|
|
HTRANS_S9 => HTRANS_S9_xhdl105(1),
|
1240 |
|
|
HWRITE_S9 => HWRITE_S9_xhdl139,
|
1241 |
|
|
HWDATA_S9 => HWDATA_S9_xhdl122,
|
1242 |
|
|
HREADY_S9 => HREADY_S9_xhdl52,
|
1243 |
|
|
HMASTLOCK_S9 => HMASTLOCK_S9_xhdl31,
|
1244 |
|
|
HRDATA_S10 => HRDATA_S10,
|
1245 |
|
|
HREADYOUT_S10 => HREADYOUT_S10,
|
1246 |
|
|
HRESP_S10 => HRESP_S10(0),
|
1247 |
|
|
HSEL_S10 => HSEL_S10_xhdl58,
|
1248 |
|
|
HADDR_S10 => HADDR_S10_xhdl2,
|
1249 |
|
|
HSIZE_S10 => HSIZE_S10_xhdl75,
|
1250 |
|
|
HTRANS_S10 => HTRANS_S10_xhdl92(1),
|
1251 |
|
|
HWRITE_S10 => HWRITE_S10_xhdl126,
|
1252 |
|
|
HWDATA_S10 => HWDATA_S10_xhdl109,
|
1253 |
|
|
HREADY_S10 => HREADY_S10_xhdl39,
|
1254 |
|
|
HMASTLOCK_S10 => HMASTLOCK_S10_xhdl18,
|
1255 |
|
|
HRDATA_S11 => HRDATA_S11,
|
1256 |
|
|
HREADYOUT_S11 => HREADYOUT_S11,
|
1257 |
|
|
HRESP_S11 => HRESP_S11(0),
|
1258 |
|
|
HSEL_S11 => HSEL_S11_xhdl59,
|
1259 |
|
|
HADDR_S11 => HADDR_S11_xhdl3,
|
1260 |
|
|
HSIZE_S11 => HSIZE_S11_xhdl76,
|
1261 |
|
|
HTRANS_S11 => HTRANS_S11_xhdl93(1),
|
1262 |
|
|
HWRITE_S11 => HWRITE_S11_xhdl127,
|
1263 |
|
|
HWDATA_S11 => HWDATA_S11_xhdl110,
|
1264 |
|
|
HREADY_S11 => HREADY_S11_xhdl40,
|
1265 |
|
|
HMASTLOCK_S11 => HMASTLOCK_S11_xhdl19,
|
1266 |
|
|
HRDATA_S12 => HRDATA_S12,
|
1267 |
|
|
HREADYOUT_S12 => HREADYOUT_S12,
|
1268 |
|
|
HRESP_S12 => HRESP_S12(0),
|
1269 |
|
|
HSEL_S12 => HSEL_S12_xhdl60,
|
1270 |
|
|
HADDR_S12 => HADDR_S12_xhdl4,
|
1271 |
|
|
HSIZE_S12 => HSIZE_S12_xhdl77,
|
1272 |
|
|
HTRANS_S12 => HTRANS_S12_xhdl94(1),
|
1273 |
|
|
HWRITE_S12 => HWRITE_S12_xhdl128,
|
1274 |
|
|
HWDATA_S12 => HWDATA_S12_xhdl111,
|
1275 |
|
|
HREADY_S12 => HREADY_S12_xhdl41,
|
1276 |
|
|
HMASTLOCK_S12 => HMASTLOCK_S12_xhdl20,
|
1277 |
|
|
HRDATA_S13 => HRDATA_S13,
|
1278 |
|
|
HREADYOUT_S13 => HREADYOUT_S13,
|
1279 |
|
|
HRESP_S13 => HRESP_S13(0),
|
1280 |
|
|
HSEL_S13 => HSEL_S13_xhdl61,
|
1281 |
|
|
HADDR_S13 => HADDR_S13_xhdl5,
|
1282 |
|
|
HSIZE_S13 => HSIZE_S13_xhdl78,
|
1283 |
|
|
HTRANS_S13 => HTRANS_S13_xhdl95(1),
|
1284 |
|
|
HWRITE_S13 => HWRITE_S13_xhdl129,
|
1285 |
|
|
HWDATA_S13 => HWDATA_S13_xhdl112,
|
1286 |
|
|
HREADY_S13 => HREADY_S13_xhdl42,
|
1287 |
|
|
HMASTLOCK_S13 => HMASTLOCK_S13_xhdl21,
|
1288 |
|
|
HRDATA_S14 => HRDATA_S14,
|
1289 |
|
|
HREADYOUT_S14 => HREADYOUT_S14,
|
1290 |
|
|
HRESP_S14 => HRESP_S14(0),
|
1291 |
|
|
HSEL_S14 => HSEL_S14_xhdl62,
|
1292 |
|
|
HADDR_S14 => HADDR_S14_xhdl6,
|
1293 |
|
|
HSIZE_S14 => HSIZE_S14_xhdl79,
|
1294 |
|
|
HTRANS_S14 => HTRANS_S14_xhdl96(1),
|
1295 |
|
|
HWRITE_S14 => HWRITE_S14_xhdl130,
|
1296 |
|
|
HWDATA_S14 => HWDATA_S14_xhdl113,
|
1297 |
|
|
HREADY_S14 => HREADY_S14_xhdl43,
|
1298 |
|
|
HMASTLOCK_S14 => HMASTLOCK_S14_xhdl22,
|
1299 |
|
|
HRDATA_S15 => HRDATA_S15,
|
1300 |
|
|
HREADYOUT_S15 => HREADYOUT_S15,
|
1301 |
|
|
HRESP_S15 => HRESP_S15(0),
|
1302 |
|
|
HSEL_S15 => HSEL_S15_xhdl63,
|
1303 |
|
|
HADDR_S15 => HADDR_S15_xhdl7,
|
1304 |
|
|
HSIZE_S15 => HSIZE_S15_xhdl80,
|
1305 |
|
|
HTRANS_S15 => HTRANS_S15_xhdl97(1),
|
1306 |
|
|
HWRITE_S15 => HWRITE_S15_xhdl131,
|
1307 |
|
|
HWDATA_S15 => HWDATA_S15_xhdl114,
|
1308 |
|
|
HREADY_S15 => HREADY_S15_xhdl44,
|
1309 |
|
|
HMASTLOCK_S15 => HMASTLOCK_S15_xhdl23,
|
1310 |
|
|
HRDATA_S16 => HRDATA_S16,
|
1311 |
|
|
HREADYOUT_S16 => HREADYOUT_S16,
|
1312 |
|
|
HRESP_S16 => HRESP_S16(0),
|
1313 |
|
|
HSEL_S16 => HSEL_S16_xhdl72,
|
1314 |
|
|
HADDR_S16 => HADDR_S16,
|
1315 |
|
|
HSIZE_S16 => HSIZE_S16_xhdl89,
|
1316 |
|
|
HTRANS_S16 => HTRANS_S16_xhdl106(1),
|
1317 |
|
|
HWRITE_S16 => HWRITE_S16_xhdl140,
|
1318 |
|
|
HWDATA_S16 => HWDATA_S16_xhdl123,
|
1319 |
|
|
HREADY_S16 => HREADY_S16_xhdl53,
|
1320 |
|
|
HMASTLOCK_S16 => HMASTLOCK_S16_xhdl32
|
1321 |
|
|
);
|
1322 |
|
|
|
1323 |
|
|
end architecture CoreAHBLite_arch;
|