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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [component/] [work/] [top/] [CoreUARTapb_0/] [rtl/] [vhdl/] [core/] [Rx_async.vhd] - Blame information for rev 3

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-- ********************************************************************
-- Actel Corporation Proprietary and Confidential
--  Copyright 2008 Actel Corporation.  All rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
--
-- Description: CoreUART/ CoreUARTapb UART core
--
--
--  Revision Information:
-- Date     Description
-- Jun09    Revision 4.1
-- Aug10    Revision 4.2
 
-- SVN Revision Information:
-- SVN $Revision: 8508 $
-- SVN $Date: 2009-06-15 16:49:49 -0700 (Mon, 15 Jun 2009) $
--
-- Resolved SARs
-- SAR      Date     Who   Description
-- 20741    2Sep10   AS    Increased baud rate by ensuring fifo ctrl runs off
--                         sys clk (not baud clock).  See note below.
 
-- Notes:
-- best viewed with tabstops set to "4"
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
 
ENTITY top_CoreUARTapb_0_Rx_async IS
   GENERIC ( SYNC_RESET      : integer := 0;
             -- RX Parameters
             RX_FIFO         :  integer := 0);    --  0=without rx fifo, 1=with rx fifo 
   PORT (
 
      clk                     : IN std_logic;   --   system clock
      baud_clock              : IN std_logic;   --   8x baud clock pulse
      reset_n                 : IN std_logic;   --   active low async reset  
      bit8                    : IN std_logic;   --   if set to one 8 data bits otherwise 7 data bits
      parity_en               : IN std_logic;   --   if set to one parity is enabled otherwise disabled
      odd_n_even              : IN std_logic;   --   if set to one odd parity otherwise even parity
      read_rx_byte            : IN std_logic;   --   read rx byte register
      clear_parity            : IN std_logic;   --   clear parity error 
      clear_framing_error     : IN std_logic;   --   clear framing error 
      rx                      : IN std_logic;
      overflow                : OUT std_logic;   --   receiver overflow
      parity_err              : OUT std_logic;   --   parity error indicator on recieved data
      framing_error           : OUT std_logic;   --   framing error indicator (AS)
      rx_idle_out             : OUT std_logic;   --   used for framing error assignment (AS)
      stop_strobe             : OUT std_logic;   --   stop sync signal for RXRDY
      clear_framing_error_en  : OUT std_logic;   --  clear framing error enable
      clear_parity_en         : OUT std_logic;   --  clear parity error enable
      receive_full            : OUT std_logic;   --   receiver has a byte ready
      rx_byte                 : OUT std_logic_vector(7 DOWNTO 0);
      fifo_write              : OUT std_logic);
END ENTITY top_CoreUARTapb_0_Rx_async;
 
ARCHITECTURE translated OF top_CoreUARTapb_0_Rx_async IS
 
   -- TYPE receive_states:
   type receive_states  is (rx_idle, rx_data_bits, rx_stop_bit, rx_wait_state);
 
   --  receive byte register
   SIGNAL rx_state                 :  receive_states;                -- receive state machine
   SIGNAL receive_count            :  std_logic_vector(3 DOWNTO 0);   --   counts bits received
   SIGNAL rx_filtered              :  std_logic;   --   filtered rx data
   SIGNAL rx_shift                 :  std_logic_vector(8 DOWNTO 0);   --   receive shift register
   SIGNAL rx_parity_calc           :  std_logic;   --   received parity, calculated
   SIGNAL rx_bit_cnt               :  std_logic_vector(3 DOWNTO 0);   --   count of received bits 
   SIGNAL receive_full_int         :  std_logic;   --   receiver has a byte ready
   SIGNAL samples                  :  std_logic_vector(2 DOWNTO 0);
   SIGNAL overflow_int             :  std_logic;
   SIGNAL shift_choice             :  std_logic_vector(1 DOWNTO 0);
   SIGNAL parity_choice            :  std_logic_vector(1 DOWNTO 0);
   -- ----------------------------------------------------------------------------
   SIGNAL last_bit                 :  std_logic_vector(3 DOWNTO 0);
   -- ----------------------------------------------------------------------------
   --  receive state machine & byte register
   -- ----------------------------------------------------------------------------
   SIGNAL overflow_xhdl1           :  std_logic;
   SIGNAL parity_err_xhdl2         :  std_logic;
   SIGNAL framing_error_i          :  std_logic;
   SIGNAL framing_error_int        :  std_logic;
   SIGNAL stop_strobe_i            :  std_logic;
   SIGNAL clear_parity_en_xhdl3    :  std_logic;
   SIGNAL clear_framing_error_en_i :  std_logic; -- AS: Added 07-29-09
   SIGNAL receive_full_xhdl4       :  std_logic;
   SIGNAL rx_byte_xhdl5            :  std_logic_vector(7 DOWNTO 0);
   SIGNAL last_bit_case            :  std_logic_vector(1 DOWNTO 0);
   SIGNAL fifo_write_xhdl6         :  std_logic;
   SIGNAL aresetn                  :  std_logic;
   SIGNAL sresetn                  :  std_logic;
 
BEGIN
   aresetn <= '1' WHEN (SYNC_RESET=1) ELSE reset_n;
   sresetn <= reset_n WHEN (SYNC_RESET=1) ELSE '1';
   stop_strobe <= stop_strobe_i;
   framing_error <= framing_error_i;
   overflow <= overflow_xhdl1;
   parity_err <= parity_err_xhdl2;
   clear_parity_en <= clear_parity_en_xhdl3;
   receive_full <= receive_full_xhdl4;
   rx_byte <= rx_byte_xhdl5;
   fifo_write <= fifo_write_xhdl6;
   rx_idle_out <= '1' when (rx_state = rx_idle) else '0';
   clear_framing_error_en <= clear_framing_error_en_i;
   last_bit_case <= bit8 & parity_en;
 
   --  filter the receive data
   -- ----------------------------------------------------------------------------
   --  The receive data filter is a simple majority voter that accepts three
   --  samples of the "raw" data and reports the most populus result.  This
   --  provides a simple single-cycle glitch filter.
   --  This input needs to go to both the state machine start bit detector as
   --  well as the data shift register as this filter introduces a three-clock 
   --  delay and we need to keep the phases lined up.
   -- 
 
   majority : PROCESS (clk, aresetn)
   BEGIN
      IF (aresetn = '0') THEN
         samples <= "111";
      ELSIF (clk'EVENT AND clk = '1') THEN
         IF (sresetn = '0') THEN
            samples <= "111";
             ELSE
            IF (baud_clock = '1') THEN
               samples(1 DOWNTO 0) <= samples(2 DOWNTO 1);
               samples(2) <= rx;
            END IF;
         END IF;
      END IF;
   END PROCESS majority;
 
   --  our voter
 
   PROCESS (samples)
   BEGIN
      CASE samples IS
         WHEN "000" =>
                  rx_filtered <= '0';
         WHEN "001" =>
                  rx_filtered <= '0';
         WHEN "010" =>
                  rx_filtered <= '0';
         WHEN "011" =>
                  rx_filtered <= '1';
         WHEN "100" =>
                  rx_filtered <= '0';
         WHEN "101" =>
                  rx_filtered <= '1';
         WHEN "110" =>
                  rx_filtered <= '1';
         WHEN OTHERS  =>
                  rx_filtered <= '1';
 
      END CASE;
   END PROCESS;
 
   -- ----------------------------------------------------------------------------
   --  receive bit counter
   -- ----------------------------------------------------------------------------
 
   rcv_cnt : PROCESS (clk, aresetn)
   BEGIN
      IF (aresetn = '0') THEN
         receive_count <= "0000";
      ELSIF (clk'EVENT AND clk = '1') THEN
         IF (sresetn = '0') THEN
            receive_count <= "0000";
             ELSE
            IF (baud_clock = '1') THEN
               --  no start bit yet or begin sample period for data
 
               IF ((baud_clock = '1' AND rx_state = rx_idle AND (rx_filtered = '1' OR receive_count = "1000")) OR (rx_state = rx_wait_state AND (receive_count = "0110"))) THEN
                  receive_count <= "0000";
               ELSE
                  receive_count <= receive_count + "0001";
               END IF;
            END IF;
         END IF;
      END IF;
   END PROCESS rcv_cnt;
 
   -- ----------------------------------------------------------------------------
   --  registering of the overflow signal
   -- ----------------------------------------------------------------------------
 
   make_overflow : PROCESS (clk, aresetn)
   BEGIN
      IF (aresetn = '0') THEN
         overflow_xhdl1 <= '0';
      ELSIF (clk'EVENT AND clk = '1') THEN
         IF (sresetn = '0') THEN
            overflow_xhdl1 <= '0';
             ELSE
            IF (baud_clock = '1') THEN
               IF (overflow_int = '1') THEN
                  overflow_xhdl1 <= '1';
               END IF;
            END IF;
            IF (read_rx_byte = '1') THEN
               overflow_xhdl1 <= '0';
            END IF;
         END IF;
      END IF;
   END PROCESS make_overflow;
 
   -- ----------------------------------------------------------------------------
   --  registering of the framing_error signal
   -- ----------------------------------------------------------------------------
 
   make_framing_error : PROCESS (clk, aresetn)
   BEGIN
      IF (aresetn = '0') THEN
         framing_error_i <= '0';
      ELSIF (clk'EVENT AND clk = '1') THEN
         IF (sresetn = '0') THEN
            framing_error_i <= '0';
             ELSE
            IF (baud_clock = '1') THEN
               IF (framing_error_int = '1') THEN
                  framing_error_i <= '1';
               ELSIF (clear_framing_error = '1') THEN
                   framing_error_i <= '0';
               END IF;
            ELSIF (clear_framing_error = '1') THEN
               framing_error_i <= '0';
            ELSE
               framing_error_i <= framing_error_i;
            END IF;
         END IF;
      END IF;
   END PROCESS make_framing_error;
 
   make_last_bit : PROCESS (clk, aresetn)
   BEGIN
       IF(aresetn = '0') THEN
           last_bit <= "1001";
       ELSIF (clk'EVENT AND clk = '1') THEN
           IF(sresetn = '0') THEN
               last_bit <= "1001";
               ELSE
               IF((baud_clock = '1') AND (rx_state = rx_idle) AND (receive_count = "1000")) THEN
                   CASE(last_bit_case) IS
                     WHEN "00" => last_bit <= "0111";
                     WHEN "01" => last_bit <= "1000";
                     WHEN "10" => last_bit <= "1000";
                     WHEN "11" => last_bit <= "1001";
                     WHEN OTHERS => last_bit <= "1001";
                   END CASE;
               ELSE
                   last_bit <= last_bit;
               END IF;
           END IF;
       END IF;
   END PROCESS;
 
   rcv_sm : PROCESS (clk, aresetn)
   BEGIN
      IF (aresetn = '0') THEN
         rx_state <= rx_idle;
         rx_byte_xhdl5 <= "00000000";
         overflow_int <= '0';
         framing_error_int <= '0';
         stop_strobe_i <= '0';
      ELSIF (clk'EVENT AND clk = '1') THEN
          IF (sresetn = '0') THEN
             rx_state <= rx_idle;
             rx_byte_xhdl5 <= "00000000";
             overflow_int <= '0';
             framing_error_int <= '0';
             stop_strobe_i <= '0';
              ELSE
             IF (baud_clock = '1') THEN
                overflow_int <= '0';
                framing_error_int <= '0';
                stop_strobe_i <= '0';
                CASE rx_state IS
                   WHEN rx_idle =>
                            IF (receive_count = "1000") THEN
                               rx_state <= rx_data_bits;
                            ELSE
                               rx_state <= rx_idle;
                            END IF;
                   WHEN rx_data_bits =>
                            IF (rx_bit_cnt = last_bit) THEN
                               --  last bit has been received
                               --  if receive_full is still active at this point, then overflow     
                               rx_state <= rx_stop_bit ;
                               overflow_int <= receive_full_int;
                               IF (receive_full_int = '0') THEN
                                  rx_byte_xhdl5 <= (bit8 AND rx_shift(7)) & rx_shift(6 DOWNTO 0);
                               END IF;
                            ELSE
                               rx_state <= rx_data_bits;    --   still clocking in bits
                            END IF;
                   WHEN rx_stop_bit =>
                            IF (receive_count = "1110") THEN
                               IF (rx_filtered = '0') THEN
                                  framing_error_int <= '1';
                                END IF;
                            ELSIF (receive_count = "1111") THEN
                               stop_strobe_i <= '1';
                               rx_state <=  rx_wait_state;
                            ELSE
                               rx_state <= rx_stop_bit;
                            END IF;
                   WHEN rx_wait_state =>
                            IF ((rx_filtered = '1') OR (receive_count = "0110")) THEN
                                                    rx_state <=  rx_idle;
                                                ELSE
                                                    rx_state <=  rx_wait_state;
                                                END IF;
                   WHEN OTHERS  =>
                            rx_state <=  rx_idle;
 
                END CASE;
             END IF;
          END IF;
      END IF;
   END PROCESS rcv_sm;
   -- ----------------------------------------------------------------------------
   --  receive shift register and parity calculation
   -- ----------------------------------------------------------------------------
   shift_choice <= bit8 & parity_en ;
 
   receive_shift : PROCESS (clk, aresetn)
   BEGIN
      IF (aresetn = '0') THEN
         rx_shift(8 DOWNTO 0) <= "000000000";
         rx_bit_cnt <= "0000";
      ELSIF (clk'EVENT AND clk = '1') THEN
         IF (sresetn = '0') THEN
            rx_shift(8 DOWNTO 0) <= "000000000";
            rx_bit_cnt <= "0000";
             ELSE
            IF (baud_clock = '1') THEN
               IF (rx_state = rx_idle) THEN
                  rx_shift(8 DOWNTO 0) <= "000000000";
                  rx_bit_cnt <= "0000";
               ELSE
                  IF (receive_count = "1111") THEN
                     --  sample new data bit
 
                     rx_bit_cnt <= rx_bit_cnt + "0001";
                     CASE shift_choice IS
                        WHEN "00" =>
                                 rx_shift(5 DOWNTO 0) <= rx_shift(6 DOWNTO 1);
                                 rx_shift(6) <= rx_filtered;
                        WHEN "11" =>
                                 rx_shift(7 DOWNTO 0) <= rx_shift(8 DOWNTO 1);
                                 rx_shift(8) <= rx_filtered;
                        WHEN OTHERS  =>
                                 rx_shift(6 DOWNTO 0) <= rx_shift(7 DOWNTO 1);
                                 rx_shift(7) <= rx_filtered;
 
                     END CASE;
                  END IF;
               END IF;
            END IF;
         END IF;
      END IF;
   END PROCESS receive_shift;
 
   -- ----------------------------------------------------------------------------
   --  receiver parity calculation
   -- ----------------------------------------------------------------------------
 
   rx_par_calc : PROCESS (clk, aresetn)
   BEGIN
      IF (aresetn = '0') THEN
         rx_parity_calc <= '0';
      ELSIF (clk'EVENT AND clk = '1') THEN
         IF (sresetn = '0') THEN
            rx_parity_calc <= '0';
             ELSE
            IF (baud_clock = '1') THEN
               IF (receive_count = "1111" AND parity_en = '1') THEN
                  rx_parity_calc <= rx_parity_calc XOR rx_filtered;
               END IF;
               IF ((rx_state =  rx_stop_bit)) THEN
                  rx_parity_calc <= '0';
               END IF;
            END IF;
         END IF;
      END IF;
   END PROCESS rx_par_calc;
   -- ----------------------------------------------------------------------------
   --  latch parity error for even or odd parity
   -- ----------------------------------------------------------------------------
   parity_choice <= bit8 & odd_n_even ;
 
   make_parity_err : PROCESS (clk, aresetn)
   BEGIN
      IF (aresetn = '0') THEN
         parity_err_xhdl2 <= '0';
      ELSIF (clk'EVENT AND clk = '1') THEN
         IF (sresetn = '0') THEN
            parity_err_xhdl2 <= '0';
             ELSE
            IF ((baud_clock = '1' AND parity_en = '1') AND receive_count = "1111") THEN
               CASE parity_choice IS
                  WHEN "00" =>
                           IF (rx_bit_cnt = "0111") THEN
                              parity_err_xhdl2 <= rx_parity_calc XOR rx_filtered;
                           END IF;
                  WHEN "01" =>
                           IF (rx_bit_cnt = "0111") THEN
                              parity_err_xhdl2 <= NOT (rx_parity_calc XOR rx_filtered);
                           END IF;
                  WHEN "10" =>
                           IF (rx_bit_cnt = "1000") THEN
                              parity_err_xhdl2 <= rx_parity_calc XOR rx_filtered;
                           END IF;
                  WHEN "11" =>
                           IF (rx_bit_cnt = "1000") THEN
                              parity_err_xhdl2 <= NOT (rx_parity_calc XOR rx_filtered);
                           END IF;
                  WHEN OTHERS  =>
                           parity_err_xhdl2 <= '0';
 
               END CASE;
            END IF;
            -- if (read_rx_byte == 1'b1)
 
            IF (clear_parity = '1') THEN
               parity_err_xhdl2 <= '0';
            END IF;
         END IF;
      END IF;
   END PROCESS make_parity_err;
 
   -- ----------------------------------------------------------------------------
   --  receive full indicator process
   -- ----------------------------------------------------------------------------
 
   receive_full_indicator : PROCESS (clk, aresetn)
   BEGIN
      IF (aresetn = '0') THEN
         receive_full_int <= '0';
         fifo_write_xhdl6 <= '1';
         clear_parity_en_xhdl3 <= '0';
         clear_framing_error_en_i <= '0';
      ELSIF (clk'EVENT AND clk = '1') THEN
         IF (sresetn = '0') THEN
            receive_full_int <= '0';
            fifo_write_xhdl6 <= '1';
            clear_parity_en_xhdl3 <= '0';
            clear_framing_error_en_i <= '0';
             ELSE
            fifo_write_xhdl6 <= '1';
            clear_parity_en_xhdl3 <= '0';
            clear_framing_error_en_i <= '0';
            IF (baud_clock = '1') THEN
               --  last bit has been received 
 
               IF (bit8 = '1') THEN
                  IF (parity_en = '1') THEN
                     IF (rx_bit_cnt = "1001" AND rx_state = rx_data_bits) THEN
                        fifo_write_xhdl6 <= '0';
                        clear_parity_en_xhdl3 <= '1';
                        clear_framing_error_en_i <= '1';
                        IF (RX_FIFO = 2#0#) THEN
                           receive_full_int <= '1';
                        END IF;
                     END IF;
                  ELSE
                     IF (rx_bit_cnt = "1000" AND rx_state = rx_data_bits) THEN
                        fifo_write_xhdl6 <= '0';
                        clear_parity_en_xhdl3 <= '1';
                        clear_framing_error_en_i <= '1';
                        IF (RX_FIFO = 2#0#) THEN
                           receive_full_int <= '1';
                        END IF;
                     END IF;
                  END IF;
               ELSE
                  IF (parity_en = '1') THEN
                     IF (rx_bit_cnt = "1000" AND rx_state = rx_data_bits) THEN
                        fifo_write_xhdl6 <= '0';
                        clear_parity_en_xhdl3 <= '1';
                        clear_framing_error_en_i <= '1';
                        IF (RX_FIFO = 2#0#) THEN
                           receive_full_int <= '1';
                        END IF;
                     END IF;
                  ELSE
                     IF (rx_bit_cnt = "0111" AND rx_state = rx_data_bits) THEN
                        fifo_write_xhdl6 <= '0';
                        clear_parity_en_xhdl3 <= '1';
                        clear_framing_error_en_i <= '1';
                        IF (RX_FIFO = 2#0#) THEN
                           receive_full_int <= '1';
                        END IF;
                     END IF;
                  END IF;
               END IF;
            END IF;
            IF (read_rx_byte = '1') THEN
               receive_full_int <= '0';
            END IF;
         END IF;
      END IF;
   END PROCESS receive_full_indicator;
   receive_full_xhdl4 <= receive_full_int ;
 
END ARCHITECTURE translated;

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Subversion Repositories ahbmaster

[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [component/] [work/] [top/] [CoreUARTapb_0/] [rtl/] [vhdl/] [core/] [Rx_async.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	uson	`-- ********************************************************************`
2			`-- Actel Corporation Proprietary and Confidential`
3			`-- Copyright 2008 Actel Corporation. All rights reserved.`
4			`--`
5			`-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN`
6			`-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED`
7			`-- IN ADVANCE IN WRITING.`
8			`--`
9			`-- Description: CoreUART/ CoreUARTapb UART core`
10			`--`
11			`--`
12			`-- Revision Information:`
13			`-- Date Description`
14			`-- Jun09 Revision 4.1`
15			`-- Aug10 Revision 4.2`
16
17			`-- SVN Revision Information:`
18			`-- SVN $Revision: 8508 $`
19			`-- SVN $Date: 2009-06-15 16:49:49 -0700 (Mon, 15 Jun 2009) $`
20			`--`
21			`-- Resolved SARs`
22			`-- SAR Date Who Description`
23			`-- 20741 2Sep10 AS Increased baud rate by ensuring fifo ctrl runs off`
24			`-- sys clk (not baud clock). See note below.`
25
26			`-- Notes:`
27			`-- best viewed with tabstops set to "4"`
28			`LIBRARY IEEE;`
29			`USE IEEE.std_logic_1164.all;`
30			`USE IEEE.std_logic_arith.all;`
31			`USE IEEE.std_logic_unsigned.all;`
32
33			`ENTITY top_CoreUARTapb_0_Rx_async IS`
34			`GENERIC ( SYNC_RESET : integer := 0;`
35			`-- RX Parameters`
36			`RX_FIFO : integer := 0); -- 0=without rx fifo, 1=with rx fifo`
37			`PORT (`
38
39			`clk : IN std_logic; -- system clock`
40			`baud_clock : IN std_logic; -- 8x baud clock pulse`
41			`reset_n : IN std_logic; -- active low async reset`
42			`bit8 : IN std_logic; -- if set to one 8 data bits otherwise 7 data bits`
43			`parity_en : IN std_logic; -- if set to one parity is enabled otherwise disabled`
44			`odd_n_even : IN std_logic; -- if set to one odd parity otherwise even parity`
45			`read_rx_byte : IN std_logic; -- read rx byte register`
46			`clear_parity : IN std_logic; -- clear parity error`
47			`clear_framing_error : IN std_logic; -- clear framing error`
48			`rx : IN std_logic;`
49			`overflow : OUT std_logic; -- receiver overflow`
50			`parity_err : OUT std_logic; -- parity error indicator on recieved data`
51			`framing_error : OUT std_logic; -- framing error indicator (AS)`
52			`rx_idle_out : OUT std_logic; -- used for framing error assignment (AS)`
53			`stop_strobe : OUT std_logic; -- stop sync signal for RXRDY`
54			`clear_framing_error_en : OUT std_logic; -- clear framing error enable`
55			`clear_parity_en : OUT std_logic; -- clear parity error enable`
56			`receive_full : OUT std_logic; -- receiver has a byte ready`
57			`rx_byte : OUT std_logic_vector(7 DOWNTO 0);`
58			`fifo_write : OUT std_logic);`
59			`END ENTITY top_CoreUARTapb_0_Rx_async;`
60
61			`ARCHITECTURE translated OF top_CoreUARTapb_0_Rx_async IS`
62
63			`-- TYPE receive_states:`
64			`type receive_states is (rx_idle, rx_data_bits, rx_stop_bit, rx_wait_state);`
65
66			`-- receive byte register`
67			`SIGNAL rx_state : receive_states; -- receive state machine`
68			`SIGNAL receive_count : std_logic_vector(3 DOWNTO 0); -- counts bits received`
69			`SIGNAL rx_filtered : std_logic; -- filtered rx data`
70			`SIGNAL rx_shift : std_logic_vector(8 DOWNTO 0); -- receive shift register`
71			`SIGNAL rx_parity_calc : std_logic; -- received parity, calculated`
72			`SIGNAL rx_bit_cnt : std_logic_vector(3 DOWNTO 0); -- count of received bits`
73			`SIGNAL receive_full_int : std_logic; -- receiver has a byte ready`
74			`SIGNAL samples : std_logic_vector(2 DOWNTO 0);`
75			`SIGNAL overflow_int : std_logic;`
76			`SIGNAL shift_choice : std_logic_vector(1 DOWNTO 0);`
77			`SIGNAL parity_choice : std_logic_vector(1 DOWNTO 0);`
78			`-- ----------------------------------------------------------------------------`
79			`SIGNAL last_bit : std_logic_vector(3 DOWNTO 0);`
80			`-- ----------------------------------------------------------------------------`
81			`-- receive state machine & byte register`
82			`-- ----------------------------------------------------------------------------`
83			`SIGNAL overflow_xhdl1 : std_logic;`
84			`SIGNAL parity_err_xhdl2 : std_logic;`
85			`SIGNAL framing_error_i : std_logic;`
86			`SIGNAL framing_error_int : std_logic;`
87			`SIGNAL stop_strobe_i : std_logic;`
88			`SIGNAL clear_parity_en_xhdl3 : std_logic;`
89			`SIGNAL clear_framing_error_en_i : std_logic; -- AS: Added 07-29-09`
90			`SIGNAL receive_full_xhdl4 : std_logic;`
91			`SIGNAL rx_byte_xhdl5 : std_logic_vector(7 DOWNTO 0);`
92			`SIGNAL last_bit_case : std_logic_vector(1 DOWNTO 0);`
93			`SIGNAL fifo_write_xhdl6 : std_logic;`
94			`SIGNAL aresetn : std_logic;`
95			`SIGNAL sresetn : std_logic;`
96
97			`BEGIN`
98			`aresetn <= '1' WHEN (SYNC_RESET=1) ELSE reset_n;`
99			`sresetn <= reset_n WHEN (SYNC_RESET=1) ELSE '1';`
100			`stop_strobe <= stop_strobe_i;`
101			`framing_error <= framing_error_i;`
102			`overflow <= overflow_xhdl1;`
103			`parity_err <= parity_err_xhdl2;`
104			`clear_parity_en <= clear_parity_en_xhdl3;`
105			`receive_full <= receive_full_xhdl4;`
106			`rx_byte <= rx_byte_xhdl5;`
107			`fifo_write <= fifo_write_xhdl6;`
108			`rx_idle_out <= '1' when (rx_state = rx_idle) else '0';`
109			`clear_framing_error_en <= clear_framing_error_en_i;`
110			`last_bit_case <= bit8 & parity_en;`
111
112			`-- filter the receive data`
113			`-- ----------------------------------------------------------------------------`
114			`-- The receive data filter is a simple majority voter that accepts three`
115			`-- samples of the "raw" data and reports the most populus result. This`
116			`-- provides a simple single-cycle glitch filter.`
117			`-- This input needs to go to both the state machine start bit detector as`
118			`-- well as the data shift register as this filter introduces a three-clock`
119			`-- delay and we need to keep the phases lined up.`
120			`--`
121
122			`majority : PROCESS (clk, aresetn)`
123			`BEGIN`
124			`IF (aresetn = '0') THEN`
125			`samples <= "111";`
126			`ELSIF (clk'EVENT AND clk = '1') THEN`
127			`IF (sresetn = '0') THEN`
128			`samples <= "111";`
129			`ELSE`
130			`IF (baud_clock = '1') THEN`
131			`samples(1 DOWNTO 0) <= samples(2 DOWNTO 1);`
132			`samples(2) <= rx;`
133			`END IF;`
134			`END IF;`
135			`END IF;`
136			`END PROCESS majority;`
137
138			`-- our voter`
139
140			`PROCESS (samples)`
141			`BEGIN`
142			`CASE samples IS`
143			`WHEN "000" =>`
144			`rx_filtered <= '0';`
145			`WHEN "001" =>`
146			`rx_filtered <= '0';`
147			`WHEN "010" =>`
148			`rx_filtered <= '0';`
149			`WHEN "011" =>`
150			`rx_filtered <= '1';`
151			`WHEN "100" =>`
152			`rx_filtered <= '0';`
153			`WHEN "101" =>`
154			`rx_filtered <= '1';`
155			`WHEN "110" =>`
156			`rx_filtered <= '1';`
157			`WHEN OTHERS =>`
158			`rx_filtered <= '1';`
159
160			`END CASE;`
161			`END PROCESS;`
162
163			`-- ----------------------------------------------------------------------------`
164			`-- receive bit counter`
165			`-- ----------------------------------------------------------------------------`
166
167			`rcv_cnt : PROCESS (clk, aresetn)`
168			`BEGIN`
169			`IF (aresetn = '0') THEN`
170			`receive_count <= "0000";`
171			`ELSIF (clk'EVENT AND clk = '1') THEN`
172			`IF (sresetn = '0') THEN`
173			`receive_count <= "0000";`
174			`ELSE`
175			`IF (baud_clock = '1') THEN`
176			`-- no start bit yet or begin sample period for data`
177
178			`IF ((baud_clock = '1' AND rx_state = rx_idle AND (rx_filtered = '1' OR receive_count = "1000")) OR (rx_state = rx_wait_state AND (receive_count = "0110"))) THEN`
179			`receive_count <= "0000";`
180			`ELSE`
181			`receive_count <= receive_count + "0001";`
182			`END IF;`
183			`END IF;`
184			`END IF;`
185			`END IF;`
186			`END PROCESS rcv_cnt;`
187
188			`-- ----------------------------------------------------------------------------`
189			`-- registering of the overflow signal`
190			`-- ----------------------------------------------------------------------------`
191
192			`make_overflow : PROCESS (clk, aresetn)`
193			`BEGIN`
194			`IF (aresetn = '0') THEN`
195			`overflow_xhdl1 <= '0';`
196			`ELSIF (clk'EVENT AND clk = '1') THEN`
197			`IF (sresetn = '0') THEN`
198			`overflow_xhdl1 <= '0';`
199			`ELSE`
200			`IF (baud_clock = '1') THEN`
201			`IF (overflow_int = '1') THEN`
202			`overflow_xhdl1 <= '1';`
203			`END IF;`
204			`END IF;`
205			`IF (read_rx_byte = '1') THEN`
206			`overflow_xhdl1 <= '0';`
207			`END IF;`
208			`END IF;`
209			`END IF;`
210			`END PROCESS make_overflow;`
211
212			`-- ----------------------------------------------------------------------------`
213			`-- registering of the framing_error signal`
214			`-- ----------------------------------------------------------------------------`
215
216			`make_framing_error : PROCESS (clk, aresetn)`
217			`BEGIN`
218			`IF (aresetn = '0') THEN`
219			`framing_error_i <= '0';`
220			`ELSIF (clk'EVENT AND clk = '1') THEN`
221			`IF (sresetn = '0') THEN`
222			`framing_error_i <= '0';`
223			`ELSE`
224			`IF (baud_clock = '1') THEN`
225			`IF (framing_error_int = '1') THEN`
226			`framing_error_i <= '1';`
227			`ELSIF (clear_framing_error = '1') THEN`
228			`framing_error_i <= '0';`
229			`END IF;`
230			`ELSIF (clear_framing_error = '1') THEN`
231			`framing_error_i <= '0';`
232			`ELSE`
233			`framing_error_i <= framing_error_i;`
234			`END IF;`
235			`END IF;`
236			`END IF;`
237			`END PROCESS make_framing_error;`
238
239			`make_last_bit : PROCESS (clk, aresetn)`
240			`BEGIN`
241			`IF(aresetn = '0') THEN`
242			`last_bit <= "1001";`
243			`ELSIF (clk'EVENT AND clk = '1') THEN`
244			`IF(sresetn = '0') THEN`
245			`last_bit <= "1001";`
246			`ELSE`
247			`IF((baud_clock = '1') AND (rx_state = rx_idle) AND (receive_count = "1000")) THEN`
248			`CASE(last_bit_case) IS`
249			`WHEN "00" => last_bit <= "0111";`
250			`WHEN "01" => last_bit <= "1000";`
251			`WHEN "10" => last_bit <= "1000";`
252			`WHEN "11" => last_bit <= "1001";`
253			`WHEN OTHERS => last_bit <= "1001";`
254			`END CASE;`
255			`ELSE`
256			`last_bit <= last_bit;`
257			`END IF;`
258			`END IF;`
259			`END IF;`
260			`END PROCESS;`
261
262			`rcv_sm : PROCESS (clk, aresetn)`
263			`BEGIN`
264			`IF (aresetn = '0') THEN`
265			`rx_state <= rx_idle;`
266			`rx_byte_xhdl5 <= "00000000";`
267			`overflow_int <= '0';`
268			`framing_error_int <= '0';`
269			`stop_strobe_i <= '0';`
270			`ELSIF (clk'EVENT AND clk = '1') THEN`
271			`IF (sresetn = '0') THEN`
272			`rx_state <= rx_idle;`
273			`rx_byte_xhdl5 <= "00000000";`
274			`overflow_int <= '0';`
275			`framing_error_int <= '0';`
276			`stop_strobe_i <= '0';`
277			`ELSE`
278			`IF (baud_clock = '1') THEN`
279			`overflow_int <= '0';`
280			`framing_error_int <= '0';`
281			`stop_strobe_i <= '0';`
282			`CASE rx_state IS`
283			`WHEN rx_idle =>`
284			`IF (receive_count = "1000") THEN`
285			`rx_state <= rx_data_bits;`
286			`ELSE`
287			`rx_state <= rx_idle;`
288			`END IF;`
289			`WHEN rx_data_bits =>`
290			`IF (rx_bit_cnt = last_bit) THEN`
291			`-- last bit has been received`
292			`-- if receive_full is still active at this point, then overflow`
293			`rx_state <= rx_stop_bit ;`
294			`overflow_int <= receive_full_int;`
295			`IF (receive_full_int = '0') THEN`
296			`rx_byte_xhdl5 <= (bit8 AND rx_shift(7)) & rx_shift(6 DOWNTO 0);`
297			`END IF;`
298			`ELSE`
299			`rx_state <= rx_data_bits; -- still clocking in bits`
300			`END IF;`
301			`WHEN rx_stop_bit =>`
302			`IF (receive_count = "1110") THEN`
303			`IF (rx_filtered = '0') THEN`
304			`framing_error_int <= '1';`
305			`END IF;`
306			`ELSIF (receive_count = "1111") THEN`
307			`stop_strobe_i <= '1';`
308			`rx_state <= rx_wait_state;`
309			`ELSE`
310			`rx_state <= rx_stop_bit;`
311			`END IF;`
312			`WHEN rx_wait_state =>`
313			`IF ((rx_filtered = '1') OR (receive_count = "0110")) THEN`
314			`rx_state <= rx_idle;`
315			`ELSE`
316			`rx_state <= rx_wait_state;`
317			`END IF;`
318			`WHEN OTHERS =>`
319			`rx_state <= rx_idle;`
320
321			`END CASE;`
322			`END IF;`
323			`END IF;`
324			`END IF;`
325			`END PROCESS rcv_sm;`
326			`-- ----------------------------------------------------------------------------`
327			`-- receive shift register and parity calculation`
328			`-- ----------------------------------------------------------------------------`
329			`shift_choice <= bit8 & parity_en ;`
330
331			`receive_shift : PROCESS (clk, aresetn)`
332			`BEGIN`
333			`IF (aresetn = '0') THEN`
334			`rx_shift(8 DOWNTO 0) <= "000000000";`
335			`rx_bit_cnt <= "0000";`
336			`ELSIF (clk'EVENT AND clk = '1') THEN`
337			`IF (sresetn = '0') THEN`
338			`rx_shift(8 DOWNTO 0) <= "000000000";`
339			`rx_bit_cnt <= "0000";`
340			`ELSE`
341			`IF (baud_clock = '1') THEN`
342			`IF (rx_state = rx_idle) THEN`
343			`rx_shift(8 DOWNTO 0) <= "000000000";`
344			`rx_bit_cnt <= "0000";`
345			`ELSE`
346			`IF (receive_count = "1111") THEN`
347			`-- sample new data bit`
348
349			`rx_bit_cnt <= rx_bit_cnt + "0001";`
350			`CASE shift_choice IS`
351			`WHEN "00" =>`
352			`rx_shift(5 DOWNTO 0) <= rx_shift(6 DOWNTO 1);`
353			`rx_shift(6) <= rx_filtered;`
354			`WHEN "11" =>`
355			`rx_shift(7 DOWNTO 0) <= rx_shift(8 DOWNTO 1);`
356			`rx_shift(8) <= rx_filtered;`
357			`WHEN OTHERS =>`
358			`rx_shift(6 DOWNTO 0) <= rx_shift(7 DOWNTO 1);`
359			`rx_shift(7) <= rx_filtered;`
360
361			`END CASE;`
362			`END IF;`
363			`END IF;`
364			`END IF;`
365			`END IF;`
366			`END IF;`
367			`END PROCESS receive_shift;`
368
369			`-- ----------------------------------------------------------------------------`
370			`-- receiver parity calculation`
371			`-- ----------------------------------------------------------------------------`
372
373			`rx_par_calc : PROCESS (clk, aresetn)`
374			`BEGIN`
375			`IF (aresetn = '0') THEN`
376			`rx_parity_calc <= '0';`
377			`ELSIF (clk'EVENT AND clk = '1') THEN`
378			`IF (sresetn = '0') THEN`
379			`rx_parity_calc <= '0';`
380			`ELSE`
381			`IF (baud_clock = '1') THEN`
382			`IF (receive_count = "1111" AND parity_en = '1') THEN`
383			`rx_parity_calc <= rx_parity_calc XOR rx_filtered;`
384			`END IF;`
385			`IF ((rx_state = rx_stop_bit)) THEN`
386			`rx_parity_calc <= '0';`
387			`END IF;`
388			`END IF;`
389			`END IF;`
390			`END IF;`
391			`END PROCESS rx_par_calc;`
392			`-- ----------------------------------------------------------------------------`
393			`-- latch parity error for even or odd parity`
394			`-- ----------------------------------------------------------------------------`
395			`parity_choice <= bit8 & odd_n_even ;`
396
397			`make_parity_err : PROCESS (clk, aresetn)`
398			`BEGIN`
399			`IF (aresetn = '0') THEN`
400			`parity_err_xhdl2 <= '0';`
401			`ELSIF (clk'EVENT AND clk = '1') THEN`
402			`IF (sresetn = '0') THEN`
403			`parity_err_xhdl2 <= '0';`
404			`ELSE`
405			`IF ((baud_clock = '1' AND parity_en = '1') AND receive_count = "1111") THEN`
406			`CASE parity_choice IS`
407			`WHEN "00" =>`
408			`IF (rx_bit_cnt = "0111") THEN`
409			`parity_err_xhdl2 <= rx_parity_calc XOR rx_filtered;`
410			`END IF;`
411			`WHEN "01" =>`
412			`IF (rx_bit_cnt = "0111") THEN`
413			`parity_err_xhdl2 <= NOT (rx_parity_calc XOR rx_filtered);`
414			`END IF;`
415			`WHEN "10" =>`
416			`IF (rx_bit_cnt = "1000") THEN`
417			`parity_err_xhdl2 <= rx_parity_calc XOR rx_filtered;`
418			`END IF;`
419			`WHEN "11" =>`
420			`IF (rx_bit_cnt = "1000") THEN`
421			`parity_err_xhdl2 <= NOT (rx_parity_calc XOR rx_filtered);`
422			`END IF;`
423			`WHEN OTHERS =>`
424			`parity_err_xhdl2 <= '0';`
425
426			`END CASE;`
427			`END IF;`
428			`-- if (read_rx_byte == 1'b1)`
429
430			`IF (clear_parity = '1') THEN`
431			`parity_err_xhdl2 <= '0';`
432			`END IF;`
433			`END IF;`
434			`END IF;`
435			`END PROCESS make_parity_err;`
436
437			`-- ----------------------------------------------------------------------------`
438			`-- receive full indicator process`
439			`-- ----------------------------------------------------------------------------`
440
441			`receive_full_indicator : PROCESS (clk, aresetn)`
442			`BEGIN`
443			`IF (aresetn = '0') THEN`
444			`receive_full_int <= '0';`
445			`fifo_write_xhdl6 <= '1';`
446			`clear_parity_en_xhdl3 <= '0';`
447			`clear_framing_error_en_i <= '0';`
448			`ELSIF (clk'EVENT AND clk = '1') THEN`
449			`IF (sresetn = '0') THEN`
450			`receive_full_int <= '0';`
451			`fifo_write_xhdl6 <= '1';`
452			`clear_parity_en_xhdl3 <= '0';`
453			`clear_framing_error_en_i <= '0';`
454			`ELSE`
455			`fifo_write_xhdl6 <= '1';`
456			`clear_parity_en_xhdl3 <= '0';`
457			`clear_framing_error_en_i <= '0';`
458			`IF (baud_clock = '1') THEN`
459			`-- last bit has been received`
460
461			`IF (bit8 = '1') THEN`
462			`IF (parity_en = '1') THEN`
463			`IF (rx_bit_cnt = "1001" AND rx_state = rx_data_bits) THEN`
464			`fifo_write_xhdl6 <= '0';`
465			`clear_parity_en_xhdl3 <= '1';`
466			`clear_framing_error_en_i <= '1';`
467			`IF (RX_FIFO = 2#0#) THEN`
468			`receive_full_int <= '1';`
469			`END IF;`
470			`END IF;`
471			`ELSE`
472			`IF (rx_bit_cnt = "1000" AND rx_state = rx_data_bits) THEN`
473			`fifo_write_xhdl6 <= '0';`
474			`clear_parity_en_xhdl3 <= '1';`
475			`clear_framing_error_en_i <= '1';`
476			`IF (RX_FIFO = 2#0#) THEN`
477			`receive_full_int <= '1';`
478			`END IF;`
479			`END IF;`
480			`END IF;`
481			`ELSE`
482			`IF (parity_en = '1') THEN`
483			`IF (rx_bit_cnt = "1000" AND rx_state = rx_data_bits) THEN`
484			`fifo_write_xhdl6 <= '0';`
485			`clear_parity_en_xhdl3 <= '1';`
486			`clear_framing_error_en_i <= '1';`
487			`IF (RX_FIFO = 2#0#) THEN`
488			`receive_full_int <= '1';`
489			`END IF;`
490			`END IF;`
491			`ELSE`
492			`IF (rx_bit_cnt = "0111" AND rx_state = rx_data_bits) THEN`
493			`fifo_write_xhdl6 <= '0';`
494			`clear_parity_en_xhdl3 <= '1';`
495			`clear_framing_error_en_i <= '1';`
496			`IF (RX_FIFO = 2#0#) THEN`
497			`receive_full_int <= '1';`
498			`END IF;`
499			`END IF;`
500			`END IF;`
501			`END IF;`
502			`END IF;`
503			`IF (read_rx_byte = '1') THEN`
504			`receive_full_int <= '0';`
505			`END IF;`
506			`END IF;`
507			`END IF;`
508			`END PROCESS receive_full_indicator;`
509			`receive_full_xhdl4 <= receive_full_int ;`
510
511			`END ARCHITECTURE translated;`