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top./top.sdbSDB./top_DRC.xmllog./top_DataSheet.xmllog./top_manifest.txtLOG../../Actel/DirectCore/CoreAHB2APB/1.1.101/CoreAHB2APB.cxfCXF../../Actel/DirectCore/CoreAHBLite/5.3.101/CoreAHBLite.cxfCXF./CoreAHBLite_0/top_CoreAHBLite_0_CoreAHBLite.cxfCXF../../Actel/DirectCore/CoreAPB/1.1.101/CoreAPB.cxfCXF../../Actel/DirectCore/CoreUARTapb/5.6.102/CoreUARTapb.cxfCXF./CoreUARTapb_0/top_CoreUARTapb_0_CoreUARTapb.cxfCXF./top.vhdVHDLSource./subsystem.bfmunknownOTHER_FILESETCOMPONENT_FILESETOTHERHDL_FILESETHDLANY_SIMULATION_FILESETSIMULATIONSmartCoreDesignSmartDesignSmartDesignActel1.0SmartCoreDesignfalseHCLKinfalsefalsetrueHRESETninfalsefalsetrueLREADinfalsefalsetrueLWRITEinfalsefalsetrueahb_busyoutfalsefalsetrueTXoutfalsefalsetrueADDRin310falsefalsetrueDATAINin310falsefalsetrueDATAOUTout310falsefalsetrueRESP_errout10falsefalsetrue
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