URL https://opencores.org/ocsvn/ahbmaster/ahbmaster/trunk

Subversion Repositories ahbmaster

[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [component/] [work/] [top/] [top_DataSheet.xml] - Blame information for rev 3

Details | Compare with Previous | View Log





  top
  
    ProASIC3
    A3PN250
    100 VQFP
    STD
    1.5
    VHDL
    
    
    C:/Actelprj/test79_AHBmaster/component/work/top
    GENERATED ( Sat Jun 02 22:53:04 2018 )
    SoftConsole workspace has not been generated
  
  
  
  
    HDL File(s)
    C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd
    C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_addrdec.vhd
    C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_defaultslavesm.vhd
    C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd
    C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd
    C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_pkg.vhd
    C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd
    C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavestage.vhd
    C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd
    C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\MuxP2B.vhd
    C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\components.vhd
    C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd
    C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd
    C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\components.vhd
    C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd
    C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd
    C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\coreuart_pkg.vhd
    C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\fifo_256x8_pa3.vhd
    C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd
    C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd
    C:\Actelprj\test79_AHBmaster\component\work\top\top.vhd
    C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd
    C:\Actelprj\test79_AHBmaster\smartgen\FlashROM\FlashROM.vhd
  
  
    ADDR[6]
    IN
    -
    LVTTL
  
  
    DATAOUT[2]
    OUT
    -
    LVTTL
  
  
    ADDR[1]
    IN
    -
    LVTTL
  
  
    DATAOUT[24]
    OUT
    -
    LVTTL
  
  
    DATAIN[7]
    IN
    -
    LVTTL
  
  
    DATAIN[11]
    IN
    -
    LVTTL
  
  
    ADDR[0]
    IN
    -
    LVTTL
  
  
    ADDR[23]
    IN
    -
    LVTTL
  
  
    ADDR[15]
    IN
    -
    LVTTL
  
  
    DATAOUT[13]
    OUT
    -
    LVTTL
  
  
    DATAIN[25]
    IN
    -
    LVTTL
  
  
    ADDR[24]
    IN
    -
    LVTTL
  
  
    ADDR[2]
    IN
    -
    LVTTL
  
  
    DATAOUT[20]
    OUT
    -
    LVTTL
  
  
    DATAOUT[8]
    OUT
    -
    LVTTL
  
  
    ADDR[27]
    IN
    -
    LVTTL
  
  
    ADDR[18]
    IN
    -
    LVTTL
  
  
    DATAIN[26]
    IN
    -
    LVTTL
  
  
    DATAOUT[9]
    OUT
    -
    LVTTL
  
  
    LWRITE
    IN
    -
    LVTTL
  
  
    DATAOUT[31]
    OUT
    -
    LVTTL
  
  
    DATAIN[18]
    IN
    -
    LVTTL
  
  
    DATAOUT[26]
    OUT
    -
    LVTTL
  
  
    DATAIN[13]
    IN
    -
    LVTTL
  
  
    DATAOUT[25]
    OUT
    -
    LVTTL
  
  
    DATAIN[12]
    IN
    -
    LVTTL
  
  
    DATAIN[20]
    IN
    -
    LVTTL
  
  
    DATAIN[1]
    IN
    -
    LVTTL
  
  
    ADDR[25]
    IN
    -
    LVTTL
  
  
    ADDR[28]
    IN
    -
    LVTTL
  
  
    DATAOUT[3]
    OUT
    -
    LVTTL
  
  
    ADDR[9]
    IN
    -
    LVTTL
  
  
    DATAIN[27]
    IN
    -
    LVTTL
  
  
    DATAOUT[27]
    OUT
    -
    LVTTL
  
  
    DATAIN[14]
    IN
    -
    LVTTL
  
  
    DATAIN[29]
    IN
    -
    LVTTL
  
  
    RESP_err[1]
    OUT
    -
    LVTTL
  
  
    DATAOUT[10]
    OUT
    -
    LVTTL
  
  
    DATAOUT[14]
    OUT
    -
    LVTTL
  
  
    RESP_err[0]
    OUT
    -
    LVTTL
  
  
    LREAD
    IN
    -
    LVTTL
  
  
    DATAIN[8]
    IN
    -
    LVTTL
  
  
    ADDR[3]
    IN
    -
    LVTTL
  
  
    DATAIN[3]
    IN
    -
    LVTTL
  
  
    DATAIN[2]
    IN
    -
    LVTTL
  
  
    ADDR[16]
    IN
    -
    LVTTL
  
  
    ADDR[19]
    IN
    -
    LVTTL
  
  
    ADDR[11]
    IN
    -
    LVTTL
  
  
    ADDR[10]
    IN
    -
    LVTTL
  
  
    ADDR[4]
    IN
    -
    LVTTL
  
  
    DATAOUT[22]
    OUT
    -
    LVTTL
  
  
    DATAIN[9]
    IN
    -
    LVTTL
  
  
    DATAIN[21]
    IN
    -
    LVTTL
  
  
    DATAOUT[21]
    OUT
    -
    LVTTL
  
  
    DATAIN[4]
    IN
    -
    LVTTL
  
  
    DATAOUT[16]
    OUT
    -
    LVTTL
  
  
    DATAOUT[4]
    OUT
    -
    LVTTL
  
  
    DATAOUT[15]
    OUT
    -
    LVTTL
  
  
    ADDR[12]
    IN
    -
    LVTTL
  
  
    DATAIN[30]
    IN
    -
    LVTTL
  
  
    TX
    OUT
    -
    LVTTL
  
  
    DATAOUT[28]
    OUT
    -
    LVTTL
  
  
    DATAIN[15]
    IN
    -
    LVTTL
  
  
    DATAOUT[17]
    OUT
    -
    LVTTL
  
  
    ADDR[5]
    IN
    -
    LVTTL
  
  
    ADDR[26]
    IN
    -
    LVTTL
  
  
    ADDR[21]
    IN
    -
    LVTTL
  
  
    ADDR[20]
    IN
    -
    LVTTL
  
  
    DATAOUT[29]
    OUT
    -
    LVTTL
  
  
    DATAIN[16]
    IN
    -
    LVTTL
  
  
    DATAIN[28]
    IN
    -
    LVTTL
  
  
    DATAOUT[0]
    OUT
    -
    LVTTL
  
  
    DATAIN[23]
    IN
    -
    LVTTL
  
  
    DATAIN[22]
    IN
    -
    LVTTL
  
  
    ahb_busy
    OUT
    -
    LVTTL
  
  
    DATAOUT[11]
    OUT
    -
    LVTTL
  
  
    HCLK
    IN
    -
    LVTTL
  
  
    DATAOUT[6]
    OUT
    -
    LVTTL
  
  
    ADDR[22]
    IN
    -
    LVTTL
  
  
    DATAOUT[5]
    OUT
    -
    LVTTL
  
  
    ADDR[7]
    IN
    -
    LVTTL
  
  
    DATAOUT[23]
    OUT
    -
    LVTTL
  
  
    DATAIN[10]
    IN
    -
    LVTTL
  
  
    DATAIN[24]
    IN
    -
    LVTTL
  
  
    DATAOUT[12]
    OUT
    -
    LVTTL
  
  
    DATAOUT[30]
    OUT
    -
    LVTTL
  
  
    DATAIN[17]
    IN
    -
    LVTTL
  
  
    DATAOUT[7]
    OUT
    -
    LVTTL
  
  
    DATAIN[5]
    IN
    -
    LVTTL
  
  
    DATAIN[31]
    IN
    -
    LVTTL
  
  
    ADDR[31]
    IN
    -
    LVTTL
  
  
    ADDR[13]
    IN
    -
    LVTTL
  
  
    HRESETn
    IN
    -
    LVTTL
  
  
    ADDR[30]
    IN
    -
    LVTTL
  
  
    DATAIN[6]
    IN
    -
    LVTTL
  
  
    ADDR[14]
    IN
    -
    LVTTL
  
  
    ADDR[17]
    IN
    -
    LVTTL
  
  
    DATAOUT[18]
    OUT
    -
    LVTTL
  
  
    ADDR[29]
    IN
    -
    LVTTL
  
  
    DATAIN[0]
    IN
    -
    LVTTL
  
  
    DATAOUT[1]
    OUT
    -
    LVTTL
  
  
    ADDR[8]
    IN
    -
    LVTTL
  
  
    DATAIN[19]
    IN
    -
    LVTTL
  
  
    DATAOUT[19]
    OUT
    -
    LVTTL
  
  
    AHBMASTER_FIC_0
  
  
    IP
    SpiritModule
    Actel
    DirectCore
    CoreAHB2APB
    1.1.101
    
The CoreAHB2APB is an AHB slave which provides an interface (bridge) between the high- speed AHB domain and the low-power APB domain.
        
    CoreAHB2APB_0
  
  
    IP
    SpiritModule
    Actel
    DirectCore
    CoreAHBLite
    5.3.101
    
The CoreAHBLite component implements a multi-master AHB-Lite bus. It provides up to 4 AHB-Lite master interfaces, and up to 16 AHB-Lite slave interfaces. It is possible to allocate one or more slave slots to a "combined region" that is accessed through a further slave interface. Slave slots allocated to the combined region are not available for separate connection.
        
    
      FPGA Family:
      ProASIC3
      FAMILY
      15
      spirit:hwParameter
    
    
      Address range seen by slave connected to huge (2GB) slot interface:
      0x80000000 - 0xFFFFFFFF
      HADDR_SHG_CFG
      1
      spirit:hwParameter
    
    
      M0 can access slot 0:
      true
      M0_AHBSLOT0ENABLE
      1
      spirit:hwParameter
    
    
      M0 can access slot 1:
      false
      M0_AHBSLOT1ENABLE
      0
      spirit:hwParameter
    
    
      M0 can access slot 2:
      false
      M0_AHBSLOT2ENABLE
      0
      spirit:hwParameter
    
    
      M0 can access slot 3:
      false
      M0_AHBSLOT3ENABLE
      0
      spirit:hwParameter
    
    
      M0 can access slot 4:
      false
      M0_AHBSLOT4ENABLE
      0
      spirit:hwParameter
    
    
      M0 can access slot 5:
      false
      M0_AHBSLOT5ENABLE
      0
      spirit:hwParameter
    
    
      M0 can access slot 6:
      false
      M0_AHBSLOT6ENABLE
      0
      spirit:hwParameter
    
    
      M0 can access slot 7:
      false
      M0_AHBSLOT7ENABLE
      0
      spirit:hwParameter
    
    
      M0 can access slot 8:
      false
      M0_AHBSLOT8ENABLE
      0
      spirit:hwParameter
    
    
      M0 can access slot 9:
      false
      M0_AHBSLOT9ENABLE
      0
      spirit:hwParameter
    
    
      M0 can access slot 10:
      false
      M0_AHBSLOT10ENABLE
      0
      spirit:hwParameter
    
    
      M0 can access slot 11:
      false
      M0_AHBSLOT11ENABLE
      0
      spirit:hwParameter
    
    
      M0 can access slot 12:
      false
      M0_AHBSLOT12ENABLE
      0
      spirit:hwParameter
    
    
      M0 can access slot 13:
      false
      M0_AHBSLOT13ENABLE
      0
      spirit:hwParameter
    
    
      M0 can access slot 14:
      false
      M0_AHBSLOT14ENABLE
      0
      spirit:hwParameter
    
    
      M0 can access slot 15:
      false
      M0_AHBSLOT15ENABLE
      0
      spirit:hwParameter
    
    
      M0 can access slot 16 (combined/huge):
      false
      M0_AHBSLOT16ENABLE
      0
      spirit:hwParameter
    
    
      M1 can access slot 0:
      false
      M1_AHBSLOT0ENABLE
      0
      spirit:hwParameter
    
    
      M1 can access slot 1:
      false
      M1_AHBSLOT1ENABLE
      0
      spirit:hwParameter
    
    
      M1 can access slot 2:
      false
      M1_AHBSLOT2ENABLE
      0
      spirit:hwParameter
    
    
      M1 can access slot 3:
      false
      M1_AHBSLOT3ENABLE
      0
      spirit:hwParameter
    
    
      M1 can access slot 4:
      false
      M1_AHBSLOT4ENABLE
      0
      spirit:hwParameter
    
    
      M1 can access slot 5:
      false
      M1_AHBSLOT5ENABLE
      0
      spirit:hwParameter
    
    
      M1 can access slot 6:
      false
      M1_AHBSLOT6ENABLE
      0
      spirit:hwParameter
    
    
      M1 can access slot 7:
      false
      M1_AHBSLOT7ENABLE
      0
      spirit:hwParameter
    
    
      M1 can access slot 8:
      false
      M1_AHBSLOT8ENABLE
      0
      spirit:hwParameter
    
    
      M1 can access slot 9:
      false
      M1_AHBSLOT9ENABLE
      0
      spirit:hwParameter
    
    
      M1 can access slot 10:
      false
      M1_AHBSLOT10ENABLE
      0
      spirit:hwParameter
    
    
      M1 can access slot 11:
      false
      M1_AHBSLOT11ENABLE
      0
      spirit:hwParameter
    
    
      M1 can access slot 12:
      false
      M1_AHBSLOT12ENABLE
      0
      spirit:hwParameter
    
    
      M1 can access slot 13:
      false
      M1_AHBSLOT13ENABLE
      0
      spirit:hwParameter
    
    
      M1 can access slot 14:
      false
      M1_AHBSLOT14ENABLE
      0
      spirit:hwParameter
    
    
      M1 can access slot 15:
      false
      M1_AHBSLOT15ENABLE
      0
      spirit:hwParameter
    
    
      M1 can access slot 16 (combined/huge):
      false
      M1_AHBSLOT16ENABLE
      0
      spirit:hwParameter
    
    
      M2 can access slot 0:
      false
      M2_AHBSLOT0ENABLE
      0
      spirit:hwParameter
    
    
      M2 can access slot 1:
      false
      M2_AHBSLOT1ENABLE
      0
      spirit:hwParameter
    
    
      M2 can access slot 2:
      false
      M2_AHBSLOT2ENABLE
      0
      spirit:hwParameter
    
    
      M2 can access slot 3:
      false
      M2_AHBSLOT3ENABLE
      0
      spirit:hwParameter
    
    
      M2 can access slot 4:
      false
      M2_AHBSLOT4ENABLE
      0
      spirit:hwParameter
    
    
      M2 can access slot 5:
      false
      M2_AHBSLOT5ENABLE
      0
      spirit:hwParameter
    
    
      M2 can access slot 6:
      false
      M2_AHBSLOT6ENABLE
      0
      spirit:hwParameter
    
    
      M2 can access slot 7:
      false
      M2_AHBSLOT7ENABLE
      0
      spirit:hwParameter
    
    
      M2 can access slot 8:
      false
      M2_AHBSLOT8ENABLE
      0
      spirit:hwParameter
    
    
      M2 can access slot 9:
      false
      M2_AHBSLOT9ENABLE
      0
      spirit:hwParameter
    
    
      M2 can access slot 10:
      false
      M2_AHBSLOT10ENABLE
      0
      spirit:hwParameter
    
    
      M2 can access slot 11:
      false
      M2_AHBSLOT11ENABLE
      0
      spirit:hwParameter
    
    
      M2 can access slot 12:
      false
      M2_AHBSLOT12ENABLE
      0
      spirit:hwParameter
    
    
      M2 can access slot 13:
      false
      M2_AHBSLOT13ENABLE
      0
      spirit:hwParameter
    
    
      M2 can access slot 14:
      false
      M2_AHBSLOT14ENABLE
      0
      spirit:hwParameter
    
    
      M2 can access slot 15:
      false
      M2_AHBSLOT15ENABLE
      0
      spirit:hwParameter
    
    
      M2 can access slot 16 (combined/huge):
      false
      M2_AHBSLOT16ENABLE
      0
      spirit:hwParameter
    
    
      M3 can access slot 0:
      false
      M3_AHBSLOT0ENABLE
      0
      spirit:hwParameter
    
    
      M3 can access slot 1:
      false
      M3_AHBSLOT1ENABLE
      0
      spirit:hwParameter
    
    
      M3 can access slot 2:
      false
      M3_AHBSLOT2ENABLE
      0
      spirit:hwParameter
    
    
      M3 can access slot 3:
      false
      M3_AHBSLOT3ENABLE
      0
      spirit:hwParameter
    
    
      M3 can access slot 4:
      false
      M3_AHBSLOT4ENABLE
      0
      spirit:hwParameter
    
    
      M3 can access slot 5:
      false
      M3_AHBSLOT5ENABLE
      0
      spirit:hwParameter
    
    
      M3 can access slot 6:
      false
      M3_AHBSLOT6ENABLE
      0
      spirit:hwParameter
    
    
      M3 can access slot 7:
      false
      M3_AHBSLOT7ENABLE
      0
      spirit:hwParameter
    
    
      M3 can access slot 8:
      false
      M3_AHBSLOT8ENABLE
      0
      spirit:hwParameter
    
    
      M3 can access slot 9:
      false
      M3_AHBSLOT9ENABLE
      0
      spirit:hwParameter
    
    
      M3 can access slot 10:
      false
      M3_AHBSLOT10ENABLE
      0
      spirit:hwParameter
    
    
      M3 can access slot 11:
      false
      M3_AHBSLOT11ENABLE
      0
      spirit:hwParameter
    
    
      M3 can access slot 12:
      false
      M3_AHBSLOT12ENABLE
      0
      spirit:hwParameter
    
    
      M3 can access slot 13:
      false
      M3_AHBSLOT13ENABLE
      0
      spirit:hwParameter
    
    
      M3 can access slot 14:
      false
      M3_AHBSLOT14ENABLE
      0
      spirit:hwParameter
    
    
      M3 can access slot 15:
      false
      M3_AHBSLOT15ENABLE
      0
      spirit:hwParameter
    
    
      M3 can access slot 16 (combined/huge):
      false
      M3_AHBSLOT16ENABLE
      0
      spirit:hwParameter
    
    
      Memory space:
      4GB addressable space apportioned into 16 slave slots, each of size 256MB
      MEMSPACE
      1
      spirit:hwParameter
    
    
      Slot 0:
      false
      SC_0
      0
      spirit:hwParameter
    
    
      Slot 1:
      false
      SC_1
      0
      spirit:hwParameter
    
    
      Slot 2:
      false
      SC_2
      0
      spirit:hwParameter
    
    
      Slot 3:
      false
      SC_3
      0
      spirit:hwParameter
    
    
      Slot 4:
      false
      SC_4
      0
      spirit:hwParameter
    
    
      Slot 5:
      false
      SC_5
      0
      spirit:hwParameter
    
    
      Slot 6:
      false
      SC_6
      0
      spirit:hwParameter
    
    
      Slot 7:
      false
      SC_7
      0
      spirit:hwParameter
    
    
      Slot 8:
      false
      SC_8
      0
      spirit:hwParameter
    
    
      Slot 9:
      false
      SC_9
      0
      spirit:hwParameter
    
    
      Slot 10:
      false
      SC_10
      0
      spirit:hwParameter
    
    
      Slot 11:
      false
      SC_11
      0
      spirit:hwParameter
    
    
      Slot 12:
      false
      SC_12
      0
      spirit:hwParameter
    
    
      Slot 13:
      false
      SC_13
      0
      spirit:hwParameter
    
    
      Slot 14:
      false
      SC_14
      0
      spirit:hwParameter
    
    
      Slot 15:
      false
      SC_15
      0
      spirit:hwParameter
    
    CoreAHBLite_0
  
  
    IP
    SpiritModule
    Actel
    DirectCore
    CoreAPB
    1.1.101
    
The CoreAPB controller implements an AMBA APB fabric with the same implementation model
as the CoreAHBLite controller. The CoreAHB2APB bridge does the actual address decoding
and SEL generation so primarily what this component does is the PRDATA multiplexing.
 
There is one APB Master interface which is typically connected to the CoreAPB bridge,
and 16 APB slave interfaces. There are 16 slots available each of 16MB addressable
space each.
 
        
    
      Slot 0:
      true
      ApbSlot0Enable
      1
      spirit:hwParameter
    
    
      Slot 1:
      false
      ApbSlot1Enable
      0
      spirit:hwParameter
    
    
      Slot 2:
      false
      ApbSlot2Enable
      0
      spirit:hwParameter
    
    
      Slot 3:
      false
      ApbSlot3Enable
      0
      spirit:hwParameter
    
    
      Slot 4:
      false
      ApbSlot4Enable
      0
      spirit:hwParameter
    
    
      Slot 5:
      false
      ApbSlot5Enable
      0
      spirit:hwParameter
    
    
      Slot 6:
      false
      ApbSlot6Enable
      0
      spirit:hwParameter
    
    
      Slot 7:
      false
      ApbSlot7Enable
      0
      spirit:hwParameter
    
    
      Slot 8:
      false
      ApbSlot8Enable
      0
      spirit:hwParameter
    
    
      Slot 9:
      false
      ApbSlot9Enable
      0
      spirit:hwParameter
    
    
      Slot 10:
      false
      ApbSlot10Enable
      0
      spirit:hwParameter
    
    
      Slot 11:
      false
      ApbSlot11Enable
      0
      spirit:hwParameter
    
    
      Slot 12:
      false
      ApbSlot12Enable
      0
      spirit:hwParameter
    
    
      Slot 13:
      false
      ApbSlot13Enable
      0
      spirit:hwParameter
    
    
      Slot 14:
      false
      ApbSlot14Enable
      0
      spirit:hwParameter
    
    
      Slot 15:
      false
      ApbSlot15Enable
      0
      spirit:hwParameter
    
    CoreAPB_0
  
  
    IP
    SpiritModule
    Actel
    DirectCore
    CoreUARTapb
    5.6.102
    CoreUARTapb is a serial communication controller with a flexible serial data interface that is intended primarily for embedded systems. The controller operates as an asynchronous (UART) with a control register interface and APB wrapper.
    
      Fractional Part of Baud Value:
      +0.0
      BAUD_VAL_FRCTN
      0
      spirit:hwParameter
    
    
      Enable Extra Precision:
      false
      BAUD_VAL_FRCTN_EN
      0
      spirit:hwParameter
    
    
      Baud Value:
      1
      BAUD_VALUE
      1
      spirit:hwParameter
    
    
      FPGA Family:
      ProASIC3
      FAMILY
      15
      spirit:hwParameter
    
    
      Configuration:
      Fixed
      FIXEDMODE
      1
      spirit:hwParameter
    
    
      Character Size:
      8 bits
      PRG_BIT8
      1
      spirit:hwParameter
    
    
      Parity:
      Parity Disabled
      PRG_PARITY
      0
      spirit:hwParameter
    
    
      RX FIFO:
      Disable RX FIFO
      RX_FIFO
      0
      spirit:hwParameter
    
    
      RX Legacy Mode:
      Disabled
      RX_LEGACY_MODE
      0
      spirit:hwParameter
    
    
      TX FIFO:
      Disable TX FIFO
      TX_FIFO
      0
      spirit:hwParameter
    
    CoreUARTapb_0
  
  
    Memory Map for top
    The project contains the following subsystems:
    
      
        AHBMASTER_FIC_0
        AHBMASTER_FIC_0
        
          2
          NoRemap
          M0_SwapSlots0and1
        
        
          CoreUARTapb_0
          CoreUARTapb_0:APB_bif
          0x00000000
          0x00000000 - 0x00FFFFFF
          0x10000000
          0x10000000 - 0x10FFFFFF
          0x01000000
        
      
    
  


Browse

Tools

Subversion Repositories ahbmaster

[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [component/] [work/] [top/] [top_DataSheet.xml] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	uson
2
3
4			`top`
5
6			`ProASIC3`
7			`A3PN250`
8			`100 VQFP`
9			`STD`
10			`1.5`
11			`VHDL`
12
13
14			`C:/Actelprj/test79_AHBmaster/component/work/top`
15			`GENERATED ( Sat Jun 02 22:53:04 2018 )`
16			`SoftConsole workspace has not been generated`
17
18
19
20
21			`HDL File(s)`
22			`C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd`
23			`C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_addrdec.vhd`
24			`C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_defaultslavesm.vhd`
25			`C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd`
26			`C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd`
27			`C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_pkg.vhd`
28			`C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd`
29			`C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavestage.vhd`
30			`C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd`
31			`C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\MuxP2B.vhd`
32			`C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\components.vhd`
33			`C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd`
34			`C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd`
35			`C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\components.vhd`
36			`C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd`
37			`C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd`
38			`C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\coreuart_pkg.vhd`
39			`C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\fifo_256x8_pa3.vhd`
40			`C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd`
41			`C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd`
42			`C:\Actelprj\test79_AHBmaster\component\work\top\top.vhd`
43			`C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd`
44			`C:\Actelprj\test79_AHBmaster\smartgen\FlashROM\FlashROM.vhd`
45
46
47			`ADDR[6]`
48			`IN`
49			`-`
50			`LVTTL`
51
52
53			`DATAOUT[2]`
54			`OUT`
55			`-`
56			`LVTTL`
57
58
59			`ADDR[1]`
60			`IN`
61			`-`
62			`LVTTL`
63
64
65			`DATAOUT[24]`
66			`OUT`
67			`-`
68			`LVTTL`
69
70
71			`DATAIN[7]`
72			`IN`
73			`-`
74			`LVTTL`
75
76
77			`DATAIN[11]`
78			`IN`
79			`-`
80			`LVTTL`
81
82
83			`ADDR[0]`
84			`IN`
85			`-`
86			`LVTTL`
87
88
89			`ADDR[23]`
90			`IN`
91			`-`
92			`LVTTL`
93
94
95			`ADDR[15]`
96			`IN`
97			`-`
98			`LVTTL`
99
100
101			`DATAOUT[13]`
102			`OUT`
103			`-`
104			`LVTTL`
105
106
107			`DATAIN[25]`
108			`IN`
109			`-`
110			`LVTTL`
111
112
113			`ADDR[24]`
114			`IN`
115			`-`
116			`LVTTL`
117
118
119			`ADDR[2]`
120			`IN`
121			`-`
122			`LVTTL`
123
124
125			`DATAOUT[20]`
126			`OUT`
127			`-`
128			`LVTTL`
129
130
131			`DATAOUT[8]`
132			`OUT`
133			`-`
134			`LVTTL`
135
136
137			`ADDR[27]`
138			`IN`
139			`-`
140			`LVTTL`
141
142
143			`ADDR[18]`
144			`IN`
145			`-`
146			`LVTTL`
147
148
149			`DATAIN[26]`
150			`IN`
151			`-`
152			`LVTTL`
153
154
155			`DATAOUT[9]`
156			`OUT`
157			`-`
158			`LVTTL`
159
160
161			`LWRITE`
162			`IN`
163			`-`
164			`LVTTL`
165
166
167			`DATAOUT[31]`
168			`OUT`
169			`-`
170			`LVTTL`
171
172
173			`DATAIN[18]`
174			`IN`
175			`-`
176			`LVTTL`
177
178
179			`DATAOUT[26]`
180			`OUT`
181			`-`
182			`LVTTL`
183
184
185			`DATAIN[13]`
186			`IN`
187			`-`
188			`LVTTL`
189
190
191			`DATAOUT[25]`
192			`OUT`
193			`-`
194			`LVTTL`
195
196
197			`DATAIN[12]`
198			`IN`
199			`-`
200			`LVTTL`
201
202
203			`DATAIN[20]`
204			`IN`
205			`-`
206			`LVTTL`
207
208
209			`DATAIN[1]`
210			`IN`
211			`-`
212			`LVTTL`
213
214
215			`ADDR[25]`
216			`IN`
217			`-`
218			`LVTTL`
219
220
221			`ADDR[28]`
222			`IN`
223			`-`
224			`LVTTL`
225
226
227			`DATAOUT[3]`
228			`OUT`
229			`-`
230			`LVTTL`
231
232
233			`ADDR[9]`
234			`IN`
235			`-`
236			`LVTTL`
237
238
239			`DATAIN[27]`
240			`IN`
241			`-`
242			`LVTTL`
243
244
245			`DATAOUT[27]`
246			`OUT`
247			`-`
248			`LVTTL`
249
250
251			`DATAIN[14]`
252			`IN`
253			`-`
254			`LVTTL`
255
256
257			`DATAIN[29]`
258			`IN`
259			`-`
260			`LVTTL`
261
262
263			`RESP_err[1]`
264			`OUT`
265			`-`
266			`LVTTL`
267
268
269			`DATAOUT[10]`
270			`OUT`
271			`-`
272			`LVTTL`
273
274
275			`DATAOUT[14]`
276			`OUT`
277			`-`
278			`LVTTL`
279
280
281			`RESP_err[0]`
282			`OUT`
283			`-`
284			`LVTTL`
285
286
287			`LREAD`
288			`IN`
289			`-`
290			`LVTTL`
291
292
293			`DATAIN[8]`
294			`IN`
295			`-`
296			`LVTTL`
297
298
299			`ADDR[3]`
300			`IN`
301			`-`
302			`LVTTL`
303
304
305			`DATAIN[3]`
306			`IN`
307			`-`
308			`LVTTL`
309
310
311			`DATAIN[2]`
312			`IN`
313			`-`
314			`LVTTL`
315
316
317			`ADDR[16]`
318			`IN`
319			`-`
320			`LVTTL`
321
322
323			`ADDR[19]`
324			`IN`
325			`-`
326			`LVTTL`
327
328
329			`ADDR[11]`
330			`IN`
331			`-`
332			`LVTTL`
333
334
335			`ADDR[10]`
336			`IN`
337			`-`
338			`LVTTL`
339
340
341			`ADDR[4]`
342			`IN`
343			`-`
344			`LVTTL`
345
346
347			`DATAOUT[22]`
348			`OUT`
349			`-`
350			`LVTTL`
351
352
353			`DATAIN[9]`
354			`IN`
355			`-`
356			`LVTTL`
357
358
359			`DATAIN[21]`
360			`IN`
361			`-`
362			`LVTTL`
363
364
365			`DATAOUT[21]`
366			`OUT`
367			`-`
368			`LVTTL`
369
370
371			`DATAIN[4]`
372			`IN`
373			`-`
374			`LVTTL`
375
376
377			`DATAOUT[16]`
378			`OUT`
379			`-`
380			`LVTTL`
381
382
383			`DATAOUT[4]`
384			`OUT`
385			`-`
386			`LVTTL`
387
388
389			`DATAOUT[15]`
390			`OUT`
391			`-`
392			`LVTTL`
393
394
395			`ADDR[12]`
396			`IN`
397			`-`
398			`LVTTL`
399
400
401			`DATAIN[30]`
402			`IN`
403			`-`
404			`LVTTL`
405
406
407			`TX`
408			`OUT`
409			`-`
410			`LVTTL`
411
412
413			`DATAOUT[28]`
414			`OUT`
415			`-`
416			`LVTTL`
417
418
419			`DATAIN[15]`
420			`IN`
421			`-`
422			`LVTTL`
423
424
425			`DATAOUT[17]`
426			`OUT`
427			`-`
428			`LVTTL`
429
430
431			`ADDR[5]`
432			`IN`
433			`-`
434			`LVTTL`
435
436
437			`ADDR[26]`
438			`IN`
439			`-`
440			`LVTTL`
441
442
443			`ADDR[21]`
444			`IN`
445			`-`
446			`LVTTL`
447
448
449			`ADDR[20]`
450			`IN`
451			`-`
452			`LVTTL`
453
454
455			`DATAOUT[29]`
456			`OUT`
457			`-`
458			`LVTTL`
459
460
461			`DATAIN[16]`
462			`IN`
463			`-`
464			`LVTTL`
465
466
467			`DATAIN[28]`
468			`IN`
469			`-`
470			`LVTTL`
471
472
473			`DATAOUT[0]`
474			`OUT`
475			`-`
476			`LVTTL`
477
478
479			`DATAIN[23]`
480			`IN`
481			`-`
482			`LVTTL`
483
484
485			`DATAIN[22]`
486			`IN`
487			`-`
488			`LVTTL`
489
490
491			`ahb_busy`
492			`OUT`
493			`-`
494			`LVTTL`
495
496
497			`DATAOUT[11]`
498			`OUT`
499			`-`
500			`LVTTL`
501
502
503			`HCLK`
504			`IN`
505			`-`
506			`LVTTL`
507
508
509			`DATAOUT[6]`
510			`OUT`
511			`-`
512			`LVTTL`
513
514
515			`ADDR[22]`
516			`IN`
517			`-`
518			`LVTTL`
519
520
521			`DATAOUT[5]`
522			`OUT`
523			`-`
524			`LVTTL`
525
526
527			`ADDR[7]`
528			`IN`
529			`-`
530			`LVTTL`
531
532
533			`DATAOUT[23]`
534			`OUT`
535			`-`
536			`LVTTL`
537
538
539			`DATAIN[10]`
540			`IN`
541			`-`
542			`LVTTL`
543
544
545			`DATAIN[24]`
546			`IN`
547			`-`
548			`LVTTL`
549
550
551			`DATAOUT[12]`
552			`OUT`
553			`-`
554			`LVTTL`
555
556
557			`DATAOUT[30]`
558			`OUT`
559			`-`
560			`LVTTL`
561
562
563			`DATAIN[17]`
564			`IN`
565			`-`
566			`LVTTL`
567
568
569			`DATAOUT[7]`
570			`OUT`
571			`-`
572			`LVTTL`
573
574
575			`DATAIN[5]`
576			`IN`
577			`-`
578			`LVTTL`
579
580
581			`DATAIN[31]`
582			`IN`
583			`-`
584			`LVTTL`
585
586
587			`ADDR[31]`
588			`IN`
589			`-`
590			`LVTTL`
591
592
593			`ADDR[13]`
594			`IN`
595			`-`
596			`LVTTL`
597
598
599			`HRESETn`
600			`IN`
601			`-`
602			`LVTTL`
603
604
605			`ADDR[30]`
606			`IN`
607			`-`
608			`LVTTL`
609
610
611			`DATAIN[6]`
612			`IN`
613			`-`
614			`LVTTL`
615
616
617			`ADDR[14]`
618			`IN`
619			`-`
620			`LVTTL`
621
622
623			`ADDR[17]`
624			`IN`
625			`-`
626			`LVTTL`
627
628
629			`DATAOUT[18]`
630			`OUT`
631			`-`
632			`LVTTL`
633
634
635			`ADDR[29]`
636			`IN`
637			`-`
638			`LVTTL`
639
640
641			`DATAIN[0]`
642			`IN`
643			`-`
644			`LVTTL`
645
646
647			`DATAOUT[1]`
648			`OUT`
649			`-`
650			`LVTTL`
651
652
653			`ADDR[8]`
654			`IN`
655			`-`
656			`LVTTL`
657
658
659			`DATAIN[19]`
660			`IN`
661			`-`
662			`LVTTL`
663
664
665			`DATAOUT[19]`
666			`OUT`
667			`-`
668			`LVTTL`
669
670
671			`AHBMASTER_FIC_0`
672
673
674			`IP`
675			`SpiritModule`
676			`Actel`
677			`DirectCore`
678			`CoreAHB2APB`
679			`1.1.101`
680
681			`The CoreAHB2APB is an AHB slave which provides an interface (bridge) between the high- speed AHB domain and the low-power APB domain.`
682
683			`CoreAHB2APB_0`
684
685
686			`IP`
687			`SpiritModule`
688			`Actel`
689			`DirectCore`
690			`CoreAHBLite`
691			`5.3.101`
692
693			`The CoreAHBLite component implements a multi-master AHB-Lite bus. It provides up to 4 AHB-Lite master interfaces, and up to 16 AHB-Lite slave interfaces. It is possible to allocate one or more slave slots to a "combined region" that is accessed through a further slave interface. Slave slots allocated to the combined region are not available for separate connection.`
694
695
696			`FPGA Family:`
697			`ProASIC3`
698			`FAMILY`
699			`15`
700			`spirit:hwParameter`
701
702
703			`Address range seen by slave connected to huge (2GB) slot interface:`
704			`0x80000000 - 0xFFFFFFFF`
705			`HADDR_SHG_CFG`
706			`1`
707			`spirit:hwParameter`
708
709
710			`M0 can access slot 0:`
711			`true`
712			`M0_AHBSLOT0ENABLE`
713			`1`
714			`spirit:hwParameter`
715
716
717			`M0 can access slot 1:`
718			`false`
719			`M0_AHBSLOT1ENABLE`
720			`0`
721			`spirit:hwParameter`
722
723
724			`M0 can access slot 2:`
725			`false`
726			`M0_AHBSLOT2ENABLE`
727			`0`
728			`spirit:hwParameter`
729
730
731			`M0 can access slot 3:`
732			`false`
733			`M0_AHBSLOT3ENABLE`
734			`0`
735			`spirit:hwParameter`
736
737
738			`M0 can access slot 4:`
739			`false`
740			`M0_AHBSLOT4ENABLE`
741			`0`
742			`spirit:hwParameter`
743
744
745			`M0 can access slot 5:`
746			`false`
747			`M0_AHBSLOT5ENABLE`
748			`0`
749			`spirit:hwParameter`
750
751
752			`M0 can access slot 6:`
753			`false`
754			`M0_AHBSLOT6ENABLE`
755			`0`
756			`spirit:hwParameter`
757
758
759			`M0 can access slot 7:`
760			`false`
761			`M0_AHBSLOT7ENABLE`
762			`0`
763			`spirit:hwParameter`
764
765
766			`M0 can access slot 8:`
767			`false`
768			`M0_AHBSLOT8ENABLE`
769			`0`
770			`spirit:hwParameter`
771
772
773			`M0 can access slot 9:`
774			`false`
775			`M0_AHBSLOT9ENABLE`
776			`0`
777			`spirit:hwParameter`
778
779
780			`M0 can access slot 10:`
781			`false`
782			`M0_AHBSLOT10ENABLE`
783			`0`
784			`spirit:hwParameter`
785
786
787			`M0 can access slot 11:`
788			`false`
789			`M0_AHBSLOT11ENABLE`
790			`0`
791			`spirit:hwParameter`
792
793
794			`M0 can access slot 12:`
795			`false`
796			`M0_AHBSLOT12ENABLE`
797			`0`
798			`spirit:hwParameter`
799
800
801			`M0 can access slot 13:`
802			`false`
803			`M0_AHBSLOT13ENABLE`
804			`0`
805			`spirit:hwParameter`
806
807
808			`M0 can access slot 14:`
809			`false`
810			`M0_AHBSLOT14ENABLE`
811			`0`
812			`spirit:hwParameter`
813
814
815			`M0 can access slot 15:`
816			`false`
817			`M0_AHBSLOT15ENABLE`
818			`0`
819			`spirit:hwParameter`
820
821
822			`M0 can access slot 16 (combined/huge):`
823			`false`
824			`M0_AHBSLOT16ENABLE`
825			`0`
826			`spirit:hwParameter`
827
828
829			`M1 can access slot 0:`
830			`false`
831			`M1_AHBSLOT0ENABLE`
832			`0`
833			`spirit:hwParameter`
834
835
836			`M1 can access slot 1:`
837			`false`
838			`M1_AHBSLOT1ENABLE`
839			`0`
840			`spirit:hwParameter`
841
842
843			`M1 can access slot 2:`
844			`false`
845			`M1_AHBSLOT2ENABLE`
846			`0`
847			`spirit:hwParameter`
848
849
850			`M1 can access slot 3:`
851			`false`
852			`M1_AHBSLOT3ENABLE`
853			`0`
854			`spirit:hwParameter`
855
856
857			`M1 can access slot 4:`
858			`false`
859			`M1_AHBSLOT4ENABLE`
860			`0`
861			`spirit:hwParameter`
862
863
864			`M1 can access slot 5:`
865			`false`
866			`M1_AHBSLOT5ENABLE`
867			`0`
868			`spirit:hwParameter`
869
870
871			`M1 can access slot 6:`
872			`false`
873			`M1_AHBSLOT6ENABLE`
874			`0`
875			`spirit:hwParameter`
876
877
878			`M1 can access slot 7:`
879			`false`
880			`M1_AHBSLOT7ENABLE`
881			`0`
882			`spirit:hwParameter`
883
884
885			`M1 can access slot 8:`
886			`false`
887			`M1_AHBSLOT8ENABLE`
888			`0`
889			`spirit:hwParameter`
890
891
892			`M1 can access slot 9:`
893			`false`
894			`M1_AHBSLOT9ENABLE`
895			`0`
896			`spirit:hwParameter`
897
898
899			`M1 can access slot 10:`
900			`false`
901			`M1_AHBSLOT10ENABLE`
902			`0`
903			`spirit:hwParameter`
904
905
906			`M1 can access slot 11:`
907			`false`
908			`M1_AHBSLOT11ENABLE`
909			`0`
910			`spirit:hwParameter`
911
912
913			`M1 can access slot 12:`
914			`false`
915			`M1_AHBSLOT12ENABLE`
916			`0`
917			`spirit:hwParameter`
918
919
920			`M1 can access slot 13:`
921			`false`
922			`M1_AHBSLOT13ENABLE`
923			`0`
924			`spirit:hwParameter`
925
926
927			`M1 can access slot 14:`
928			`false`
929			`M1_AHBSLOT14ENABLE`
930			`0`
931			`spirit:hwParameter`
932
933
934			`M1 can access slot 15:`
935			`false`
936			`M1_AHBSLOT15ENABLE`
937			`0`
938			`spirit:hwParameter`
939
940
941			`M1 can access slot 16 (combined/huge):`
942			`false`
943			`M1_AHBSLOT16ENABLE`
944			`0`
945			`spirit:hwParameter`
946
947
948			`M2 can access slot 0:`
949			`false`
950			`M2_AHBSLOT0ENABLE`
951			`0`
952			`spirit:hwParameter`
953
954
955			`M2 can access slot 1:`
956			`false`
957			`M2_AHBSLOT1ENABLE`
958			`0`
959			`spirit:hwParameter`
960
961
962			`M2 can access slot 2:`
963			`false`
964			`M2_AHBSLOT2ENABLE`
965			`0`
966			`spirit:hwParameter`
967
968
969			`M2 can access slot 3:`
970			`false`
971			`M2_AHBSLOT3ENABLE`
972			`0`
973			`spirit:hwParameter`
974
975
976			`M2 can access slot 4:`
977			`false`
978			`M2_AHBSLOT4ENABLE`
979			`0`
980			`spirit:hwParameter`
981
982
983			`M2 can access slot 5:`
984			`false`
985			`M2_AHBSLOT5ENABLE`
986			`0`
987			`spirit:hwParameter`
988
989
990			`M2 can access slot 6:`
991			`false`
992			`M2_AHBSLOT6ENABLE`
993			`0`
994			`spirit:hwParameter`
995
996
997			`M2 can access slot 7:`
998			`false`
999			`M2_AHBSLOT7ENABLE`
1000			`0`
1001			`spirit:hwParameter`
1002
1003
1004			`M2 can access slot 8:`
1005			`false`
1006			`M2_AHBSLOT8ENABLE`
1007			`0`
1008			`spirit:hwParameter`
1009
1010
1011			`M2 can access slot 9:`
1012			`false`
1013			`M2_AHBSLOT9ENABLE`
1014			`0`
1015			`spirit:hwParameter`
1016
1017
1018			`M2 can access slot 10:`
1019			`false`
1020			`M2_AHBSLOT10ENABLE`
1021			`0`
1022			`spirit:hwParameter`
1023
1024
1025			`M2 can access slot 11:`
1026			`false`
1027			`M2_AHBSLOT11ENABLE`
1028			`0`
1029			`spirit:hwParameter`
1030
1031
1032			`M2 can access slot 12:`
1033			`false`
1034			`M2_AHBSLOT12ENABLE`
1035			`0`
1036			`spirit:hwParameter`
1037
1038
1039			`M2 can access slot 13:`
1040			`false`
1041			`M2_AHBSLOT13ENABLE`
1042			`0`
1043			`spirit:hwParameter`
1044
1045
1046			`M2 can access slot 14:`
1047			`false`
1048			`M2_AHBSLOT14ENABLE`
1049			`0`
1050			`spirit:hwParameter`
1051
1052
1053			`M2 can access slot 15:`
1054			`false`
1055			`M2_AHBSLOT15ENABLE`
1056			`0`
1057			`spirit:hwParameter`
1058
1059
1060			`M2 can access slot 16 (combined/huge):`
1061			`false`
1062			`M2_AHBSLOT16ENABLE`
1063			`0`
1064			`spirit:hwParameter`
1065
1066
1067			`M3 can access slot 0:`
1068			`false`
1069			`M3_AHBSLOT0ENABLE`
1070			`0`
1071			`spirit:hwParameter`
1072
1073
1074			`M3 can access slot 1:`
1075			`false`
1076			`M3_AHBSLOT1ENABLE`
1077			`0`
1078			`spirit:hwParameter`
1079
1080
1081			`M3 can access slot 2:`
1082			`false`
1083			`M3_AHBSLOT2ENABLE`
1084			`0`
1085			`spirit:hwParameter`
1086
1087
1088			`M3 can access slot 3:`
1089			`false`
1090			`M3_AHBSLOT3ENABLE`
1091			`0`
1092			`spirit:hwParameter`
1093
1094
1095			`M3 can access slot 4:`
1096			`false`
1097			`M3_AHBSLOT4ENABLE`
1098			`0`
1099			`spirit:hwParameter`
1100
1101
1102			`M3 can access slot 5:`
1103			`false`
1104			`M3_AHBSLOT5ENABLE`
1105			`0`
1106			`spirit:hwParameter`
1107
1108
1109			`M3 can access slot 6:`
1110			`false`
1111			`M3_AHBSLOT6ENABLE`
1112			`0`
1113			`spirit:hwParameter`
1114
1115
1116			`M3 can access slot 7:`
1117			`false`
1118			`M3_AHBSLOT7ENABLE`
1119			`0`
1120			`spirit:hwParameter`
1121
1122
1123			`M3 can access slot 8:`
1124			`false`
1125			`M3_AHBSLOT8ENABLE`
1126			`0`
1127			`spirit:hwParameter`
1128
1129
1130			`M3 can access slot 9:`
1131			`false`
1132			`M3_AHBSLOT9ENABLE`
1133			`0`
1134			`spirit:hwParameter`
1135
1136
1137			`M3 can access slot 10:`
1138			`false`
1139			`M3_AHBSLOT10ENABLE`
1140			`0`
1141			`spirit:hwParameter`
1142
1143
1144			`M3 can access slot 11:`
1145			`false`
1146			`M3_AHBSLOT11ENABLE`
1147			`0`
1148			`spirit:hwParameter`
1149
1150
1151			`M3 can access slot 12:`
1152			`false`
1153			`M3_AHBSLOT12ENABLE`
1154			`0`
1155			`spirit:hwParameter`
1156
1157
1158			`M3 can access slot 13:`
1159			`false`
1160			`M3_AHBSLOT13ENABLE`
1161			`0`
1162			`spirit:hwParameter`
1163
1164
1165			`M3 can access slot 14:`
1166			`false`
1167			`M3_AHBSLOT14ENABLE`
1168			`0`
1169			`spirit:hwParameter`
1170
1171
1172			`M3 can access slot 15:`
1173			`false`
1174			`M3_AHBSLOT15ENABLE`
1175			`0`
1176			`spirit:hwParameter`
1177
1178
1179			`M3 can access slot 16 (combined/huge):`
1180			`false`
1181			`M3_AHBSLOT16ENABLE`
1182			`0`
1183			`spirit:hwParameter`
1184
1185
1186			`Memory space:`
1187			`4GB addressable space apportioned into 16 slave slots, each of size 256MB`
1188			`MEMSPACE`
1189			`1`
1190			`spirit:hwParameter`
1191
1192
1193			`Slot 0:`
1194			`false`
1195			`SC_0`
1196			`0`
1197			`spirit:hwParameter`
1198
1199
1200			`Slot 1:`
1201			`false`
1202			`SC_1`
1203			`0`
1204			`spirit:hwParameter`
1205
1206
1207			`Slot 2:`
1208			`false`
1209			`SC_2`
1210			`0`
1211			`spirit:hwParameter`
1212
1213
1214			`Slot 3:`
1215			`false`
1216			`SC_3`
1217			`0`
1218			`spirit:hwParameter`
1219
1220
1221			`Slot 4:`
1222			`false`
1223			`SC_4`
1224			`0`
1225			`spirit:hwParameter`
1226
1227
1228			`Slot 5:`
1229			`false`
1230			`SC_5`
1231			`0`
1232			`spirit:hwParameter`
1233
1234
1235			`Slot 6:`
1236			`false`
1237			`SC_6`
1238			`0`
1239			`spirit:hwParameter`
1240
1241
1242			`Slot 7:`
1243			`false`
1244			`SC_7`
1245			`0`
1246			`spirit:hwParameter`
1247
1248
1249			`Slot 8:`
1250			`false`
1251			`SC_8`
1252			`0`
1253			`spirit:hwParameter`
1254
1255
1256			`Slot 9:`
1257			`false`
1258			`SC_9`
1259			`0`
1260			`spirit:hwParameter`
1261
1262
1263			`Slot 10:`
1264			`false`
1265			`SC_10`
1266			`0`
1267			`spirit:hwParameter`
1268
1269
1270			`Slot 11:`
1271			`false`
1272			`SC_11`
1273			`0`
1274			`spirit:hwParameter`
1275
1276
1277			`Slot 12:`
1278			`false`
1279			`SC_12`
1280			`0`
1281			`spirit:hwParameter`
1282
1283
1284			`Slot 13:`
1285			`false`
1286			`SC_13`
1287			`0`
1288			`spirit:hwParameter`
1289
1290
1291			`Slot 14:`
1292			`false`
1293			`SC_14`
1294			`0`
1295			`spirit:hwParameter`
1296
1297
1298			`Slot 15:`
1299			`false`
1300			`SC_15`
1301			`0`
1302			`spirit:hwParameter`
1303
1304			`CoreAHBLite_0`
1305
1306
1307			`IP`
1308			`SpiritModule`
1309			`Actel`
1310			`DirectCore`
1311			`CoreAPB`
1312			`1.1.101`
1313
1314			`The CoreAPB controller implements an AMBA APB fabric with the same implementation model`
1315			`as the CoreAHBLite controller. The CoreAHB2APB bridge does the actual address decoding`
1316			`and SEL generation so primarily what this component does is the PRDATA multiplexing.`
1317
1318			`There is one APB Master interface which is typically connected to the CoreAPB bridge,`
1319			`and 16 APB slave interfaces. There are 16 slots available each of 16MB addressable`
1320			`space each.`
1321
1322
1323
1324			`Slot 0:`
1325			`true`
1326			`ApbSlot0Enable`
1327			`1`
1328			`spirit:hwParameter`
1329
1330
1331			`Slot 1:`
1332			`false`
1333			`ApbSlot1Enable`
1334			`0`
1335			`spirit:hwParameter`
1336
1337
1338			`Slot 2:`
1339			`false`
1340			`ApbSlot2Enable`
1341			`0`
1342			`spirit:hwParameter`
1343
1344
1345			`Slot 3:`
1346			`false`
1347			`ApbSlot3Enable`
1348			`0`
1349			`spirit:hwParameter`
1350
1351
1352			`Slot 4:`
1353			`false`
1354			`ApbSlot4Enable`
1355			`0`
1356			`spirit:hwParameter`
1357
1358
1359			`Slot 5:`
1360			`false`
1361			`ApbSlot5Enable`
1362			`0`
1363			`spirit:hwParameter`
1364
1365
1366			`Slot 6:`
1367			`false`
1368			`ApbSlot6Enable`
1369			`0`
1370			`spirit:hwParameter`
1371
1372
1373			`Slot 7:`
1374			`false`
1375			`ApbSlot7Enable`
1376			`0`
1377			`spirit:hwParameter`
1378
1379
1380			`Slot 8:`
1381			`false`
1382			`ApbSlot8Enable`
1383			`0`
1384			`spirit:hwParameter`
1385
1386
1387			`Slot 9:`
1388			`false`
1389			`ApbSlot9Enable`
1390			`0`
1391			`spirit:hwParameter`
1392
1393
1394			`Slot 10:`
1395			`false`
1396			`ApbSlot10Enable`
1397			`0`
1398			`spirit:hwParameter`
1399
1400
1401			`Slot 11:`
1402			`false`
1403			`ApbSlot11Enable`
1404			`0`
1405			`spirit:hwParameter`
1406
1407
1408			`Slot 12:`
1409			`false`
1410			`ApbSlot12Enable`
1411			`0`
1412			`spirit:hwParameter`
1413
1414
1415			`Slot 13:`
1416			`false`
1417			`ApbSlot13Enable`
1418			`0`
1419			`spirit:hwParameter`
1420
1421
1422			`Slot 14:`
1423			`false`
1424			`ApbSlot14Enable`
1425			`0`
1426			`spirit:hwParameter`
1427
1428
1429			`Slot 15:`
1430			`false`
1431			`ApbSlot15Enable`
1432			`0`
1433			`spirit:hwParameter`
1434
1435			`CoreAPB_0`
1436
1437
1438			`IP`
1439			`SpiritModule`
1440			`Actel`
1441			`DirectCore`
1442			`CoreUARTapb`
1443			`5.6.102`
1444			`CoreUARTapb is a serial communication controller with a flexible serial data interface that is intended primarily for embedded systems. The controller operates as an asynchronous (UART) with a control register interface and APB wrapper.`
1445
1446			`Fractional Part of Baud Value:`
1447			`+0.0`
1448			`BAUD_VAL_FRCTN`
1449			`0`
1450			`spirit:hwParameter`
1451
1452
1453			`Enable Extra Precision:`
1454			`false`
1455			`BAUD_VAL_FRCTN_EN`
1456			`0`
1457			`spirit:hwParameter`
1458
1459
1460			`Baud Value:`
1461			`1`
1462			`BAUD_VALUE`
1463			`1`
1464			`spirit:hwParameter`
1465
1466
1467			`FPGA Family:`
1468			`ProASIC3`
1469			`FAMILY`
1470			`15`
1471			`spirit:hwParameter`
1472
1473
1474			`Configuration:`
1475			`Fixed`
1476			`FIXEDMODE`
1477			`1`
1478			`spirit:hwParameter`
1479
1480
1481			`Character Size:`
1482			`8 bits`
1483			`PRG_BIT8`
1484			`1`
1485			`spirit:hwParameter`
1486
1487
1488			`Parity:`
1489			`Parity Disabled`
1490			`PRG_PARITY`
1491			`0`
1492			`spirit:hwParameter`
1493
1494
1495			`RX FIFO:`
1496			`Disable RX FIFO`
1497			`RX_FIFO`
1498			`0`
1499			`spirit:hwParameter`
1500
1501
1502			`RX Legacy Mode:`
1503			`Disabled`
1504			`RX_LEGACY_MODE`
1505			`0`
1506			`spirit:hwParameter`
1507
1508
1509			`TX FIFO:`
1510			`Disable TX FIFO`
1511			`TX_FIFO`
1512			`0`
1513			`spirit:hwParameter`
1514
1515			`CoreUARTapb_0`
1516
1517
1518			`Memory Map for top`
1519			`The project contains the following subsystems:`
1520
1521
1522			`AHBMASTER_FIC_0`
1523			`AHBMASTER_FIC_0`
1524
1525			`2`
1526			`NoRemap`
1527			`M0_SwapSlots0and1`
1528
1529
1530			`CoreUARTapb_0`
1531			`CoreUARTapb_0:APB_bif`
1532			`0x00000000`
1533			`0x00000000 - 0x00FFFFFF`
1534			`0x10000000`
1535			`0x10000000 - 0x10FFFFFF`
1536			`0x01000000`
1537
1538
1539
1540
1541