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// ********************************************************************
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// Actel Corporation Proprietary and Confidential
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// Copyright 2010 Actel Corporation. All rights reserved.
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//
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// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
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// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
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// IN ADVANCE IN WRITING.
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//
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// Description: User testbench include file for CoreAHBLite - contains
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// various constants, procedures, etc. used by main BFM script
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//
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//
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// SVN Revision Information:
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// SVN $Revision: 21348 $
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// SVN $Date: 2013-10-23 20:30:39 +0530 (Wed, 23 Oct 2013) $
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//
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//
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// Notes:
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// 1. best viewed with tabstops set to "4"
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//
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//
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// *********************************************************************
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memmap BASE 0x00000000;
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// constants
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constant mode0_slot_incr 0x10000000;
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constant mode1_slot_incr 0x10000;
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constant mode1_client_incr 0x1000;
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constant huge_slotsize 0x80000000;
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// global variables to store local copy of testbench parameters and constants
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// derived from testbench parameters
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int FAMILY
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int MEMSPACE
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int HADDR_SHG_CFG
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int SC_0
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int SC_1
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int SC_2
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int SC_3
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int SC_4
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int SC_5
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int SC_6
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int SC_7
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int SC_8
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int SC_9
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int SC_10
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int SC_11
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int SC_12
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int SC_13
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int SC_14
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int SC_15
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int M0_AHBSLOT0ENABLE
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int M0_AHBSLOT1ENABLE
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int M0_AHBSLOT2ENABLE
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int M0_AHBSLOT3ENABLE
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int M0_AHBSLOT4ENABLE
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int M0_AHBSLOT5ENABLE
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int M0_AHBSLOT6ENABLE
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int M0_AHBSLOT7ENABLE
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int M0_AHBSLOT8ENABLE
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int M0_AHBSLOT9ENABLE
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int M0_AHBSLOT10ENABLE
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int M0_AHBSLOT11ENABLE
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int M0_AHBSLOT12ENABLE
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int M0_AHBSLOT13ENABLE
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int M0_AHBSLOT14ENABLE
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int M0_AHBSLOT15ENABLE
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int M0_AHBSLOT16ENABLE
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int M1_AHBSLOT0ENABLE
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int M1_AHBSLOT1ENABLE
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int M1_AHBSLOT2ENABLE
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int M1_AHBSLOT3ENABLE
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int M1_AHBSLOT4ENABLE
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int M1_AHBSLOT5ENABLE
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int M1_AHBSLOT6ENABLE
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int M1_AHBSLOT7ENABLE
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int M1_AHBSLOT8ENABLE
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int M1_AHBSLOT9ENABLE
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int M1_AHBSLOT10ENABLE
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int M1_AHBSLOT11ENABLE
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int M1_AHBSLOT12ENABLE
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int M1_AHBSLOT13ENABLE
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int M1_AHBSLOT14ENABLE
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int M1_AHBSLOT15ENABLE
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int M1_AHBSLOT16ENABLE
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int M2_AHBSLOT0ENABLE
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int M2_AHBSLOT1ENABLE
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int M2_AHBSLOT2ENABLE
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int M2_AHBSLOT3ENABLE
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int M2_AHBSLOT4ENABLE
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int M2_AHBSLOT5ENABLE
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int M2_AHBSLOT6ENABLE
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int M2_AHBSLOT7ENABLE
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int M2_AHBSLOT8ENABLE
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int M2_AHBSLOT9ENABLE
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int M2_AHBSLOT10ENABLE
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int M2_AHBSLOT11ENABLE
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int M2_AHBSLOT12ENABLE
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int M2_AHBSLOT13ENABLE
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int M2_AHBSLOT14ENABLE
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int M2_AHBSLOT15ENABLE
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int M2_AHBSLOT16ENABLE
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int M3_AHBSLOT0ENABLE
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int M3_AHBSLOT1ENABLE
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int M3_AHBSLOT2ENABLE
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int M3_AHBSLOT3ENABLE
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int M3_AHBSLOT4ENABLE
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int M3_AHBSLOT5ENABLE
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int M3_AHBSLOT6ENABLE
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int M3_AHBSLOT7ENABLE
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int M3_AHBSLOT8ENABLE
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int M3_AHBSLOT9ENABLE
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int M3_AHBSLOT10ENABLE
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int M3_AHBSLOT11ENABLE
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int M3_AHBSLOT12ENABLE
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int M3_AHBSLOT13ENABLE
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int M3_AHBSLOT14ENABLE
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int M3_AHBSLOT15ENABLE
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int M3_AHBSLOT16ENABLE
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int SC[16]
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int M0_AHBSLOTENABLE[17]
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int M1_AHBSLOTENABLE[17]
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int M2_AHBSLOTENABLE[17]
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int M3_AHBSLOTENABLE[17]
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// GP_OUT bits that can be set/cleared from the BFM
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constant REMAP_M0_BIT 0
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// GP_OUT bits that can be set/cleared from the BFM - also connecting to
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// GP_IN bits in testbench that can be monitored
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constant M0_REQ_BIT 16
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constant M0_ACK_BIT 17
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constant M1_REQ_BIT 18
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constant M1_ACK_BIT 19
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//---------------------------------------------------------------------------
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// print line of underscores
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//---------------------------------------------------------------------------
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procedure pr_underscores
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print "____________________________________________________________________"
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print " "
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return
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//---------------------------------------------------------------------------
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// initialize local variables from the ARGVALUE* BFM parameters passed
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// down from the testbench HDL
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//---------------------------------------------------------------------------
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//procedure init_parameter_vars_temp
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procedure init_parameter_vars
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int i0
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int d0
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set FAMILY $ARGVALUE0
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set MEMSPACE $ARGVALUE1
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set HADDR_SHG_CFG $ARGVALUE2
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set SC_0 $ARGVALUE3
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set SC_1 $ARGVALUE4
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set SC_2 $ARGVALUE5
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set SC_3 $ARGVALUE6
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set SC_4 $ARGVALUE7
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set SC_5 $ARGVALUE8
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set SC_6 $ARGVALUE9
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set SC_7 $ARGVALUE10
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set SC_8 $ARGVALUE11
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set SC_9 $ARGVALUE12
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set SC_10 $ARGVALUE13
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set SC_11 $ARGVALUE14
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set SC_12 $ARGVALUE15
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set SC_13 $ARGVALUE16
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set SC_14 $ARGVALUE17
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set SC_15 $ARGVALUE18
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set M0_AHBSLOT0ENABLE $ARGVALUE19
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set M0_AHBSLOT1ENABLE $ARGVALUE20
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set M0_AHBSLOT2ENABLE $ARGVALUE21
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set M0_AHBSLOT3ENABLE $ARGVALUE22
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set M0_AHBSLOT4ENABLE $ARGVALUE23
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set M0_AHBSLOT5ENABLE $ARGVALUE24
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set M0_AHBSLOT6ENABLE $ARGVALUE25
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set M0_AHBSLOT7ENABLE $ARGVALUE26
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set M0_AHBSLOT8ENABLE $ARGVALUE27
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set M0_AHBSLOT9ENABLE $ARGVALUE28
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set M0_AHBSLOT10ENABLE $ARGVALUE29
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set M0_AHBSLOT11ENABLE $ARGVALUE30
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set M0_AHBSLOT12ENABLE $ARGVALUE31
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set M0_AHBSLOT13ENABLE $ARGVALUE32
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set M0_AHBSLOT14ENABLE $ARGVALUE33
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set M0_AHBSLOT15ENABLE $ARGVALUE34
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set M0_AHBSLOT16ENABLE $ARGVALUE35
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set M1_AHBSLOT0ENABLE $ARGVALUE36
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set M1_AHBSLOT1ENABLE $ARGVALUE37
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set M1_AHBSLOT2ENABLE $ARGVALUE38
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set M1_AHBSLOT3ENABLE $ARGVALUE39
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set M1_AHBSLOT4ENABLE $ARGVALUE40
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set M1_AHBSLOT5ENABLE $ARGVALUE41
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set M1_AHBSLOT6ENABLE $ARGVALUE42
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set M1_AHBSLOT7ENABLE $ARGVALUE43
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set M1_AHBSLOT8ENABLE $ARGVALUE44
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set M1_AHBSLOT9ENABLE $ARGVALUE45
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set M1_AHBSLOT10ENABLE $ARGVALUE46
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set M1_AHBSLOT11ENABLE $ARGVALUE47
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set M1_AHBSLOT12ENABLE $ARGVALUE48
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set M1_AHBSLOT13ENABLE $ARGVALUE49
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set M1_AHBSLOT14ENABLE $ARGVALUE50
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set M1_AHBSLOT15ENABLE $ARGVALUE51
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set M1_AHBSLOT16ENABLE $ARGVALUE52
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set M2_AHBSLOT0ENABLE $ARGVALUE53
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set M2_AHBSLOT1ENABLE $ARGVALUE54
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set M2_AHBSLOT2ENABLE $ARGVALUE55
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set M2_AHBSLOT3ENABLE $ARGVALUE56
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set M2_AHBSLOT4ENABLE $ARGVALUE57
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set M2_AHBSLOT5ENABLE $ARGVALUE58
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set M2_AHBSLOT6ENABLE $ARGVALUE59
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set M2_AHBSLOT7ENABLE $ARGVALUE60
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set M2_AHBSLOT8ENABLE $ARGVALUE61
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set M2_AHBSLOT9ENABLE $ARGVALUE62
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set M2_AHBSLOT10ENABLE $ARGVALUE63
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set M2_AHBSLOT11ENABLE $ARGVALUE64
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set M2_AHBSLOT12ENABLE $ARGVALUE65
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set M2_AHBSLOT13ENABLE $ARGVALUE66
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set M2_AHBSLOT14ENABLE $ARGVALUE67
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set M2_AHBSLOT15ENABLE $ARGVALUE68
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set M2_AHBSLOT16ENABLE $ARGVALUE69
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set M3_AHBSLOT0ENABLE $ARGVALUE70
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set M3_AHBSLOT1ENABLE $ARGVALUE71
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set M3_AHBSLOT2ENABLE $ARGVALUE72
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set M3_AHBSLOT3ENABLE $ARGVALUE73
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set M3_AHBSLOT4ENABLE $ARGVALUE74
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set M3_AHBSLOT5ENABLE $ARGVALUE75
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set M3_AHBSLOT6ENABLE $ARGVALUE76
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set M3_AHBSLOT7ENABLE $ARGVALUE77
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set M3_AHBSLOT8ENABLE $ARGVALUE78
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set M3_AHBSLOT9ENABLE $ARGVALUE79
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set M3_AHBSLOT10ENABLE $ARGVALUE80
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set M3_AHBSLOT11ENABLE $ARGVALUE81
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set M3_AHBSLOT12ENABLE $ARGVALUE82
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set M3_AHBSLOT13ENABLE $ARGVALUE83
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set M3_AHBSLOT14ENABLE $ARGVALUE84
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set M3_AHBSLOT15ENABLE $ARGVALUE85
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set M3_AHBSLOT16ENABLE $ARGVALUE86
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// aggregate parameters
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set SC[0] SC_0
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set SC[1] SC_1
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set SC[2] SC_2
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set SC[3] SC_3
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set SC[4] SC_4
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set SC[5] SC_5
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set SC[6] SC_6
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set SC[7] SC_7
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set SC[8] SC_8
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set SC[9] SC_9
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set SC[10] SC_10
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set SC[11] SC_11
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set SC[12] SC_12
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set SC[13] SC_13
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set SC[14] SC_14
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set SC[15] SC_15
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set M0_AHBSLOTENABLE[0] M0_AHBSLOT0ENABLE
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set M0_AHBSLOTENABLE[1] M0_AHBSLOT1ENABLE
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set M0_AHBSLOTENABLE[2] M0_AHBSLOT2ENABLE
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set M0_AHBSLOTENABLE[3] M0_AHBSLOT3ENABLE
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set M0_AHBSLOTENABLE[4] M0_AHBSLOT4ENABLE
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set M0_AHBSLOTENABLE[5] M0_AHBSLOT5ENABLE
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set M0_AHBSLOTENABLE[6] M0_AHBSLOT6ENABLE
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set M0_AHBSLOTENABLE[7] M0_AHBSLOT7ENABLE
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set M0_AHBSLOTENABLE[8] M0_AHBSLOT8ENABLE
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set M0_AHBSLOTENABLE[9] M0_AHBSLOT9ENABLE
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set M0_AHBSLOTENABLE[10] M0_AHBSLOT10ENABLE
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set M0_AHBSLOTENABLE[11] M0_AHBSLOT11ENABLE
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set M0_AHBSLOTENABLE[12] M0_AHBSLOT12ENABLE
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set M0_AHBSLOTENABLE[13] M0_AHBSLOT13ENABLE
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set M0_AHBSLOTENABLE[14] M0_AHBSLOT14ENABLE
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set M0_AHBSLOTENABLE[15] M0_AHBSLOT15ENABLE
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set M0_AHBSLOTENABLE[16] M0_AHBSLOT16ENABLE
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set M1_AHBSLOTENABLE[0] M1_AHBSLOT0ENABLE
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set M1_AHBSLOTENABLE[1] M1_AHBSLOT1ENABLE
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set M1_AHBSLOTENABLE[2] M1_AHBSLOT2ENABLE
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set M1_AHBSLOTENABLE[3] M1_AHBSLOT3ENABLE
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set M1_AHBSLOTENABLE[4] M1_AHBSLOT4ENABLE
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set M1_AHBSLOTENABLE[5] M1_AHBSLOT5ENABLE
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set M1_AHBSLOTENABLE[6] M1_AHBSLOT6ENABLE
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set M1_AHBSLOTENABLE[7] M1_AHBSLOT7ENABLE
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set M1_AHBSLOTENABLE[8] M1_AHBSLOT8ENABLE
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set M1_AHBSLOTENABLE[9] M1_AHBSLOT9ENABLE
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set M1_AHBSLOTENABLE[10] M1_AHBSLOT10ENABLE
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set M1_AHBSLOTENABLE[11] M1_AHBSLOT11ENABLE
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set M1_AHBSLOTENABLE[12] M1_AHBSLOT12ENABLE
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set M1_AHBSLOTENABLE[13] M1_AHBSLOT13ENABLE
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set M1_AHBSLOTENABLE[14] M1_AHBSLOT14ENABLE
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set M1_AHBSLOTENABLE[15] M1_AHBSLOT15ENABLE
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set M1_AHBSLOTENABLE[16] M1_AHBSLOT16ENABLE
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set M2_AHBSLOTENABLE[0] M2_AHBSLOT0ENABLE
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set M2_AHBSLOTENABLE[1] M2_AHBSLOT1ENABLE
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set M2_AHBSLOTENABLE[2] M2_AHBSLOT2ENABLE
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set M2_AHBSLOTENABLE[3] M2_AHBSLOT3ENABLE
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set M2_AHBSLOTENABLE[4] M2_AHBSLOT4ENABLE
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set M2_AHBSLOTENABLE[5] M2_AHBSLOT5ENABLE
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set M2_AHBSLOTENABLE[6] M2_AHBSLOT6ENABLE
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set M2_AHBSLOTENABLE[7] M2_AHBSLOT7ENABLE
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set M2_AHBSLOTENABLE[8] M2_AHBSLOT8ENABLE
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set M2_AHBSLOTENABLE[9] M2_AHBSLOT9ENABLE
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set M2_AHBSLOTENABLE[10] M2_AHBSLOT10ENABLE
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set M2_AHBSLOTENABLE[11] M2_AHBSLOT11ENABLE
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set M2_AHBSLOTENABLE[12] M2_AHBSLOT12ENABLE
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set M2_AHBSLOTENABLE[13] M2_AHBSLOT13ENABLE
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set M2_AHBSLOTENABLE[14] M2_AHBSLOT14ENABLE
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set M2_AHBSLOTENABLE[15] M2_AHBSLOT15ENABLE
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set M2_AHBSLOTENABLE[16] M2_AHBSLOT16ENABLE
|
314 |
|
|
|
315 |
|
|
set M3_AHBSLOTENABLE[0] M3_AHBSLOT0ENABLE
|
316 |
|
|
set M3_AHBSLOTENABLE[1] M3_AHBSLOT1ENABLE
|
317 |
|
|
set M3_AHBSLOTENABLE[2] M3_AHBSLOT2ENABLE
|
318 |
|
|
set M3_AHBSLOTENABLE[3] M3_AHBSLOT3ENABLE
|
319 |
|
|
set M3_AHBSLOTENABLE[4] M3_AHBSLOT4ENABLE
|
320 |
|
|
set M3_AHBSLOTENABLE[5] M3_AHBSLOT5ENABLE
|
321 |
|
|
set M3_AHBSLOTENABLE[6] M3_AHBSLOT6ENABLE
|
322 |
|
|
set M3_AHBSLOTENABLE[7] M3_AHBSLOT7ENABLE
|
323 |
|
|
set M3_AHBSLOTENABLE[8] M3_AHBSLOT8ENABLE
|
324 |
|
|
set M3_AHBSLOTENABLE[9] M3_AHBSLOT9ENABLE
|
325 |
|
|
set M3_AHBSLOTENABLE[10] M3_AHBSLOT10ENABLE
|
326 |
|
|
set M3_AHBSLOTENABLE[11] M3_AHBSLOT11ENABLE
|
327 |
|
|
set M3_AHBSLOTENABLE[12] M3_AHBSLOT12ENABLE
|
328 |
|
|
set M3_AHBSLOTENABLE[13] M3_AHBSLOT13ENABLE
|
329 |
|
|
set M3_AHBSLOTENABLE[14] M3_AHBSLOT14ENABLE
|
330 |
|
|
set M3_AHBSLOTENABLE[15] M3_AHBSLOT15ENABLE
|
331 |
|
|
set M3_AHBSLOTENABLE[16] M3_AHBSLOT16ENABLE
|
332 |
|
|
|
333 |
|
|
# print some variable values
|
334 |
|
|
call pr_underscores
|
335 |
|
|
|
336 |
|
|
print "MEMSPACE:%0d" MEMSPACE
|
337 |
|
|
print "HADDR_SHG_CFG:%0d" HADDR_SHG_CFG
|
338 |
|
|
|
339 |
|
|
loop i0 0 15 1
|
340 |
|
|
set d0 SC[i0]
|
341 |
|
|
print "SC bit:%0d is:%0d" i0 d0
|
342 |
|
|
endloop
|
343 |
|
|
loop i0 0 16 1
|
344 |
|
|
set d0 M0_AHBSLOTENABLE[i0]
|
345 |
|
|
print "M0_AHBSLOTENABLE bit:%0d is:%0d" i0 d0
|
346 |
|
|
endloop
|
347 |
|
|
loop i0 0 16 1
|
348 |
|
|
set d0 M1_AHBSLOTENABLE[i0]
|
349 |
|
|
print "M1_AHBSLOTENABLE bit:%0d is:%0d" i0 d0
|
350 |
|
|
endloop
|
351 |
|
|
loop i0 0 16 1
|
352 |
|
|
set d0 M2_AHBSLOTENABLE[i0]
|
353 |
|
|
print "M2_AHBSLOTENABLE bit:%0d is:%0d" i0 d0
|
354 |
|
|
endloop
|
355 |
|
|
loop i0 0 16 1
|
356 |
|
|
set d0 M3_AHBSLOTENABLE[i0]
|
357 |
|
|
print "M3_AHBSLOTENABLE bit:%0d is:%0d" i0 d0
|
358 |
|
|
endloop
|
359 |
|
|
|
360 |
|
|
call pr_underscores
|
361 |
|
|
|
362 |
|
|
return
|