Subversion Repositories ahbmaster

# Reading C:/Microsemi/Libero_SoC_v11.8/Modelsim/tcl/vsim/pref.tcl

# ERROR: No extended dataflow license exists

# do run.do

# Model Technology ModelSim Microsemi vmap 10.5c Lib Mapping Utility 2016.07 Jul 21 2016

# vmap postsynth postsynth

# Modifying modelsim.ini

# Model Technology ModelSim Microsemi vmap 10.5c Lib Mapping Utility 2016.07 Jul 21 2016

# vmap proasic3 C:/Microsemi/Libero_SoC_v11.8/Designer/lib/modelsim/precompiled/vhdl/proasic3

# Modifying modelsim.ini

# Model Technology ModelSim Microsemi vmap 10.5c Lib Mapping Utility 2016.07 Jul 21 2016

# vmap COREAHBLITE_LIB ../component/Actel/DirectCore/CoreAHBLite/5.3.101/mti/user_vhdl/COREAHBLITE_LIB

# Modifying modelsim.ini

# Model Technology ModelSim Microsemi vcom 10.5c Compiler 2016.07 Jul 21 2016

# Start time: 22:54:12 on Jun 02,2018

# vcom -reportprogress 300 -work COREAHBLITE_LIB -force_refresh

# -- Loading package STANDARD

# -- Loading package TEXTIO

# -- Loading package std_logic_1164

# -- Loading package NUMERIC_STD

# -- Loading package bfm_misc

# -- Loading package bfm_textio

# -- Loading package bfM_packAGE

# -- Compiling entity bfm_AHbl

# -- Compiling architecture BFMA1I10i of BFm_ahBL

# -- Compiling entity BFM_ahbSLAve

# -- Compiling architecture BFMA1Io1ol of bFM_ahbsLAVe

# -- Compiling entity bfM_AHbslaVEext

# -- Compiling architecture BFMA1io1OL of bfm_AHbslAVEext

# -- Compiling entity bFM_maiN

# -- Compiling architecture BFMA1i10I of bfM_Main

# -- Compiling package bfm_misc

# -- Compiling package body bfm_misc

# -- Loading package bfm_misc

# -- Loading package bfm_misc

# -- Loading package bfm_textio

# -- Compiling package bfM_packAGE

# -- Compiling package body bfM_packAGE

# -- Loading package bfM_packAGE

# -- Compiling package bfm_textio

# -- Compiling package body bfm_textio

# -- Loading package bfm_textio

# -- Loading package std_logic_arith

# -- Loading package bfm_textio

# -- Compiling entity bfm_textio_test

# -- Compiling architecture TB of bfm_textio_test

# End time: 22:54:12 on Jun 02,2018, Elapsed time: 0:00:00

# Errors: 0, Warnings: 0

# Model Technology ModelSim Microsemi vlog 10.5c Compiler 2016.07 Jul 21 2016

# Start time: 22:54:13 on Jun 02,2018

# vlog -reportprogress 300 -work COREAHBLITE_LIB -force_refresh

# -- Skipping entity bfm_ahbl

# -- Skipping entity bfm_ahbslave

# -- Skipping entity bfm_ahbslaveext

# -- Skipping entity bfm_main

# -- Skipping package bfm_misc

# -- Skipping package bfm_package

# -- Skipping package bfm_textio

# -- Skipping entity bfm_textio_test

# End time: 22:54:13 on Jun 02,2018, Elapsed time: 0:00:00

# Errors: 0, Warnings: 0

# Model Technology ModelSim Microsemi vmap 10.5c Lib Mapping Utility 2016.07 Jul 21 2016

# vmap COREUARTAPB_LIB COREUARTAPB_LIB

# Modifying modelsim.ini

# Model Technology ModelSim Microsemi vcom 10.5c Compiler 2016.07 Jul 21 2016

# Start time: 22:54:13 on Jun 02,2018

# vcom -reportprogress 300 -2008 -explicit -work COREAHBLITE_LIB C:/Actelprj/test79_AHBmaster/component/Actel/DirectCore/CoreAHBLite/5.3.101/rtl/vhdl/core/coreahblite_addrdec.vhd

# -- Loading package STANDARD

# -- Loading package TEXTIO

# -- Loading package std_logic_1164

# -- Loading package NUMERIC_STD

# -- Compiling package coreahblite_support

# -- Compiling package body coreahblite_support

# -- Loading package coreahblite_support

# -- Loading package coreahblite_support

# -- Compiling entity COREAHBLITE_ADDRDEC

# -- Compiling architecture COREAHBLITE_ADDRDEC_arch of COREAHBLITE_ADDRDEC

# End time: 22:54:13 on Jun 02,2018, Elapsed time: 0:00:00

# Errors: 0, Warnings: 0

# Model Technology ModelSim Microsemi vcom 10.5c Compiler 2016.07 Jul 21 2016

# Start time: 22:54:13 on Jun 02,2018

# vcom -reportprogress 300 -2008 -explicit -work COREAHBLITE_LIB C:/Actelprj/test79_AHBmaster/component/Actel/DirectCore/CoreAHBLite/5.3.101/rtl/vhdl/core/coreahblite_pkg.vhd

# -- Loading package STANDARD

# -- Compiling package coreahblite_pkg

# -- Compiling package body coreahblite_pkg

# -- Loading package coreahblite_pkg

# End time: 22:54:13 on Jun 02,2018, Elapsed time: 0:00:00

# Errors: 0, Warnings: 0

# Model Technology ModelSim Microsemi vcom 10.5c Compiler 2016.07 Jul 21 2016

# Start time: 22:54:13 on Jun 02,2018

# vcom -reportprogress 300 -2008 -explicit -work COREAHBLITE_LIB C:/Actelprj/test79_AHBmaster/component/work/top/CoreAHBLite_0/rtl/vhdl/core/components.vhd

# -- Loading package STANDARD

# -- Loading package TEXTIO

# -- Loading package std_logic_1164

# -- Compiling package top_CoreAHBLite_0_components

# End time: 22:54:13 on Jun 02,2018, Elapsed time: 0:00:00

# Errors: 0, Warnings: 0

# Model Technology ModelSim Microsemi vcom 10.5c Compiler 2016.07 Jul 21 2016

# Start time: 22:54:13 on Jun 02,2018

# vcom -reportprogress 300 -2008 -explicit -work COREUARTAPB_LIB C:/Actelprj/test79_AHBmaster/component/work/top/CoreUARTapb_0/rtl/vhdl/core/components.vhd

# -- Loading package STANDARD

# -- Loading package TEXTIO

# -- Loading package std_logic_1164

# -- Compiling package top_CoreUARTapb_0_components

# End time: 22:54:13 on Jun 02,2018, Elapsed time: 0:00:00

# Errors: 0, Warnings: 0

# Model Technology ModelSim Microsemi vcom 10.5c Compiler 2016.07 Jul 21 2016

# Start time: 22:54:13 on Jun 02,2018

# vcom -reportprogress 300 -2008 -explicit -work COREUARTAPB_LIB C:/Actelprj/test79_AHBmaster/component/work/top/CoreUARTapb_0/rtl/vhdl/core/coreuart_pkg.vhd

# -- Loading package STANDARD

# -- Compiling package top_CoreUARTapb_0_coreuart_pkg

# -- Compiling package body top_CoreUARTapb_0_coreuart_pkg

# -- Loading package top_CoreUARTapb_0_coreuart_pkg

# End time: 22:54:13 on Jun 02,2018, Elapsed time: 0:00:00

# Errors: 0, Warnings: 0

# Model Technology ModelSim Microsemi vcom 10.5c Compiler 2016.07 Jul 21 2016

# Start time: 22:54:14 on Jun 02,2018

# vcom -reportprogress 300 -2008 -explicit -work postsynth C:/Actelprj/test79_AHBmaster/synthesis/top.vhd

# -- Loading package STANDARD

# -- Loading package TEXTIO

# -- Loading package std_logic_1164

# -- Compiling entity AHBMASTER_FIC

# -- Compiling architecture DEF_ARCH of AHBMASTER_FIC

# -- Compiling entity COReAPB_l

# -- Compiling architecture DEF_ARCH of COReAPB_l

# -- Compiling entity COREAPB

# -- Compiling architecture DEF_ARCH of COREAPB

# -- Loading entity COReAPB_l

# -- Compiling entity COREAHBLITE_SLAVEARBITER_0

# -- Compiling architecture DEF_ARCH of COREAHBLITE_SLAVEARBITER_0

# -- Compiling entity COREAHBLITE_SLAVESTAGE_16

# -- Compiling architecture DEF_ARCH of COREAHBLITE_SLAVESTAGE_16

# -- Loading entity COREAHBLITE_SLAVEARBITER_0

# -- Compiling entity COREAHBLITE_DEFAULTSLAVESM_0

# -- Compiling architecture DEF_ARCH of COREAHBLITE_DEFAULTSLAVESM_0

# -- Compiling entity COREAHBLITE_MASTERSTAGE_1_1_0_1_0

# -- Compiling architecture DEF_ARCH of COREAHBLITE_MASTERSTAGE_1_1_0_1_0

# -- Loading entity COREAHBLITE_DEFAULTSLAVESM_0

# -- Compiling entity COREAHBLITE_MATRIX4X16

# -- Compiling architecture DEF_ARCH of COREAHBLITE_MATRIX4X16

# -- Loading entity COREAHBLITE_SLAVESTAGE_16

# -- Loading entity COREAHBLITE_MASTERSTAGE_1_1_0_1_0

# -- Compiling entity top_CoreAHBLite_0_CoreAHBLite

# -- Compiling architecture DEF_ARCH of top_CoreAHBLite_0_CoreAHBLite

# -- Loading entity COREAHBLITE_MATRIX4X16

# -- Compiling entity top_CoreUARTapb_0_Tx_async

# -- Compiling architecture DEF_ARCH of top_CoreUARTapb_0_Tx_async

# -- Compiling entity top_CoreUARTapb_0_Clock_gen

# -- Compiling architecture DEF_ARCH of top_CoreUARTapb_0_Clock_gen

# -- Compiling entity top_CoreUARTapb_0_Rx_async

# -- Compiling architecture DEF_ARCH of top_CoreUARTapb_0_Rx_async

# -- Compiling entity top_CoreUARTapb_0_COREUART

# -- Compiling architecture DEF_ARCH of top_CoreUARTapb_0_COREUART

# -- Loading entity top_CoreUARTapb_0_Tx_async

# -- Loading entity top_CoreUARTapb_0_Clock_gen

# -- Loading entity top_CoreUARTapb_0_Rx_async

# -- Compiling entity top_CoreUARTapb_0_CoreUARTapb

# -- Compiling architecture DEF_ARCH of top_CoreUARTapb_0_CoreUARTapb

# -- Loading entity top_CoreUARTapb_0_COREUART

# -- Compiling entity CoreAHB2APB

# -- Compiling architecture DEF_ARCH of CoreAHB2APB

# -- Compiling entity top

# -- Compiling architecture DEF_ARCH of top

# -- Loading entity AHBMASTER_FIC

# -- Loading entity COREAPB

# -- Loading entity top_CoreAHBLite_0_CoreAHBLite

# -- Loading entity top_CoreUARTapb_0_CoreUARTapb

# -- Loading entity CoreAHB2APB

# End time: 22:54:14 on Jun 02,2018, Elapsed time: 0:00:00

# Errors: 0, Warnings: 0

# Model Technology ModelSim Microsemi vcom 10.5c Compiler 2016.07 Jul 21 2016

# Start time: 22:54:14 on Jun 02,2018

# vcom -reportprogress 300 -2008 -explicit -work postsynth C:/Actelprj/test79_AHBmaster/stimulus/tb_clk.vhd

# -- Loading package STANDARD

# -- Loading package TEXTIO

# -- Loading package std_logic_1164

# -- Compiling entity tb_clk

# -- Compiling architecture RTL of tb_clk

# End time: 22:54:14 on Jun 02,2018, Elapsed time: 0:00:00

# Errors: 0, Warnings: 0

# Model Technology ModelSim Microsemi vcom 10.5c Compiler 2016.07 Jul 21 2016

# Start time: 22:54:14 on Jun 02,2018

# vcom -reportprogress 300 -2008 -explicit -work postsynth C:/Actelprj/test79_AHBmaster/component/work/tb_top/tb_top.vhd

# -- Loading package STANDARD

# -- Loading package TEXTIO

# -- Loading package std_logic_1164

# -- Compiling entity tb_top

# -- Compiling architecture RTL of tb_top

# End time: 22:54:14 on Jun 02,2018, Elapsed time: 0:00:00

# Errors: 0, Warnings: 0

# vsim -L proasic3 -L postsynth -L COREAHBLITE_LIB -L COREUARTAPB_LIB -t 1ps postsynth.tb_top

# Start time: 22:54:15 on Jun 02,2018

# //  ModelSim Microsemi 10.5c Jul 21 2016

# //

# //  Copyright 1991-2016 Mentor Graphics Corporation

# //  All Rights Reserved.

# //

# //  ModelSim Microsemi and its associated documentation contain trade

# //  secrets and commercial or financial information that are the property of

# //  Mentor Graphics Corporation and are privileged, confidential,

# //  and exempt from disclosure under the Freedom of Information Act,

# //  5 U.S.C. Section 552. Furthermore, this information

# //  is prohibited from disclosure under the Trade Secrets Act,

# //  18 U.S.C. Section 1905.

# //

# Loading std.standard

# Loading std.textio(body)

# Loading ieee.std_logic_1164(body)

# Loading postsynth.tb_top(rtl)

# Loading postsynth.tb_clk(rtl)

# Loading postsynth.top(def_arch)

# Loading ieee.vital_timing(body)

# Loading ieee.vital_primitives(body)

# Loading proasic3.vtables

# Loading proasic3.outbuf(vital_act)

# Loading postsynth.ahbmaster_fic(def_arch)

# Loading proasic3.dfn1e0(vital_act)

# Loading proasic3.dfn1c0(vital_act)

# Loading proasic3.dfn1e0c0(vital_act)

# Loading proasic3.dfn1e1c0(vital_act)

# Loading proasic3.ao1a(vital_act)

# Loading proasic3.nor2a(vital_act)

# Loading proasic3.ao1(vital_act)

# Loading proasic3.or2(vital_act)

# Loading proasic3.nor2b(vital_act)

# Loading proasic3.aoi1(vital_act)

# Loading proasic3.mx2c(vital_act)

# Loading proasic3.nor3a(vital_act)

# Loading proasic3.vcc(vital_act)

# Loading proasic3.or3c(vital_act)

# Loading proasic3.dfn1p0(vital_act)

# Loading proasic3.nor2(vital_act)

# Loading proasic3.or2a(vital_act)

# Loading proasic3.or3(vital_act)

# Loading proasic3.nor3b(vital_act)

# Loading proasic3.gnd(vital_act)

# Loading proasic3.nor3(vital_act)

# Loading proasic3.inbuf(vital_act)

# Loading postsynth.coreapb(def_arch)

# Loading postsynth.coreapb_l(def_arch)

# Loading proasic3.nor3c(vital_act)

# Loading proasic3.clkbuf(vital_act)

# Loading postsynth.top_coreahblite_0_coreahblite(def_arch)

# Loading postsynth.coreahblite_matrix4x16(def_arch)

# Loading postsynth.coreahblite_slavestage_16(def_arch)

# Loading postsynth.coreahblite_slavearbiter_0(def_arch)

# Loading proasic3.oa1c(vital_act)

# Loading proasic3.oa1a(vital_act)

# Loading proasic3.oa1(vital_act)

# Loading proasic3.ao1c(vital_act)

# Loading proasic3.ao1b(vital_act)

# Loading proasic3.aoi1b(vital_act)

# Loading proasic3.min3x(vital_act)

# Loading proasic3.mx2(vital_act)

# Loading proasic3.xa1(vital_act)

# Loading postsynth.coreahblite_masterstage_1_1_0_1_0(def_arch)

# Loading proasic3.xor2(vital_act)

# Loading proasic3.or2b(vital_act)

# Loading postsynth.coreahblite_defaultslavesm_0(def_arch)

# Loading postsynth.top_coreuartapb_0_coreuartapb(def_arch)

# Loading proasic3.mx2a(vital_act)

# Loading postsynth.top_coreuartapb_0_coreuart(def_arch)

# Loading proasic3.inv(vital_act)

# Loading postsynth.top_coreuartapb_0_tx_async(def_arch)

# Loading proasic3.dfn1e0p0(vital_act)

# Loading proasic3.axoi5(vital_act)

# Loading proasic3.mx2b(vital_act)

# Loading postsynth.top_coreuartapb_0_clock_gen(def_arch)

# Loading proasic3.ax1c(vital_act)

# Loading proasic3.xnor2(vital_act)

# Loading postsynth.top_coreuartapb_0_rx_async(def_arch)

# Loading proasic3.or3a(vital_act)

# Loading proasic3.xa1b(vital_act)

# Loading proasic3.oai1(vital_act)

# Loading proasic3.ao18(vital_act)

# Loading proasic3.axoi4(vital_act)

# Loading proasic3.ao1d(vital_act)

# Loading proasic3.dfn1e1p0(vital_act)

# Loading postsynth.coreahb2apb(def_arch)

run -all

run -all

# End time: 22:55:52 on Jun 02,2018, Elapsed time: 0:01:37

# Errors: 0, Warnings: 0