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-- Company: <Name>

--

-- File: tb_clk.vhd

-- File history:

--      <Revision number>: <Date>: <Comments>

--      <Revision number>: <Date>: <Comments>

--      <Revision number>: <Date>: <Comments>

--

-- Description: 

--

-- <Description here>

--

-- Targeted device: <Family::ProASIC3> <Die::A3PN250> <Package::100 VQFP>

-- Author: <Name>

--

--------------------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

entity tb_clk is

        port(

            -- Inputs

            HCLK    : out std_logic;

            HRSTn   : out std_logic

    );

end tb_clk;

architecture RTL of tb_clk is

    constant SYSCLK_PERIOD : time := 20.0 ns; -- 50MHZ

    signal gclk : std_logic := '1';

begin

    process

        variable vhdl_initial : BOOLEAN := TRUE;

    begin

        if ( vhdl_initial ) then

            -- Assert Reset

            --HCLK    <= '1';

            HRSTn   <= '0';

            wait for ( SYSCLK_PERIOD * 50 );

            HRSTn <= '1';

            wait;

        end if;

    end process;

    gclk <= not gclk after (SYSCLK_PERIOD / 2.0 );

    HCLK <= gclk;

   -- architecture body

end RTL;