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#Build: Synplify Pro L-2016.09M-2, Build 065R, Nov 16 2016
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#install: C:\Microsemi\Libero_SoC_v11.8\SynplifyPro
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#OS: Windows 8 6.2
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#Hostname: H81I
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# Sat Jun 02 22:49:56 2018
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#Implementation: synthesis
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Synopsys HDL Compiler, version comp2016q3p1, Build 117R, built Nov 17 2016
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@N|Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Synopsys VHDL Compiler, version comp2016q3p1, Build 127R, built Nov 24 2016
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@N|Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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@N: CD720 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vhd2008\std.vhd":146:18:146:21|Setting time resolution to ps
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@N:"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":32:7:32:19|Top entity is set to AHBMASTER_FIC.
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VHDL syntax check successful!
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@N: CD231 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vhd2008\std1164.vhd":890:16:890:17|Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000".
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@N: CD630 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":32:7:32:19|Synthesizing work.ahbmaster_fic.rtl.
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@W: CD274 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":118:3:118:6|Incomplete case statement - add more cases or a when others
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Post processing for work.ahbmaster_fic.rtl
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@A: CL282 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Feedback mux created for signal HADDR_int[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
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@A: CL282 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Feedback mux created for signal HWDATA_int[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
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@W: CL190 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Optimizing register bit HTRANS(0) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: CL260 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Pruning register bit 0 of HTRANS(1 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
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@N: CL201 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Trying to extract state machine for register ahb_fsm_current_state.
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Extracted state machine for register ahb_fsm_current_state
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State machine has 7 reachable states with original encodings of:
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000
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001
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010
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011
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100
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101
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110
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At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Sat Jun 02 22:49:57 2018
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###########################################################]
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Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016
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@N|Running in 64-bit mode
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@N: NF107 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":32:7:32:19|Selected library: work cell: AHBMASTER_FIC view rtl as top level
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@N: NF107 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":32:7:32:19|Selected library: work cell: AHBMASTER_FIC view rtl as top level
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Sat Jun 02 22:49:57 2018
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###########################################################]
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@END
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At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Sat Jun 02 22:49:57 2018
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###########################################################]
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Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016
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@N|Running in 64-bit mode
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@N: NF107 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":32:7:32:19|Selected library: work cell: AHBMASTER_FIC view rtl as top level
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@N: NF107 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":32:7:32:19|Selected library: work cell: AHBMASTER_FIC view rtl as top level
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Sat Jun 02 22:49:59 2018
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###########################################################]
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Pre-mapping Report
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# Sat Jun 02 22:49:59 2018
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Synopsys Microsemi Technology Pre-mapping, Version mapact, Build 1920R, Built Nov 17 2016 09:40:34
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Product Version L-2016.09M-2
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
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@A: MF827 |No constraint file specified.
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@L: C:\Actelprj\test79_AHBmaster\synthesis\AHBMASTER_FIC_scck.rpt
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Printing clock summary report in "C:\Actelprj\test79_AHBmaster\synthesis\AHBMASTER_FIC_scck.rpt" file
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@N: MF248 |Running in 64-bit mode.
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@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
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Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB)
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Clock Summary
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*****************
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Start Requested Requested Clock Clock Clock
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Clock Frequency Period Type Group Load
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---------------------------------------------------------------------------------------------
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AHBMASTER_FIC|HCLK 100.0 MHz 10.000 inferred Inferred_clkgroup_0 173
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=============================================================================================
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@W: MT530 :"c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd":106:2:106:3|Found inferred clock AHBMASTER_FIC|HCLK which controls 173 sequential elements including HADDR[31:0]. This clock has no specified timing constraint which may adversely impact design performance.
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Finished Pre Mapping Phase.
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@N: BN225 |Writing default property annotation file C:\Actelprj\test79_AHBmaster\synthesis\AHBMASTER_FIC.sap.
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Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB)
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Encoding state machine ahb_fsm_current_state[0:6] (in view: work.AHBMASTER_FIC(rtl))
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original code -> new code
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000 -> 0000001
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001 -> 0000010
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010 -> 0000100
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011 -> 0001000
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100 -> 0010000
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101 -> 0100000
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110 -> 1000000
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None
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None
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Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB)
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Pre-mapping successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 109MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Sat Jun 02 22:49:59 2018
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###########################################################]
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Map & Optimize Report
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# Sat Jun 02 22:50:00 2018
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Synopsys Microsemi Technology Mapper, Version mapact, Build 1920R, Built Nov 17 2016 09:40:34
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Product Version L-2016.09M-2
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
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@N: MF248 |Running in 64-bit mode.
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@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB)
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Available hyper_sources - for debug and ip models
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None Found
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Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB)
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Encoding state machine ahb_fsm_current_state[0:6] (in view: work.AHBMASTER_FIC(rtl))
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original code -> new code
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000 -> 0000001
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001 -> 0000010
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010 -> 0000100
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011 -> 0001000
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100 -> 0010000
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101 -> 0100000
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110 -> 1000000
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@W: MO160 :"c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd":106:2:106:3|Register bit HSIZE[2] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
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@W: MO161 :"c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd":106:2:106:3|Register bit HSIZE[1] (in view view:work.AHBMASTER_FIC(rtl)) is always 1. To keep the instance, apply syn_preserve=1 on the instance.
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@W: MO160 :"c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd":106:2:106:3|Register bit HSIZE[0] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
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Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB)
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Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)
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Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB)
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Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)
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Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)
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Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)
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Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)
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Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)
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Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
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High Fanout Net Report
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**********************
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Driver Instance / Pin Name Fanout, notes
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-----------------------------------------------------------------------
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un1_HWDATA_0_sqmuxa_0 / Y 32
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HADDR_int_0_sqmuxa / Y 32
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HWDATA_int_0_sqmuxa_1 / Y 32
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| 225 |
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DATAOUT_0_sqmuxa_i / Y 32
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| 226 |
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un1_ahb_fsm_current_state_12_i / Y 32
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| 227 |
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HWDATA_1_sqmuxa_0_a4 / Y 33
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| 228 |
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v2v_pr_0.HADDR_7_sn_i0_i_i / Y 33
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| 229 |
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HRESETn_pad / Y 108 : 106 asynchronous set/reset
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| 230 |
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=======================================================================
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| 231 |
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@N: FP130 |Promoting Net HRESETn_c on CLKBUF HRESETn_pad
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| 233 |
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@N: FP130 |Promoting Net HCLK_c on CLKBUF HCLK_pad
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| 234 |
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Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
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| 236 |
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Replicating Combinational Instance v2v_pr_0.HADDR_7_sn_i0_i_i, fanout 33 segments 2
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Replicating Combinational Instance HWDATA_1_sqmuxa_0_a4, fanout 34 segments 2
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| 239 |
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Replicating Combinational Instance un1_ahb_fsm_current_state_12_i, fanout 32 segments 2
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| 240 |
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Replicating Combinational Instance DATAOUT_0_sqmuxa_i, fanout 32 segments 2
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| 241 |
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Replicating Combinational Instance HWDATA_int_0_sqmuxa_1, fanout 32 segments 2
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| 242 |
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Replicating Combinational Instance HADDR_int_0_sqmuxa, fanout 32 segments 2
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| 243 |
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Replicating Combinational Instance un1_HWDATA_0_sqmuxa_0, fanout 32 segments 2
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| 244 |
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Added 0 Buffers
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Added 7 Cells via replication
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Added 0 Sequential Cells via replication
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| 248 |
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Added 7 Combinational Cells via replication
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| 249 |
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Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
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@S |Clock Optimization Summary
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#### START OF CLOCK OPTIMIZATION REPORT #####[
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| 259 |
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Clock optimization not enabled
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1 non-gated/non-generated clock tree(s) driving 170 clock pin(s) of sequential element(s)
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| 262 |
|
|
|
| 263 |
|
|
|
| 264 |
|
|
=========================== Non-Gated/Non-Generated Clocks ============================
|
| 265 |
|
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
| 266 |
|
|
---------------------------------------------------------------------------------------
|
| 267 |
|
|
@K:CKID0001 HCLK port 170 HADDR[0]
|
| 268 |
|
|
=======================================================================================
|
| 269 |
|
|
|
| 270 |
|
|
|
| 271 |
|
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
| 272 |
|
|
|
| 273 |
|
|
|
| 274 |
|
|
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 110MB)
|
| 275 |
|
|
|
| 276 |
|
|
Writing Analyst data base C:\Actelprj\test79_AHBmaster\synthesis\synwork\AHBMASTER_FIC_m.srm
|
| 277 |
|
|
|
| 278 |
|
|
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
|
| 279 |
|
|
|
| 280 |
|
|
Writing EDIF Netlist and constraint files
|
| 281 |
|
|
L-2016.09M-2
|
| 282 |
|
|
|
| 283 |
|
|
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
|
| 284 |
|
|
|
| 285 |
|
|
|
| 286 |
|
|
Start final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
|
| 287 |
|
|
|
| 288 |
|
|
@W: MT420 |Found inferred clock AHBMASTER_FIC|HCLK with period 10.00ns. Please declare a user-defined clock on object "p:HCLK"
|
| 289 |
|
|
|
| 290 |
|
|
|
| 291 |
|
|
##### START OF TIMING REPORT #####[
|
| 292 |
|
|
# Timing Report written on Sat Jun 02 22:50:00 2018
|
| 293 |
|
|
#
|
| 294 |
|
|
|
| 295 |
|
|
|
| 296 |
|
|
Top view: AHBMASTER_FIC
|
| 297 |
|
|
Library name: PA3
|
| 298 |
|
|
Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
|
| 299 |
|
|
Requested Frequency: 100.0 MHz
|
| 300 |
|
|
Wire load mode: top
|
| 301 |
|
|
Wire load model: proasic3
|
| 302 |
|
|
Paths requested: 5
|
| 303 |
|
|
Constraint File(s):
|
| 304 |
|
|
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
|
| 305 |
|
|
|
| 306 |
|
|
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
|
| 307 |
|
|
|
| 308 |
|
|
|
| 309 |
|
|
|
| 310 |
|
|
Performance Summary
|
| 311 |
|
|
*******************
|
| 312 |
|
|
|
| 313 |
|
|
|
| 314 |
|
|
Worst slack in design: 0.679
|
| 315 |
|
|
|
| 316 |
|
|
Requested Estimated Requested Estimated Clock Clock
|
| 317 |
|
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
| 318 |
|
|
-------------------------------------------------------------------------------------------------------------------------
|
| 319 |
|
|
AHBMASTER_FIC|HCLK 100.0 MHz 107.3 MHz 10.000 9.321 0.679 inferred Inferred_clkgroup_0
|
| 320 |
|
|
=========================================================================================================================
|
| 321 |
|
|
|
| 322 |
|
|
|
| 323 |
|
|
|
| 324 |
|
|
|
| 325 |
|
|
|
| 326 |
|
|
Clock Relationships
|
| 327 |
|
|
*******************
|
| 328 |
|
|
|
| 329 |
|
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
| 330 |
|
|
------------------------------------------------------------------------------------------------------------------------------
|
| 331 |
|
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
| 332 |
|
|
------------------------------------------------------------------------------------------------------------------------------
|
| 333 |
|
|
AHBMASTER_FIC|HCLK AHBMASTER_FIC|HCLK | 10.000 0.679 | No paths - | No paths - | No paths -
|
| 334 |
|
|
==============================================================================================================================
|
| 335 |
|
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
| 336 |
|
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
| 337 |
|
|
|
| 338 |
|
|
|
| 339 |
|
|
|
| 340 |
|
|
Interface Information
|
| 341 |
|
|
*********************
|
| 342 |
|
|
|
| 343 |
|
|
No IO constraint found
|
| 344 |
|
|
|
| 345 |
|
|
|
| 346 |
|
|
|
| 347 |
|
|
====================================
|
| 348 |
|
|
Detailed Report for Clock: AHBMASTER_FIC|HCLK
|
| 349 |
|
|
====================================
|
| 350 |
|
|
|
| 351 |
|
|
|
| 352 |
|
|
|
| 353 |
|
|
Starting Points with Worst Slack
|
| 354 |
|
|
********************************
|
| 355 |
|
|
|
| 356 |
|
|
Starting Arrival
|
| 357 |
|
|
Instance Reference Type Pin Net Time Slack
|
| 358 |
|
|
Clock
|
| 359 |
|
|
---------------------------------------------------------------------------------------------------------------------
|
| 360 |
|
|
ahb_fsm_current_state[4] AHBMASTER_FIC|HCLK DFN1C0 Q ahb_fsm_current_state[4] 0.737 0.679
|
| 361 |
|
|
ahb_fsm_current_state[1] AHBMASTER_FIC|HCLK DFN1C0 Q ahb_fsm_current_state[1] 0.737 1.401
|
| 362 |
|
|
ahb_fsm_current_state[6] AHBMASTER_FIC|HCLK DFN1P0 Q ahb_fsm_current_state[6] 0.737 1.795
|
| 363 |
|
|
ahb_fsm_current_state[2] AHBMASTER_FIC|HCLK DFN1C0 Q ahb_fsm_current_state[2] 0.737 3.104
|
| 364 |
|
|
ahb_fsm_current_state[5] AHBMASTER_FIC|HCLK DFN1C0 Q ahb_fsm_current_state[5] 0.737 3.243
|
| 365 |
|
|
ahb_fsm_current_state[0] AHBMASTER_FIC|HCLK DFN1C0 Q ahb_fsm_current_state[0] 0.737 3.551
|
| 366 |
|
|
ahb_fsm_current_state[3] AHBMASTER_FIC|HCLK DFN1C0 Q ahb_fsm_current_state[3] 0.737 3.658
|
| 367 |
|
|
HADDR_int[0] AHBMASTER_FIC|HCLK DFN1E1 Q HADDR_int[0] 0.737 6.526
|
| 368 |
|
|
HADDR_int[1] AHBMASTER_FIC|HCLK DFN1E1 Q HADDR_int[1] 0.737 6.526
|
| 369 |
|
|
HADDR_int[2] AHBMASTER_FIC|HCLK DFN1E1 Q HADDR_int[2] 0.737 6.526
|
| 370 |
|
|
=====================================================================================================================
|
| 371 |
|
|
|
| 372 |
|
|
|
| 373 |
|
|
Ending Points with Worst Slack
|
| 374 |
|
|
******************************
|
| 375 |
|
|
|
| 376 |
|
|
Starting Required
|
| 377 |
|
|
Instance Reference Type Pin Net Time Slack
|
| 378 |
|
|
Clock
|
| 379 |
|
|
------------------------------------------------------------------------------------------------------
|
| 380 |
|
|
HADDR[10] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[10] 9.461 0.679
|
| 381 |
|
|
HADDR[11] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[11] 9.461 0.679
|
| 382 |
|
|
HADDR[12] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[12] 9.461 0.679
|
| 383 |
|
|
HADDR[13] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[13] 9.461 0.679
|
| 384 |
|
|
HADDR[14] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[14] 9.461 0.679
|
| 385 |
|
|
HADDR[15] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[15] 9.461 0.679
|
| 386 |
|
|
HADDR[16] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[16] 9.461 0.679
|
| 387 |
|
|
HADDR[17] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[17] 9.461 0.679
|
| 388 |
|
|
HADDR[18] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[18] 9.461 0.679
|
| 389 |
|
|
HADDR[19] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[19] 9.461 0.679
|
| 390 |
|
|
======================================================================================================
|
| 391 |
|
|
|
| 392 |
|
|
|
| 393 |
|
|
|
| 394 |
|
|
Worst Path Information
|
| 395 |
|
|
***********************
|
| 396 |
|
|
|
| 397 |
|
|
|
| 398 |
|
|
Path information for path number 1:
|
| 399 |
|
|
Requested Period: 10.000
|
| 400 |
|
|
- Setup time: 0.539
|
| 401 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
| 402 |
|
|
= Required time: 9.461
|
| 403 |
|
|
|
| 404 |
|
|
- Propagation time: 8.782
|
| 405 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
| 406 |
|
|
= Slack (critical) : 0.679
|
| 407 |
|
|
|
| 408 |
|
|
Number of logic level(s): 3
|
| 409 |
|
|
Starting point: ahb_fsm_current_state[4] / Q
|
| 410 |
|
|
Ending point: HADDR[10] / D
|
| 411 |
|
|
The start point is clocked by AHBMASTER_FIC|HCLK [rising] on pin CLK
|
| 412 |
|
|
The end point is clocked by AHBMASTER_FIC|HCLK [rising] on pin CLK
|
| 413 |
|
|
|
| 414 |
|
|
Instance / Net Pin Pin Arrival No. of
|
| 415 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 416 |
|
|
---------------------------------------------------------------------------------------------------
|
| 417 |
|
|
ahb_fsm_current_state[4] DFN1C0 Q Out 0.737 0.737 -
|
| 418 |
|
|
ahb_fsm_current_state[4] Net - - 1.639 - 8
|
| 419 |
|
|
ahb_fsm_current_state_RNIFVDD[4] NOR2B A In - 2.376 -
|
| 420 |
|
|
ahb_fsm_current_state_RNIFVDD[4] NOR2B Y Out 0.514 2.890 -
|
| 421 |
|
|
HWDATA_1_sqmuxa_0 Net - - 2.218 - 17
|
| 422 |
|
|
v2v_pr_0\.HADDR_7_sn_i0_i_i_0 NOR2 B In - 5.108 -
|
| 423 |
|
|
v2v_pr_0\.HADDR_7_sn_i0_i_i_0 NOR2 Y Out 0.646 5.754 -
|
| 424 |
|
|
N_348_0 Net - - 2.218 - 17
|
| 425 |
|
|
v2v_pr_0\.HADDR_7[10] NOR2B A In - 7.972 -
|
| 426 |
|
|
v2v_pr_0\.HADDR_7[10] NOR2B Y Out 0.488 8.460 -
|
| 427 |
|
|
v2v_pr_0\.HADDR_7[10] Net - - 0.322 - 1
|
| 428 |
|
|
HADDR[10] DFN1E0C0 D In - 8.782 -
|
| 429 |
|
|
===================================================================================================
|
| 430 |
|
|
Total path delay (propagation time + setup) of 9.321 is 2.925(31.4%) logic and 6.396(68.6%) route.
|
| 431 |
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
| 432 |
|
|
|
| 433 |
|
|
|
| 434 |
|
|
|
| 435 |
|
|
##### END OF TIMING REPORT #####]
|
| 436 |
|
|
|
| 437 |
|
|
Timing exceptions that could not be applied
|
| 438 |
|
|
None
|
| 439 |
|
|
|
| 440 |
|
|
Finished final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
|
| 441 |
|
|
|
| 442 |
|
|
|
| 443 |
|
|
Finished timing report (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
|
| 444 |
|
|
|
| 445 |
|
|
--------------------------------------------------------------------------------
|
| 446 |
|
|
Target Part: A3PN250_VQFP100_STD
|
| 447 |
|
|
Report for cell AHBMASTER_FIC.rtl
|
| 448 |
|
|
Core Cell usage:
|
| 449 |
|
|
cell count area count*area
|
| 450 |
|
|
AO1A 6 1.0 6.0
|
| 451 |
|
|
GND 1 0.0 0.0
|
| 452 |
|
|
MX2 33 1.0 33.0
|
| 453 |
|
|
NOR2 3 1.0 3.0
|
| 454 |
|
|
NOR2A 1 1.0 1.0
|
| 455 |
|
|
NOR2B 36 1.0 36.0
|
| 456 |
|
|
NOR3 1 1.0 1.0
|
| 457 |
|
|
NOR3A 1 1.0 1.0
|
| 458 |
|
|
NOR3B 1 1.0 1.0
|
| 459 |
|
|
NOR3C 4 1.0 4.0
|
| 460 |
|
|
OA1B 1 1.0 1.0
|
| 461 |
|
|
OAI1 1 1.0 1.0
|
| 462 |
|
|
OR2 6 1.0 6.0
|
| 463 |
|
|
OR2B 2 1.0 2.0
|
| 464 |
|
|
OR3 2 1.0 2.0
|
| 465 |
|
|
VCC 1 0.0 0.0
|
| 466 |
|
|
|
| 467 |
|
|
|
| 468 |
|
|
DFN1C0 6 1.0 6.0
|
| 469 |
|
|
DFN1E0C0 67 1.0 67.0
|
| 470 |
|
|
DFN1E1 64 1.0 64.0
|
| 471 |
|
|
DFN1E1C0 32 1.0 32.0
|
| 472 |
|
|
DFN1P0 1 1.0 1.0
|
| 473 |
|
|
----- ----------
|
| 474 |
|
|
TOTAL 270 268.0
|
| 475 |
|
|
|
| 476 |
|
|
|
| 477 |
|
|
IO Cell usage:
|
| 478 |
|
|
cell count
|
| 479 |
|
|
CLKBUF 2
|
| 480 |
|
|
INBUF 101
|
| 481 |
|
|
OUTBUF 112
|
| 482 |
|
|
-----
|
| 483 |
|
|
TOTAL 215
|
| 484 |
|
|
|
| 485 |
|
|
|
| 486 |
|
|
Core Cells : 268 of 6144 (4%)
|
| 487 |
|
|
IO Cells : 215
|
| 488 |
|
|
|
| 489 |
|
|
RAM/ROM Usage Summary
|
| 490 |
|
|
Block Rams : 0 of 8 (0%)
|
| 491 |
|
|
|
| 492 |
|
|
Mapper successful!
|
| 493 |
|
|
|
| 494 |
|
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 24MB peak: 110MB)
|
| 495 |
|
|
|
| 496 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
| 497 |
|
|
# Sat Jun 02 22:50:01 2018
|
| 498 |
|
|
|
| 499 |
|
|
###########################################################]
|
