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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [synthesis/] [AHBMASTER_FIC_syn.prj] - Blame information for rev 3

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#--  Synopsys, Inc.
#--  Version L-2016.09M-2
#--  Project file C:\Actelprj\test79_AHBmaster\synthesis\AHBMASTER_FIC_syn.prj
#--  Written on Sat Jun 02 22:50:01 2018
 
 
#project files
add_file -vhdl -lib work "C:/Actelprj/test79_AHBmaster/hdl/AHBMASTER_FIC.vhd"
 
 
 
#implementation: "synthesis"
impl -add synthesis -type fpga
 
#device options
set_option -technology ProASIC3
set_option -part A3PN250
set_option -package VQFP100
set_option -speed_grade STD
set_option -part_companion ""
 
#compilation/mapping options
set_option -use_fsm_explorer 0
 
# hdl_compiler_options
set_option -distributed_compile 0
 
# mapper_without_write_options
set_option -frequency 100.000
set_option -srs_instrumentation 1
 
# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0
 
# actel_options
set_option -rw_check_on_ram 0
 
# Microsemi 500K
set_option -run_prop_extract 1
set_option -maxfan 24
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 4000
set_option -opcond COMWC
set_option -update_models_cp 0
set_option -preserve_registers 0
 
# Microsemi 500K
set_option -globalthreshold 50
 
# NFilter
set_option -no_sequential_opt 0
 
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
 
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
 
# Compiler Options
set_option -auto_infer_blackbox 0
 
# Compiler Options
set_option -vhdl2008 1
 
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
 
#set result format/file last
project -result_file "./AHBMASTER_FIC.edn"
impl -active "synthesis"

Line No.	Rev	Author	Line
1	3	uson	`#-- Synopsys, Inc.`
2			`#-- Version L-2016.09M-2`
3			`#-- Project file C:\Actelprj\test79_AHBmaster\synthesis\AHBMASTER_FIC_syn.prj`
4			`#-- Written on Sat Jun 02 22:50:01 2018`
5
6
7			`#project files`
8			`add_file -vhdl -lib work "C:/Actelprj/test79_AHBmaster/hdl/AHBMASTER_FIC.vhd"`
9
10
11
12			`#implementation: "synthesis"`
13			`impl -add synthesis -type fpga`
14
15			`#device options`
16			`set_option -technology ProASIC3`
17			`set_option -part A3PN250`
18			`set_option -package VQFP100`
19			`set_option -speed_grade STD`
20			`set_option -part_companion ""`
21
22			`#compilation/mapping options`
23			`set_option -use_fsm_explorer 0`
24
25			`# hdl_compiler_options`
26			`set_option -distributed_compile 0`
27
28			`# mapper_without_write_options`
29			`set_option -frequency 100.000`
30			`set_option -srs_instrumentation 1`
31
32			`# mapper_options`
33			`set_option -write_verilog 0`
34			`set_option -write_vhdl 0`
35
36			`# actel_options`
37			`set_option -rw_check_on_ram 0`
38
39			`# Microsemi 500K`
40			`set_option -run_prop_extract 1`
41			`set_option -maxfan 24`
42			`set_option -disable_io_insertion 0`
43			`set_option -retiming 0`
44			`set_option -report_path 4000`
45			`set_option -opcond COMWC`
46			`set_option -update_models_cp 0`
47			`set_option -preserve_registers 0`
48
49			`# Microsemi 500K`
50			`set_option -globalthreshold 50`
51
52			`# NFilter`
53			`set_option -no_sequential_opt 0`
54
55			`# sequential_optimization_options`
56			`set_option -symbolic_fsm_compiler 1`
57
58			`# Compiler Options`
59			`set_option -compiler_compatible 0`
60			`set_option -resource_sharing 1`
61
62			`# Compiler Options`
63			`set_option -auto_infer_blackbox 0`
64
65			`# Compiler Options`
66			`set_option -vhdl2008 1`
67
68			`#automatic place and route (vendor) options`
69			`set_option -write_apr_constraint 1`
70
71			`#set result format/file last`
72			`project -result_file "./AHBMASTER_FIC.edn"`
73			`impl -active "synthesis"`

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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [synthesis/] [AHBMASTER_FIC_syn.prj] - Blame information for rev 3