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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [synthesis/] [synlog/] [AHBMASTER_FIC_fpga_mapper.srr] - Blame information for rev 3

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# Sat Jun 02 22:50:00 2018
 
Synopsys Microsemi Technology Mapper, Version mapact, Build 1920R, Built Nov 17 2016 09:40:34
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09M-2
 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
 
 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
 
 
 
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB)
 
 
Available hyper_sources - for debug and ip models
        None Found
 
 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB)
 
Encoding state machine ahb_fsm_current_state[0:6] (in view: work.AHBMASTER_FIC(rtl))
original code -> new code
   000 -> 0000001
   001 -> 0000010
   010 -> 0000100
   011 -> 0001000
   100 -> 0010000
   101 -> 0100000
   110 -> 1000000
@W: MO160 :"c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd":106:2:106:3|Register bit HSIZE[2] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO161 :"c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd":106:2:106:3|Register bit HSIZE[1] (in view view:work.AHBMASTER_FIC(rtl)) is always 1. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd":106:2:106:3|Register bit HSIZE[0] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB)
 
 
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)
 
 
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB)
 
 
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)
 
 
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)
 
 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)
 
 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)
 
 
Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)
 
 
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
 
 
High Fanout Net Report
**********************
 
Driver Instance / Pin Name             Fanout, notes
-----------------------------------------------------------------------
un1_HWDATA_0_sqmuxa_0 / Y              32
HADDR_int_0_sqmuxa / Y                 32
HWDATA_int_0_sqmuxa_1 / Y              32
DATAOUT_0_sqmuxa_i / Y                 32
un1_ahb_fsm_current_state_12_i / Y     32
HWDATA_1_sqmuxa_0_a4 / Y               33
v2v_pr_0.HADDR_7_sn_i0_i_i / Y         33
HRESETn_pad / Y                        108 : 106 asynchronous set/reset
=======================================================================
 
@N: FP130 |Promoting Net HRESETn_c on CLKBUF  HRESETn_pad
@N: FP130 |Promoting Net HCLK_c on CLKBUF  HCLK_pad
 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
 
Replicating Combinational Instance v2v_pr_0.HADDR_7_sn_i0_i_i, fanout 33 segments 2
Replicating Combinational Instance HWDATA_1_sqmuxa_0_a4, fanout 34 segments 2
Replicating Combinational Instance un1_ahb_fsm_current_state_12_i, fanout 32 segments 2
Replicating Combinational Instance DATAOUT_0_sqmuxa_i, fanout 32 segments 2
Replicating Combinational Instance HWDATA_int_0_sqmuxa_1, fanout 32 segments 2
Replicating Combinational Instance HADDR_int_0_sqmuxa, fanout 32 segments 2
Replicating Combinational Instance un1_HWDATA_0_sqmuxa_0, fanout 32 segments 2
 
Added 0 Buffers
Added 7 Cells via replication
        Added 0 Sequential Cells via replication
        Added 7 Combinational Cells via replication
 
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
 
 
 
@S |Clock Optimization Summary
 
 
#### START OF CLOCK OPTIMIZATION REPORT #####[
 
Clock optimization not enabled
1 non-gated/non-generated clock tree(s) driving 170 clock pin(s) of sequential element(s)
 
 
 
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@K:CKID0001       HCLK                port                   170        HADDR[0]
=======================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
 
 
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 110MB)
 
Writing Analyst data base C:\Actelprj\test79_AHBmaster\synthesis\synwork\AHBMASTER_FIC_m.srm
 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
 
Writing EDIF Netlist and constraint files
L-2016.09M-2
 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
 
 
Start final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
 
@W: MT420 |Found inferred clock AHBMASTER_FIC|HCLK with period 10.00ns. Please declare a user-defined clock on object "p:HCLK"
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Sat Jun 02 22:50:00 2018
#
 
 
Top view:               AHBMASTER_FIC
Library name:           PA3
Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        proasic3
Paths requested:        5
Constraint File(s):
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
 
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
 
 
 
Performance Summary
*******************
 
 
Worst slack in design: 0.679
 
                       Requested     Estimated     Requested     Estimated               Clock        Clock
Starting Clock         Frequency     Frequency     Period        Period        Slack     Type         Group
-------------------------------------------------------------------------------------------------------------------------
AHBMASTER_FIC|HCLK     100.0 MHz     107.3 MHz     10.000        9.321         0.679     inferred     Inferred_clkgroup_0
=========================================================================================================================
 
 
 
 
 
Clock Relationships
*******************
 
Clocks                                  |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
------------------------------------------------------------------------------------------------------------------------------
Starting            Ending              |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------
AHBMASTER_FIC|HCLK  AHBMASTER_FIC|HCLK  |  10.000      0.679  |  No paths    -      |  No paths    -      |  No paths    -
==============================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
 
 
Interface Information
*********************
 
No IO constraint found
 
 
 
====================================
Detailed Report for Clock: AHBMASTER_FIC|HCLK
====================================
 
 
 
Starting Points with Worst Slack
********************************
 
                             Starting                                                               Arrival
Instance                     Reference              Type       Pin     Net                          Time        Slack
                             Clock
---------------------------------------------------------------------------------------------------------------------
ahb_fsm_current_state[4]     AHBMASTER_FIC|HCLK     DFN1C0     Q       ahb_fsm_current_state[4]     0.737       0.679
ahb_fsm_current_state[1]     AHBMASTER_FIC|HCLK     DFN1C0     Q       ahb_fsm_current_state[1]     0.737       1.401
ahb_fsm_current_state[6]     AHBMASTER_FIC|HCLK     DFN1P0     Q       ahb_fsm_current_state[6]     0.737       1.795
ahb_fsm_current_state[2]     AHBMASTER_FIC|HCLK     DFN1C0     Q       ahb_fsm_current_state[2]     0.737       3.104
ahb_fsm_current_state[5]     AHBMASTER_FIC|HCLK     DFN1C0     Q       ahb_fsm_current_state[5]     0.737       3.243
ahb_fsm_current_state[0]     AHBMASTER_FIC|HCLK     DFN1C0     Q       ahb_fsm_current_state[0]     0.737       3.551
ahb_fsm_current_state[3]     AHBMASTER_FIC|HCLK     DFN1C0     Q       ahb_fsm_current_state[3]     0.737       3.658
HADDR_int[0]                 AHBMASTER_FIC|HCLK     DFN1E1     Q       HADDR_int[0]                 0.737       6.526
HADDR_int[1]                 AHBMASTER_FIC|HCLK     DFN1E1     Q       HADDR_int[1]                 0.737       6.526
HADDR_int[2]                 AHBMASTER_FIC|HCLK     DFN1E1     Q       HADDR_int[2]                 0.737       6.526
=====================================================================================================================
 
 
Ending Points with Worst Slack
******************************
 
              Starting                                                              Required
Instance      Reference              Type         Pin     Net                       Time         Slack
              Clock
------------------------------------------------------------------------------------------------------
HADDR[10]     AHBMASTER_FIC|HCLK     DFN1E0C0     D       v2v_pr_0\.HADDR_7[10]     9.461        0.679
HADDR[11]     AHBMASTER_FIC|HCLK     DFN1E0C0     D       v2v_pr_0\.HADDR_7[11]     9.461        0.679
HADDR[12]     AHBMASTER_FIC|HCLK     DFN1E0C0     D       v2v_pr_0\.HADDR_7[12]     9.461        0.679
HADDR[13]     AHBMASTER_FIC|HCLK     DFN1E0C0     D       v2v_pr_0\.HADDR_7[13]     9.461        0.679
HADDR[14]     AHBMASTER_FIC|HCLK     DFN1E0C0     D       v2v_pr_0\.HADDR_7[14]     9.461        0.679
HADDR[15]     AHBMASTER_FIC|HCLK     DFN1E0C0     D       v2v_pr_0\.HADDR_7[15]     9.461        0.679
HADDR[16]     AHBMASTER_FIC|HCLK     DFN1E0C0     D       v2v_pr_0\.HADDR_7[16]     9.461        0.679
HADDR[17]     AHBMASTER_FIC|HCLK     DFN1E0C0     D       v2v_pr_0\.HADDR_7[17]     9.461        0.679
HADDR[18]     AHBMASTER_FIC|HCLK     DFN1E0C0     D       v2v_pr_0\.HADDR_7[18]     9.461        0.679
HADDR[19]     AHBMASTER_FIC|HCLK     DFN1E0C0     D       v2v_pr_0\.HADDR_7[19]     9.461        0.679
======================================================================================================
 
 
 
Worst Path Information
***********************
 
 
Path information for path number 1:
      Requested Period:                      10.000
    - Setup time:                            0.539
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.461
 
    - Propagation time:                      8.782
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     0.679
 
    Number of logic level(s):                3
    Starting point:                          ahb_fsm_current_state[4] / Q
    Ending point:                            HADDR[10] / D
    The start point is clocked by            AHBMASTER_FIC|HCLK [rising] on pin CLK
    The end   point is clocked by            AHBMASTER_FIC|HCLK [rising] on pin CLK
 
Instance / Net                                    Pin      Pin               Arrival     No. of
Name                                 Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------
ahb_fsm_current_state[4]             DFN1C0       Q        Out     0.737     0.737       -
ahb_fsm_current_state[4]             Net          -        -       1.639     -           8
ahb_fsm_current_state_RNIFVDD[4]     NOR2B        A        In      -         2.376       -
ahb_fsm_current_state_RNIFVDD[4]     NOR2B        Y        Out     0.514     2.890       -
HWDATA_1_sqmuxa_0                    Net          -        -       2.218     -           17
v2v_pr_0\.HADDR_7_sn_i0_i_i_0        NOR2         B        In      -         5.108       -
v2v_pr_0\.HADDR_7_sn_i0_i_i_0        NOR2         Y        Out     0.646     5.754       -
N_348_0                              Net          -        -       2.218     -           17
v2v_pr_0\.HADDR_7[10]                NOR2B        A        In      -         7.972       -
v2v_pr_0\.HADDR_7[10]                NOR2B        Y        Out     0.488     8.460       -
v2v_pr_0\.HADDR_7[10]                Net          -        -       0.322     -           1
HADDR[10]                            DFN1E0C0     D        In      -         8.782       -
===================================================================================================
Total path delay (propagation time + setup) of 9.321 is 2.925(31.4%) logic and 6.396(68.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
 
 
 
##### END OF TIMING REPORT #####]
 
Timing exceptions that could not be applied
None
 
Finished final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
 
 
Finished timing report (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
 
--------------------------------------------------------------------------------
Target Part: A3PN250_VQFP100_STD
Report for cell AHBMASTER_FIC.rtl
  Core Cell usage:
              cell count     area count*area
              AO1A     6      1.0        6.0
               GND     1      0.0        0.0
               MX2    33      1.0       33.0
              NOR2     3      1.0        3.0
             NOR2A     1      1.0        1.0
             NOR2B    36      1.0       36.0
              NOR3     1      1.0        1.0
             NOR3A     1      1.0        1.0
             NOR3B     1      1.0        1.0
             NOR3C     4      1.0        4.0
              OA1B     1      1.0        1.0
              OAI1     1      1.0        1.0
               OR2     6      1.0        6.0
              OR2B     2      1.0        2.0
               OR3     2      1.0        2.0
               VCC     1      0.0        0.0
 
 
            DFN1C0     6      1.0        6.0
          DFN1E0C0    67      1.0       67.0
            DFN1E1    64      1.0       64.0
          DFN1E1C0    32      1.0       32.0
            DFN1P0     1      1.0        1.0
                   -----          ----------
             TOTAL   270               268.0
 
 
  IO Cell usage:
              cell count
            CLKBUF     2
             INBUF   101
            OUTBUF   112
                   -----
             TOTAL   215
 
 
Core Cells         : 268 of 6144 (4%)
IO Cells           : 215
 
  RAM/ROM Usage Summary
Block Rams : 0 of 8 (0%)
 
Mapper successful!
 
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 24MB peak: 110MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Jun 02 22:50:01 2018
 
###########################################################]

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Subversion Repositories ahbmaster

[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [synthesis/] [synlog/] [AHBMASTER_FIC_fpga_mapper.srr] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	uson	`# Sat Jun 02 22:50:00 2018`
2
3			`Synopsys Microsemi Technology Mapper, Version mapact, Build 1920R, Built Nov 17 2016 09:40:34`
4			`Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.`
5			`Product Version L-2016.09M-2`
6
7			`Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)`
8
9			`@N: MF248 \|Running in 64-bit mode.`
10			`@N: MF667 \|Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)`
11
12			`Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)`
13
14
15			`Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)`
16
17
18
19			`Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB)`
20
21
22			`Available hyper_sources - for debug and ip models`
23			`None Found`
24
25
26			`Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB)`
27
28			`Encoding state machine ahb_fsm_current_state[0:6] (in view: work.AHBMASTER_FIC(rtl))`
29			`original code -> new code`
30			`000 -> 0000001`
31			`001 -> 0000010`
32			`010 -> 0000100`
33			`011 -> 0001000`
34			`100 -> 0010000`
35			`101 -> 0100000`
36			`110 -> 1000000`
37			`@W: MO160 :"c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd":106:2:106:3\|Register bit HSIZE[2] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.`
38			`@W: MO161 :"c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd":106:2:106:3\|Register bit HSIZE[1] (in view view:work.AHBMASTER_FIC(rtl)) is always 1. To keep the instance, apply syn_preserve=1 on the instance.`
39			`@W: MO160 :"c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd":106:2:106:3\|Register bit HSIZE[0] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.`
40
41			`Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB)`
42
43
44			`Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)`
45
46
47			`Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB)`
48
49
50			`Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)`
51
52
53			`Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)`
54
55
56			`Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)`
57
58
59			`Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)`
60
61
62			`Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)`
63
64
65			`Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)`
66
67
68			`High Fanout Net Report`
69			`**********************`
70
71			`Driver Instance / Pin Name Fanout, notes`
72			`-----------------------------------------------------------------------`
73			`un1_HWDATA_0_sqmuxa_0 / Y 32`
74			`HADDR_int_0_sqmuxa / Y 32`
75			`HWDATA_int_0_sqmuxa_1 / Y 32`
76			`DATAOUT_0_sqmuxa_i / Y 32`
77			`un1_ahb_fsm_current_state_12_i / Y 32`
78			`HWDATA_1_sqmuxa_0_a4 / Y 33`
79			`v2v_pr_0.HADDR_7_sn_i0_i_i / Y 33`
80			`HRESETn_pad / Y 108 : 106 asynchronous set/reset`
81			`=======================================================================`
82
83			`@N: FP130 \|Promoting Net HRESETn_c on CLKBUF HRESETn_pad`
84			`@N: FP130 \|Promoting Net HCLK_c on CLKBUF HCLK_pad`
85
86			`Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)`
87
88			`Replicating Combinational Instance v2v_pr_0.HADDR_7_sn_i0_i_i, fanout 33 segments 2`
89			`Replicating Combinational Instance HWDATA_1_sqmuxa_0_a4, fanout 34 segments 2`
90			`Replicating Combinational Instance un1_ahb_fsm_current_state_12_i, fanout 32 segments 2`
91			`Replicating Combinational Instance DATAOUT_0_sqmuxa_i, fanout 32 segments 2`
92			`Replicating Combinational Instance HWDATA_int_0_sqmuxa_1, fanout 32 segments 2`
93			`Replicating Combinational Instance HADDR_int_0_sqmuxa, fanout 32 segments 2`
94			`Replicating Combinational Instance un1_HWDATA_0_sqmuxa_0, fanout 32 segments 2`
95
96			`Added 0 Buffers`
97			`Added 7 Cells via replication`
98			`Added 0 Sequential Cells via replication`
99			`Added 7 Combinational Cells via replication`
100
101			`Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)`
102
103
104
105			`@S \|Clock Optimization Summary`
106
107
108			`#### START OF CLOCK OPTIMIZATION REPORT #####[`
109
110			`Clock optimization not enabled`
111			`1 non-gated/non-generated clock tree(s) driving 170 clock pin(s) of sequential element(s)`
112
113
114
115			`=========================== Non-Gated/Non-Generated Clocks ============================`
116			`Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance`
117			`---------------------------------------------------------------------------------------`
118			`@K:CKID0001 HCLK port 170 HADDR[0]`
119			`=======================================================================================`
120
121
122			`##### END OF CLOCK OPTIMIZATION REPORT ######]`
123
124
125			`Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 110MB)`
126
127			`Writing Analyst data base C:\Actelprj\test79_AHBmaster\synthesis\synwork\AHBMASTER_FIC_m.srm`
128
129			`Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)`
130
131			`Writing EDIF Netlist and constraint files`
132			`L-2016.09M-2`
133
134			`Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)`
135
136
137			`Start final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)`
138
139			`@W: MT420 \|Found inferred clock AHBMASTER_FIC\|HCLK with period 10.00ns. Please declare a user-defined clock on object "p:HCLK"`
140
141
142			`##### START OF TIMING REPORT #####[`
143			`# Timing Report written on Sat Jun 02 22:50:00 2018`
144			`#`
145
146
147			`Top view: AHBMASTER_FIC`
148			`Library name: PA3`
149			`Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )`
150			`Requested Frequency: 100.0 MHz`
151			`Wire load mode: top`
152			`Wire load model: proasic3`
153			`Paths requested: 5`
154			`Constraint File(s):`
155			`@N: MT320 \|This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.`
156
157			`@N: MT322 \|Clock constraints include only register-to-register paths associated with each individual clock.`
158
159
160
161			`Performance Summary`
162			`*******************`
163
164
165			`Worst slack in design: 0.679`
166
167			`Requested Estimated Requested Estimated Clock Clock`
168			`Starting Clock Frequency Frequency Period Period Slack Type Group`
169			`-------------------------------------------------------------------------------------------------------------------------`
170			`AHBMASTER_FIC\|HCLK 100.0 MHz 107.3 MHz 10.000 9.321 0.679 inferred Inferred_clkgroup_0`
171			`=========================================================================================================================`
172
173
174
175
176
177			`Clock Relationships`
178			`*******************`
179
180			`Clocks \| rise to rise \| fall to fall \| rise to fall \| fall to rise`
181			`------------------------------------------------------------------------------------------------------------------------------`
182			`Starting Ending \| constraint slack \| constraint slack \| constraint slack \| constraint slack`
183			`------------------------------------------------------------------------------------------------------------------------------`
184			`AHBMASTER_FIC\|HCLK AHBMASTER_FIC\|HCLK \| 10.000 0.679 \| No paths - \| No paths - \| No paths -`
185			`==============================================================================================================================`
186			`Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.`
187			`'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.`
188
189
190
191			`Interface Information`
192			`*********************`
193
194			`No IO constraint found`
195
196
197
198			`====================================`
199			`Detailed Report for Clock: AHBMASTER_FIC\|HCLK`
200			`====================================`
201
202
203
204			`Starting Points with Worst Slack`
205			`********************************`
206
207			`Starting Arrival`
208			`Instance Reference Type Pin Net Time Slack`
209			`Clock`
210			`---------------------------------------------------------------------------------------------------------------------`
211			`ahb_fsm_current_state[4] AHBMASTER_FIC\|HCLK DFN1C0 Q ahb_fsm_current_state[4] 0.737 0.679`
212			`ahb_fsm_current_state[1] AHBMASTER_FIC\|HCLK DFN1C0 Q ahb_fsm_current_state[1] 0.737 1.401`
213			`ahb_fsm_current_state[6] AHBMASTER_FIC\|HCLK DFN1P0 Q ahb_fsm_current_state[6] 0.737 1.795`
214			`ahb_fsm_current_state[2] AHBMASTER_FIC\|HCLK DFN1C0 Q ahb_fsm_current_state[2] 0.737 3.104`
215			`ahb_fsm_current_state[5] AHBMASTER_FIC\|HCLK DFN1C0 Q ahb_fsm_current_state[5] 0.737 3.243`
216			`ahb_fsm_current_state[0] AHBMASTER_FIC\|HCLK DFN1C0 Q ahb_fsm_current_state[0] 0.737 3.551`
217			`ahb_fsm_current_state[3] AHBMASTER_FIC\|HCLK DFN1C0 Q ahb_fsm_current_state[3] 0.737 3.658`
218			`HADDR_int[0] AHBMASTER_FIC\|HCLK DFN1E1 Q HADDR_int[0] 0.737 6.526`
219			`HADDR_int[1] AHBMASTER_FIC\|HCLK DFN1E1 Q HADDR_int[1] 0.737 6.526`
220			`HADDR_int[2] AHBMASTER_FIC\|HCLK DFN1E1 Q HADDR_int[2] 0.737 6.526`
221			`=====================================================================================================================`
222
223
224			`Ending Points with Worst Slack`
225			`******************************`
226
227			`Starting Required`
228			`Instance Reference Type Pin Net Time Slack`
229			`Clock`
230			`------------------------------------------------------------------------------------------------------`
231			`HADDR[10] AHBMASTER_FIC\|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[10] 9.461 0.679`
232			`HADDR[11] AHBMASTER_FIC\|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[11] 9.461 0.679`
233			`HADDR[12] AHBMASTER_FIC\|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[12] 9.461 0.679`
234			`HADDR[13] AHBMASTER_FIC\|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[13] 9.461 0.679`
235			`HADDR[14] AHBMASTER_FIC\|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[14] 9.461 0.679`
236			`HADDR[15] AHBMASTER_FIC\|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[15] 9.461 0.679`
237			`HADDR[16] AHBMASTER_FIC\|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[16] 9.461 0.679`
238			`HADDR[17] AHBMASTER_FIC\|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[17] 9.461 0.679`
239			`HADDR[18] AHBMASTER_FIC\|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[18] 9.461 0.679`
240			`HADDR[19] AHBMASTER_FIC\|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[19] 9.461 0.679`
241			`======================================================================================================`
242
243
244
245			`Worst Path Information`
246			`***********************`
247
248
249			`Path information for path number 1:`
250			`Requested Period: 10.000`
251			`- Setup time: 0.539`
252			`+ Clock delay at ending point: 0.000 (ideal)`
253			`= Required time: 9.461`
254
255			`- Propagation time: 8.782`
256			`- Clock delay at starting point: 0.000 (ideal)`
257			`= Slack (critical) : 0.679`
258
259			`Number of logic level(s): 3`
260			`Starting point: ahb_fsm_current_state[4] / Q`
261			`Ending point: HADDR[10] / D`
262			`The start point is clocked by AHBMASTER_FIC\|HCLK [rising] on pin CLK`
263			`The end point is clocked by AHBMASTER_FIC\|HCLK [rising] on pin CLK`
264
265			`Instance / Net Pin Pin Arrival No. of`
266			`Name Type Name Dir Delay Time Fan Out(s)`
267			`---------------------------------------------------------------------------------------------------`
268			`ahb_fsm_current_state[4] DFN1C0 Q Out 0.737 0.737 -`
269			`ahb_fsm_current_state[4] Net - - 1.639 - 8`
270			`ahb_fsm_current_state_RNIFVDD[4] NOR2B A In - 2.376 -`
271			`ahb_fsm_current_state_RNIFVDD[4] NOR2B Y Out 0.514 2.890 -`
272			`HWDATA_1_sqmuxa_0 Net - - 2.218 - 17`
273			`v2v_pr_0\.HADDR_7_sn_i0_i_i_0 NOR2 B In - 5.108 -`
274			`v2v_pr_0\.HADDR_7_sn_i0_i_i_0 NOR2 Y Out 0.646 5.754 -`
275			`N_348_0 Net - - 2.218 - 17`
276			`v2v_pr_0\.HADDR_7[10] NOR2B A In - 7.972 -`
277			`v2v_pr_0\.HADDR_7[10] NOR2B Y Out 0.488 8.460 -`
278			`v2v_pr_0\.HADDR_7[10] Net - - 0.322 - 1`
279			`HADDR[10] DFN1E0C0 D In - 8.782 -`
280			`===================================================================================================`
281			`Total path delay (propagation time + setup) of 9.321 is 2.925(31.4%) logic and 6.396(68.6%) route.`
282			`Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value`
283
284
285
286			`##### END OF TIMING REPORT #####]`
287
288			`Timing exceptions that could not be applied`
289			`None`
290
291			`Finished final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)`
292
293
294			`Finished timing report (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)`
295
296			`--------------------------------------------------------------------------------`
297			`Target Part: A3PN250_VQFP100_STD`
298			`Report for cell AHBMASTER_FIC.rtl`
299			`Core Cell usage:`
300			`cell count area count*area`
301			`AO1A 6 1.0 6.0`
302			`GND 1 0.0 0.0`
303			`MX2 33 1.0 33.0`
304			`NOR2 3 1.0 3.0`
305			`NOR2A 1 1.0 1.0`
306			`NOR2B 36 1.0 36.0`
307			`NOR3 1 1.0 1.0`
308			`NOR3A 1 1.0 1.0`
309			`NOR3B 1 1.0 1.0`
310			`NOR3C 4 1.0 4.0`
311			`OA1B 1 1.0 1.0`
312			`OAI1 1 1.0 1.0`
313			`OR2 6 1.0 6.0`
314			`OR2B 2 1.0 2.0`
315			`OR3 2 1.0 2.0`
316			`VCC 1 0.0 0.0`
317
318
319			`DFN1C0 6 1.0 6.0`
320			`DFN1E0C0 67 1.0 67.0`
321			`DFN1E1 64 1.0 64.0`
322			`DFN1E1C0 32 1.0 32.0`
323			`DFN1P0 1 1.0 1.0`
324			`----- ----------`
325			`TOTAL 270 268.0`
326
327
328			`IO Cell usage:`
329			`cell count`
330			`CLKBUF 2`
331			`INBUF 101`
332			`OUTBUF 112`
333			`-----`
334			`TOTAL 215`
335
336
337			`Core Cells : 268 of 6144 (4%)`
338			`IO Cells : 215`
339
340			`RAM/ROM Usage Summary`
341			`Block Rams : 0 of 8 (0%)`
342
343			`Mapper successful!`
344
345			`At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 24MB peak: 110MB)`
346
347			`Process took 0h:00m:01s realtime, 0h:00m:01s cputime`
348			`# Sat Jun 02 22:50:01 2018`
349
350			`###########################################################]`