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# Sat Jun 02 22:49:59 2018
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Synopsys Microsemi Technology Pre-mapping, Version mapact, Build 1920R, Built Nov 17 2016 09:40:34
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Product Version L-2016.09M-2
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
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@A: MF827 |No constraint file specified.
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@L: C:\Actelprj\test79_AHBmaster\synthesis\AHBMASTER_FIC_scck.rpt
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Printing clock summary report in "C:\Actelprj\test79_AHBmaster\synthesis\AHBMASTER_FIC_scck.rpt" file
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@N: MF248 |Running in 64-bit mode.
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@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
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Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB)
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Clock Summary
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*****************
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Start Requested Requested Clock Clock Clock
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Clock Frequency Period Type Group Load
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---------------------------------------------------------------------------------------------
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AHBMASTER_FIC|HCLK 100.0 MHz 10.000 inferred Inferred_clkgroup_0 173
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=============================================================================================
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@W: MT530 :"c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd":106:2:106:3|Found inferred clock AHBMASTER_FIC|HCLK which controls 173 sequential elements including HADDR[31:0]. This clock has no specified timing constraint which may adversely impact design performance.
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Finished Pre Mapping Phase.
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@N: BN225 |Writing default property annotation file C:\Actelprj\test79_AHBmaster\synthesis\AHBMASTER_FIC.sap.
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Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB)
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Encoding state machine ahb_fsm_current_state[0:6] (in view: work.AHBMASTER_FIC(rtl))
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original code -> new code
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000 -> 0000001
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001 -> 0000010
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010 -> 0000100
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011 -> 0001000
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100 -> 0010000
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101 -> 0100000
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110 -> 1000000
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None
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None
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Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB)
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Pre-mapping successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 109MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Sat Jun 02 22:49:59 2018
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###########################################################]
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