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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [synthesis/] [synlog/] [report/] [top_fpga_mapper_combined_clk.rpt] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	uson
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3			`@S \|Clock Optimization Summary`
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6			`#### START OF CLOCK OPTIMIZATION REPORT #####[`
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8			`Clock optimization not enabled`
9			`1 non-gated/non-generated clock tree(s) driving 258 clock pin(s) of sequential element(s)`
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13			`================================ Non-Gated/Non-Generated Clocks ================================`
14			`Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance`
15			`------------------------------------------------------------------------------------------------`
16			`@K:CKID0001 HCLK port 258 CoreUARTapb_0.iPRDATA[7]`
17			`================================================================================================`
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20			`##### END OF CLOCK OPTIMIZATION REPORT ######]`
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