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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [synthesis/] [synlog/] [top_compiler.srr] - Blame information for rev 3

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1 3 uson
Synopsys HDL Compiler, version comp2016q3p1, Build 117R, built Nov 17 2016
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@N|Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Synopsys VHDL Compiler, version comp2016q3p1, Build 127R, built Nov 24 2016
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@N|Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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@N: CD720 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vhd2008\std.vhd":146:18:146:21|Setting time resolution to ps
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@N:"C:\Actelprj\test79_AHBmaster\component\work\top\top.vhd":23:7:23:9|Top entity is set to top.
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Options changed - recompiling
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VHDL syntax check successful!
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Options changed - recompiling
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@N: CD231 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vhd2008\std1164.vhd":890:16:890:17|Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000".
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@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\work\top\top.vhd":23:7:23:9|Synthesizing work.top.rtl.
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@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":62:7:62:35|Synthesizing coreuartapb_lib.top_coreuartapb_0_coreuartapb.translated.
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@N: CD364 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":305:16:305:26|Removing redundant assignment.
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@N: CD364 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":333:15:333:25|Removing redundant assignment.
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@W: CD638 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":153:10:153:20|Signal controlreg3 is undriven. Either assign the signal a value or remove the signal declaration.
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@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":34:7:34:32|Synthesizing coreuartapb_lib.top_coreuartapb_0_coreuart.translated.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":265:21:265:31|Signal rx_dout_reg in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":265:34:265:49|Signal parity_err_xhdl1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@N: CD604 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":392:9:392:22|OTHERS clause is not synthesized.
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@N: CD364 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":450:13:450:24|Removing redundant assignment.
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@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd":33:7:33:32|Synthesizing coreuartapb_lib.top_coreuartapb_0_rx_async.translated.
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@N: CD233 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd":64:24:64:25|Using sequential encoding for type receive_states.
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@N: CD364 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd":233:15:233:29|Removing redundant assignment.
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@N: CD604 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd":253:21:253:34|OTHERS clause is not synthesized.
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@N: CD364 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd":256:19:256:26|Removing redundant assignment.
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@N: CD604 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd":318:19:318:33|OTHERS clause is not synthesized.
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@N: CD604 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd":423:18:423:32|OTHERS clause is not synthesized.
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Post processing for coreuartapb_lib.top_coreuartapb_0_rx_async.translated
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@W: CL177 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd":443:6:443:7|Sharing sequential element clear_framing_error_en_i. Add a syn_preserve attribute to the element to prevent sharing.
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@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd":33:7:33:32|Synthesizing coreuartapb_lib.top_coreuartapb_0_tx_async.translated.
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@N: CD364 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd":311:12:311:20|Removing redundant assignment.
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Post processing for coreuartapb_lib.top_coreuartapb_0_tx_async.translated
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@W: CL190 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd":134:4:134:5|Optimizing register bit fifo_read_en0 to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd":134:4:134:5|Pruning unused register fifo_read_en0. Make sure that there are no unused intermediate registers.
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@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd":35:7:35:33|Synthesizing coreuartapb_lib.top_coreuartapb_0_clock_gen.rtl.
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@W: CD638 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd":54:7:54:19|Signal baud_cntr_one is undriven. Either assign the signal a value or remove the signal declaration.
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Post processing for coreuartapb_lib.top_coreuartapb_0_clock_gen.rtl
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Post processing for coreuartapb_lib.top_coreuartapb_0_coreuart.translated
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@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":439:7:439:8|Pruning unused register overflow_reg_3. Make sure that there are no unused intermediate registers.
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@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":414:7:414:8|Pruning unused register rx_dout_reg_empty_5. Make sure that there are no unused intermediate registers.
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@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":399:6:399:7|Pruning unused register rx_dout_reg_5(7 downto 0). Make sure that there are no unused intermediate registers.
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@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":367:6:367:7|Pruning unused register rx_state_4(1 downto 0). Make sure that there are no unused intermediate registers.
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@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":350:6:350:7|Pruning unused register clear_framing_error_reg0_3. Make sure that there are no unused intermediate registers.
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@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":350:6:350:7|Pruning unused register clear_framing_error_reg_3. Make sure that there are no unused intermediate registers.
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@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":333:6:333:7|Pruning unused register clear_parity_reg0_3. Make sure that there are no unused intermediate registers.
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@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":333:6:333:7|Pruning unused register clear_parity_reg_3. Make sure that there are no unused intermediate registers.
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@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":245:6:245:7|Pruning unused register fifo_write_tx_4. Make sure that there are no unused intermediate registers.
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Post processing for coreuartapb_lib.top_coreuartapb_0_coreuartapb.translated
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@W: CL252 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":153:10:153:20|Bit 0 of signal controlReg3 is floating -- simulation mismatch possible.
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@W: CL252 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":153:10:153:20|Bit 1 of signal controlReg3 is floating -- simulation mismatch possible.
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@W: CL252 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":153:10:153:20|Bit 2 of signal controlReg3 is floating -- simulation mismatch possible.
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@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":3:7:3:13|Synthesizing work.coreapb.coreapb_o.
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@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\MuxP2B.vhd":3:7:3:15|Synthesizing work.coreapb_l.coreapb_li0.
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@N: CD604 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\MuxP2B.vhd":144:0:144:13|OTHERS clause is not synthesized.
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Post processing for work.coreapb_l.coreapb_li0
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Post processing for work.coreapb.coreapb_o
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@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":27:7:27:35|Synthesizing coreahblite_lib.top_coreahblite_0_coreahblite.coreahblite_arch.
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@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":25:7:25:28|Synthesizing coreahblite_lib.coreahblite_matrix4x16.coreahblite_matrix4x16_arch.
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@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavestage.vhd":24:7:24:28|Synthesizing coreahblite_lib.coreahblite_slavestage.trans.
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@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd":22:7:22:30|Synthesizing coreahblite_lib.coreahblite_slavearbiter.coreahblite_slavearbiter_arch.
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@N: CD604 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd":391:12:391:25|OTHERS clause is not synthesized.
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Post processing for coreahblite_lib.coreahblite_slavearbiter.coreahblite_slavearbiter_arch
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Post processing for coreahblite_lib.coreahblite_slavestage.trans
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@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":24:7:24:29|Synthesizing coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":339:8:339:17|Signal sdataready in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":340:8:340:13|Signal shresp in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":341:8:341:16|Signal hrdata_s0 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":341:20:341:31|Signal hreadyout_s0 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":342:8:342:16|Signal hrdata_s1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":342:20:342:31|Signal hreadyout_s1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":343:8:343:16|Signal hrdata_s2 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":343:20:343:31|Signal hreadyout_s2 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":344:8:344:16|Signal hrdata_s3 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":344:20:344:31|Signal hreadyout_s3 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":345:8:345:16|Signal hrdata_s4 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":345:20:345:31|Signal hreadyout_s4 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":346:8:346:16|Signal hrdata_s5 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":346:20:346:31|Signal hreadyout_s5 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":347:8:347:16|Signal hrdata_s6 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
84
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":347:20:347:31|Signal hreadyout_s6 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":348:8:348:16|Signal hrdata_s7 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":348:20:348:31|Signal hreadyout_s7 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":349:8:349:16|Signal hrdata_s8 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
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@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":349:20:349:31|Signal hreadyout_s8 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
89
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":350:8:350:16|Signal hrdata_s9 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
90
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":350:20:350:31|Signal hreadyout_s9 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
91
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":351:8:351:17|Signal hrdata_s10 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
92
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":351:20:351:32|Signal hreadyout_s10 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
93
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":352:8:352:17|Signal hrdata_s11 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
94
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":352:20:352:32|Signal hreadyout_s11 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
95
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":353:8:353:17|Signal hrdata_s12 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
96
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":353:20:353:32|Signal hreadyout_s12 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
97
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":354:8:354:17|Signal hrdata_s13 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
98
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":354:20:354:32|Signal hreadyout_s13 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
99
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":355:8:355:17|Signal hrdata_s14 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
100
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":355:20:355:32|Signal hreadyout_s14 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
101
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":356:8:356:17|Signal hrdata_s15 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
102
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":356:20:356:32|Signal hreadyout_s15 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
103
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":357:8:357:17|Signal hrdata_s16 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
104
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":357:20:357:32|Signal hreadyout_s16 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
105
@N: CD604 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":637:12:637:25|OTHERS clause is not synthesized.
106
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_defaultslavesm.vhd":22:7:22:32|Synthesizing coreahblite_lib.coreahblite_defaultslavesm.coreahblite_defaultslavesm_arch.
107
@N: CD604 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_defaultslavesm.vhd":63:12:63:25|OTHERS clause is not synthesized.
108
Post processing for coreahblite_lib.coreahblite_defaultslavesm.coreahblite_defaultslavesm_arch
109
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_addrdec.vhd":50:7:50:25|Synthesizing coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch.
110
Post processing for coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch
111
Post processing for coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch
112
@W: CL177 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":644:8:644:9|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
113
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":24:7:24:29|Synthesizing coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch.
114
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":342:8:342:16|Signal hrdata_s1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
115
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":342:20:342:31|Signal hreadyout_s1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
116
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":343:8:343:16|Signal hrdata_s2 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
117
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":343:20:343:31|Signal hreadyout_s2 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
118
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":344:8:344:16|Signal hrdata_s3 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
119
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":344:20:344:31|Signal hreadyout_s3 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
120
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":345:8:345:16|Signal hrdata_s4 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
121
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":345:20:345:31|Signal hreadyout_s4 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
122
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":346:8:346:16|Signal hrdata_s5 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
123
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":346:20:346:31|Signal hreadyout_s5 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
124
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":347:8:347:16|Signal hrdata_s6 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
125
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":347:20:347:31|Signal hreadyout_s6 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
126
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":348:8:348:16|Signal hrdata_s7 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
127
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":348:20:348:31|Signal hreadyout_s7 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
128
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":349:8:349:16|Signal hrdata_s8 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
129
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":349:20:349:31|Signal hreadyout_s8 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
130
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":350:8:350:16|Signal hrdata_s9 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
131
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":350:20:350:31|Signal hreadyout_s9 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
132
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":351:8:351:17|Signal hrdata_s10 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
133
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":351:20:351:32|Signal hreadyout_s10 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
134
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":352:8:352:17|Signal hrdata_s11 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
135
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":352:20:352:32|Signal hreadyout_s11 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
136
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":353:8:353:17|Signal hrdata_s12 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
137
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":353:20:353:32|Signal hreadyout_s12 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
138
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":354:8:354:17|Signal hrdata_s13 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
139
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":354:20:354:32|Signal hreadyout_s13 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
140
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":355:8:355:17|Signal hrdata_s14 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
141
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":355:20:355:32|Signal hreadyout_s14 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
142
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":356:8:356:17|Signal hrdata_s15 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
143
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":356:20:356:32|Signal hreadyout_s15 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
144
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":357:8:357:17|Signal hrdata_s16 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
145
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":357:20:357:32|Signal hreadyout_s16 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
146
@N: CD604 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":637:12:637:25|OTHERS clause is not synthesized.
147
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_addrdec.vhd":50:7:50:25|Synthesizing coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch.
148
Post processing for coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch
149
Post processing for coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch
150
@W: CL177 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":644:8:644:9|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
151
Post processing for coreahblite_lib.coreahblite_matrix4x16.coreahblite_matrix4x16_arch
152
Post processing for coreahblite_lib.top_coreahblite_0_coreahblite.coreahblite_arch
153
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd":12:7:12:17|Synthesizing work.coreahb2apb.synth.
154
Post processing for work.coreahb2apb.synth
155
@N: CD630 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":32:7:32:19|Synthesizing work.ahbmaster_fic.rtl.
156
@W: CD274 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":118:3:118:6|Incomplete case statement - add more cases or a when others
157
Post processing for work.ahbmaster_fic.rtl
158
@A: CL282 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Feedback mux created for signal HADDR_int[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
159
@A: CL282 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Feedback mux created for signal HWDATA_int[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
160
@W: CL190 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Optimizing register bit HTRANS(0) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
161
@W: CL260 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Pruning register bit 0 of HTRANS(1 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
162
Post processing for work.top.rtl
163
@N: CL201 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Trying to extract state machine for register ahb_fsm_current_state.
164
Extracted state machine for register ahb_fsm_current_state
165
State machine has 7 reachable states with original encodings of:
166
   000
167
   001
168
   010
169
   011
170
   100
171
   101
172
   110
173
@N: CL201 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd":336:4:336:5|Trying to extract state machine for register CurrentState.
174
Extracted state machine for register CurrentState
175
State machine has 8 reachable states with original encodings of:
176
   0000
177
   0001
178
   0100
179
   1001
180
   1010
181
   1011
182
   1110
183
   1111
184
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd":20:4:20:9|Input port bit 0 of htrans(1 downto 0) is unused
185
@W: CL246 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":45:8:45:17|Input port bits 16 to 1 of sdataready(16 downto 0) are unused. Assign logic for all port bits or change the input port size.
186
@W: CL246 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":46:8:46:13|Input port bits 16 to 1 of shresp(16 downto 0) are unused. Assign logic for all port bits or change the input port size.
187
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":57:8:57:16|Input HRDATA_S1 is unused.
188
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":58:8:58:19|Input HREADYOUT_S1 is unused.
189
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":59:8:59:16|Input HRDATA_S2 is unused.
190
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":60:8:60:19|Input HREADYOUT_S2 is unused.
191
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":61:8:61:16|Input HRDATA_S3 is unused.
192
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":62:8:62:19|Input HREADYOUT_S3 is unused.
193
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":63:8:63:16|Input HRDATA_S4 is unused.
194
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":64:8:64:19|Input HREADYOUT_S4 is unused.
195
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":65:8:65:16|Input HRDATA_S5 is unused.
196
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":66:8:66:19|Input HREADYOUT_S5 is unused.
197
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":67:8:67:16|Input HRDATA_S6 is unused.
198
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":68:8:68:19|Input HREADYOUT_S6 is unused.
199
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":69:8:69:16|Input HRDATA_S7 is unused.
200
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":70:8:70:19|Input HREADYOUT_S7 is unused.
201
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":71:8:71:16|Input HRDATA_S8 is unused.
202
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":72:8:72:19|Input HREADYOUT_S8 is unused.
203
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":73:8:73:16|Input HRDATA_S9 is unused.
204
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":74:8:74:19|Input HREADYOUT_S9 is unused.
205
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":75:8:75:17|Input HRDATA_S10 is unused.
206
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":76:8:76:20|Input HREADYOUT_S10 is unused.
207
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":77:8:77:17|Input HRDATA_S11 is unused.
208
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":78:8:78:20|Input HREADYOUT_S11 is unused.
209
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":79:8:79:17|Input HRDATA_S12 is unused.
210
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":80:8:80:20|Input HREADYOUT_S12 is unused.
211
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":81:8:81:17|Input HRDATA_S13 is unused.
212
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":82:8:82:20|Input HREADYOUT_S13 is unused.
213
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":83:8:83:17|Input HRDATA_S14 is unused.
214
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":84:8:84:20|Input HREADYOUT_S14 is unused.
215
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":85:8:85:17|Input HRDATA_S15 is unused.
216
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":86:8:86:20|Input HREADYOUT_S15 is unused.
217
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":87:8:87:17|Input HRDATA_S16 is unused.
218
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":88:8:88:20|Input HREADYOUT_S16 is unused.
219
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":45:8:45:17|Input SDATAREADY is unused.
220
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":46:8:46:13|Input SHRESP is unused.
221
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":55:8:55:16|Input HRDATA_S0 is unused.
222
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":56:8:56:19|Input HREADYOUT_S0 is unused.
223
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":57:8:57:16|Input HRDATA_S1 is unused.
224
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":58:8:58:19|Input HREADYOUT_S1 is unused.
225
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":59:8:59:16|Input HRDATA_S2 is unused.
226
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":60:8:60:19|Input HREADYOUT_S2 is unused.
227
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":61:8:61:16|Input HRDATA_S3 is unused.
228
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":62:8:62:19|Input HREADYOUT_S3 is unused.
229
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":63:8:63:16|Input HRDATA_S4 is unused.
230
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":64:8:64:19|Input HREADYOUT_S4 is unused.
231
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":65:8:65:16|Input HRDATA_S5 is unused.
232
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":66:8:66:19|Input HREADYOUT_S5 is unused.
233
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":67:8:67:16|Input HRDATA_S6 is unused.
234
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":68:8:68:19|Input HREADYOUT_S6 is unused.
235
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":69:8:69:16|Input HRDATA_S7 is unused.
236
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":70:8:70:19|Input HREADYOUT_S7 is unused.
237
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":71:8:71:16|Input HRDATA_S8 is unused.
238
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":72:8:72:19|Input HREADYOUT_S8 is unused.
239
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":73:8:73:16|Input HRDATA_S9 is unused.
240
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":74:8:74:19|Input HREADYOUT_S9 is unused.
241
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":75:8:75:17|Input HRDATA_S10 is unused.
242
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":76:8:76:20|Input HREADYOUT_S10 is unused.
243
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":77:8:77:17|Input HRDATA_S11 is unused.
244
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":78:8:78:20|Input HREADYOUT_S11 is unused.
245
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":79:8:79:17|Input HRDATA_S12 is unused.
246
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":80:8:80:20|Input HREADYOUT_S12 is unused.
247
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":81:8:81:17|Input HRDATA_S13 is unused.
248
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":82:8:82:20|Input HREADYOUT_S13 is unused.
249
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":83:8:83:17|Input HRDATA_S14 is unused.
250
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":84:8:84:20|Input HREADYOUT_S14 is unused.
251
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":85:8:85:17|Input HRDATA_S15 is unused.
252
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":86:8:86:20|Input HREADYOUT_S15 is unused.
253
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":87:8:87:17|Input HRDATA_S16 is unused.
254
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":88:8:88:20|Input HREADYOUT_S16 is unused.
255
@N: CL201 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd":398:8:398:9|Trying to extract state machine for register arbRegSMCurrentState.
256
Extracted state machine for register arbRegSMCurrentState
257
State machine has 16 reachable states with original encodings of:
258
   0000
259
   0001
260
   0010
261
   0011
262
   0100
263
   0101
264
   0110
265
   0111
266
   1000
267
   1001
268
   1010
269
   1011
270
   1100
271
   1101
272
   1110
273
   1111
274
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":54:8:54:16|Input HWDATA_M1 is unused.
275
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":63:8:63:16|Input HWDATA_M2 is unused.
276
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":72:8:72:16|Input HWDATA_M3 is unused.
277
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":87:8:87:16|Input HRDATA_S1 is unused.
278
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":88:8:88:19|Input HREADYOUT_S1 is unused.
279
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":89:8:89:15|Input HRESP_S1 is unused.
280
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":98:8:98:16|Input HRDATA_S2 is unused.
281
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":99:8:99:19|Input HREADYOUT_S2 is unused.
282
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":100:8:100:15|Input HRESP_S2 is unused.
283
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":109:8:109:16|Input HRDATA_S3 is unused.
284
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":110:8:110:19|Input HREADYOUT_S3 is unused.
285
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":111:8:111:15|Input HRESP_S3 is unused.
286
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":120:8:120:16|Input HRDATA_S4 is unused.
287
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":121:8:121:19|Input HREADYOUT_S4 is unused.
288
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":122:8:122:15|Input HRESP_S4 is unused.
289
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":131:8:131:16|Input HRDATA_S5 is unused.
290
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":132:8:132:19|Input HREADYOUT_S5 is unused.
291
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":133:8:133:15|Input HRESP_S5 is unused.
292
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":142:8:142:16|Input HRDATA_S6 is unused.
293
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":143:8:143:19|Input HREADYOUT_S6 is unused.
294
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":144:8:144:15|Input HRESP_S6 is unused.
295
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":153:8:153:16|Input HRDATA_S7 is unused.
296
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":154:8:154:19|Input HREADYOUT_S7 is unused.
297
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":155:8:155:15|Input HRESP_S7 is unused.
298
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":164:8:164:16|Input HRDATA_S8 is unused.
299
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":165:8:165:19|Input HREADYOUT_S8 is unused.
300
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":166:8:166:15|Input HRESP_S8 is unused.
301
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":175:8:175:16|Input HRDATA_S9 is unused.
302
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":176:8:176:19|Input HREADYOUT_S9 is unused.
303
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":177:8:177:15|Input HRESP_S9 is unused.
304
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":186:8:186:17|Input HRDATA_S10 is unused.
305
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":187:8:187:20|Input HREADYOUT_S10 is unused.
306
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":188:8:188:16|Input HRESP_S10 is unused.
307
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":197:8:197:17|Input HRDATA_S11 is unused.
308
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":198:8:198:20|Input HREADYOUT_S11 is unused.
309
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":199:8:199:16|Input HRESP_S11 is unused.
310
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":208:8:208:17|Input HRDATA_S12 is unused.
311
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":209:8:209:20|Input HREADYOUT_S12 is unused.
312
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":210:8:210:16|Input HRESP_S12 is unused.
313
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":219:8:219:17|Input HRDATA_S13 is unused.
314
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":220:8:220:20|Input HREADYOUT_S13 is unused.
315
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":221:8:221:16|Input HRESP_S13 is unused.
316
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":230:8:230:17|Input HRDATA_S14 is unused.
317
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":231:8:231:20|Input HREADYOUT_S14 is unused.
318
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":232:8:232:16|Input HRESP_S14 is unused.
319
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":241:8:241:17|Input HRDATA_S15 is unused.
320
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":242:8:242:20|Input HREADYOUT_S15 is unused.
321
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":243:8:243:16|Input HRESP_S15 is unused.
322
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":252:8:252:17|Input HRDATA_S16 is unused.
323
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":253:8:253:20|Input HREADYOUT_S16 is unused.
324
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":254:8:254:16|Input HRESP_S16 is unused.
325
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":124:0:124:8|Input port bit 0 of htrans_m0(1 downto 0) is unused
326
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":135:0:135:8|Input port bit 0 of htrans_m1(1 downto 0) is unused
327
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":146:0:146:8|Input port bit 0 of htrans_m2(1 downto 0) is unused
328
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":157:0:157:8|Input port bit 0 of htrans_m3(1 downto 0) is unused
329
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":167:0:167:7|Input port bit 1 of hresp_s0(1 downto 0) is unused
330
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":180:0:180:7|Input port bit 1 of hresp_s1(1 downto 0) is unused
331
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":193:0:193:7|Input port bit 1 of hresp_s2(1 downto 0) is unused
332
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":206:0:206:7|Input port bit 1 of hresp_s3(1 downto 0) is unused
333
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":219:0:219:7|Input port bit 1 of hresp_s4(1 downto 0) is unused
334
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":232:0:232:7|Input port bit 1 of hresp_s5(1 downto 0) is unused
335
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":245:0:245:7|Input port bit 1 of hresp_s6(1 downto 0) is unused
336
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":258:0:258:7|Input port bit 1 of hresp_s7(1 downto 0) is unused
337
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":271:0:271:7|Input port bit 1 of hresp_s8(1 downto 0) is unused
338
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":284:0:284:7|Input port bit 1 of hresp_s9(1 downto 0) is unused
339
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":297:0:297:8|Input port bit 1 of hresp_s10(1 downto 0) is unused
340
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":310:0:310:8|Input port bit 1 of hresp_s11(1 downto 0) is unused
341
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":323:0:323:8|Input port bit 1 of hresp_s12(1 downto 0) is unused
342
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":336:0:336:8|Input port bit 1 of hresp_s13(1 downto 0) is unused
343
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":349:0:349:8|Input port bit 1 of hresp_s14(1 downto 0) is unused
344
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":362:0:362:8|Input port bit 1 of hresp_s15(1 downto 0) is unused
345
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":375:0:375:8|Input port bit 1 of hresp_s16(1 downto 0) is unused
346
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":127:0:127:8|Input HBURST_M0 is unused.
347
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":128:0:128:7|Input HPROT_M0 is unused.
348
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":138:0:138:8|Input HBURST_M1 is unused.
349
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":139:0:139:7|Input HPROT_M1 is unused.
350
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":149:0:149:8|Input HBURST_M2 is unused.
351
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":150:0:150:7|Input HPROT_M2 is unused.
352
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":160:0:160:8|Input HBURST_M3 is unused.
353
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":161:0:161:7|Input HPROT_M3 is unused.
354
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":46:0:46:7|Input PRDATAS1 is unused.
355
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":47:0:47:7|Input PRDATAS2 is unused.
356
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":48:0:48:7|Input PRDATAS3 is unused.
357
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":49:0:49:7|Input PRDATAS4 is unused.
358
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":50:0:50:7|Input PRDATAS5 is unused.
359
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":51:0:51:7|Input PRDATAS6 is unused.
360
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":52:0:52:7|Input PRDATAS7 is unused.
361
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":53:0:53:7|Input PRDATAS8 is unused.
362
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":54:0:54:7|Input PRDATAS9 is unused.
363
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":55:0:55:8|Input PRDATAS10 is unused.
364
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":56:0:56:8|Input PRDATAS11 is unused.
365
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":57:0:57:8|Input PRDATAS12 is unused.
366
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":58:0:58:8|Input PRDATAS13 is unused.
367
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":59:0:59:8|Input PRDATAS14 is unused.
368
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":60:0:60:8|Input PRDATAS15 is unused.
369
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd":41:20:41:36|Input BAUD_VAL_FRACTION is unused.
370
@N: CL201 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd":134:4:134:5|Trying to extract state machine for register xmit_state.
371
Extracted state machine for register xmit_state
372
State machine has 6 reachable states with original encodings of:
373
   00000000000000000000000000000000
374
   00000000000000000000000000000001
375
   00000000000000000000000000000010
376
   00000000000000000000000000000011
377
   00000000000000000000000000000100
378
   00000000000000000000000000000101
379
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd":45:9:45:19|Input tx_dout_reg is unused.
380
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd":46:9:46:18|Input fifo_empty is unused.
381
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd":47:9:47:17|Input fifo_full is unused.
382
@N: CL201 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd":264:6:264:7|Trying to extract state machine for register rx_state.
383
Extracted state machine for register rx_state
384
State machine has 4 reachable states with original encodings of:
385
   00
386
   01
387
   10
388
   11
389
@W: CL246 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":83:6:83:10|Input port bits 1 to 0 of paddr(4 downto 0) are unused. Assign logic for all port bits or change the input port size.
390
 
391
At c_vhdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 105MB peak: 112MB)
392
 
393
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
394
 
395
Process completed successfully.
396
# Sat Jun 02 22:53:11 2018
397
 
398
###########################################################]
399
Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016
400
@N|Running in 64-bit mode
401
 
402
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 75MB)
403
 
404
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
405
 
406
Process completed successfully.
407
# Sat Jun 02 22:53:12 2018
408
 
409
###########################################################]
410
@END
411
 
412
At c_hdl Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 3MB peak: 4MB)
413
 
414
Process took 0h:00m:03s realtime, 0h:00m:02s cputime
415
 
416
Process completed successfully.
417
# Sat Jun 02 22:53:12 2018
418
 
419
###########################################################]

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