| 1 |
3 |
uson |
#defaultlanguage:vhdl
|
| 2 |
|
|
#OPTIONS:"|-layerid|0|-orig_srs|C:\\Actelprj\\test79_AHBmaster\\synthesis\\synwork\\top_comp.srs|-top|work.top|-prodtype|synplify_pro|-nram|-fixsmult|-divnmod|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-vhdl2008|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREUARTAPB_LIB|-lib|COREUARTAPB_LIB|-lib|COREUARTAPB_LIB|-lib|COREUARTAPB_LIB|-lib|COREUARTAPB_LIB|-lib|COREUARTAPB_LIB|-lib|COREUARTAPB_LIB|-lib|COREAHBLITE_LIB|-lib|COREUARTAPB_LIB|-lib|work"
|
| 3 |
|
|
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\bin64\\c_vhdl.exe":1479949892
|
| 4 |
|
|
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\location.map":1478775588
|
| 5 |
|
|
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\std.vhd":1487912986
|
| 6 |
|
|
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd\\snps_haps_pkg.vhd":1487912854
|
| 7 |
|
|
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\std1164.vhd":1487912986
|
| 8 |
|
|
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\std_textio.vhd":1487912986
|
| 9 |
|
|
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\numeric.vhd":1487912986
|
| 10 |
|
|
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd\\umr_capim.vhd":1487912854
|
| 11 |
|
|
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\arith.vhd":1487912986
|
| 12 |
|
|
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\unsigned.vhd":1487912986
|
| 13 |
|
|
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd\\hyperents.vhd":1487912854
|
| 14 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\hdl\\AHBMASTER_FIC.vhd":1527947376
|
| 15 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHB2APB\\1.1.101\\rtl\\vhdl\\u\\CoreAHB2APB.vhd":1527947216
|
| 16 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAPB\\1.1.101\\rtl\\vhdl\\o\\MuxP2B.vhd":1527947216
|
| 17 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_addrdec.vhd":1527947216
|
| 18 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_defaultslavesm.vhd":1527947216
|
| 19 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_slavearbiter.vhd":1527947216
|
| 20 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_pkg.vhd":1527947216
|
| 21 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\Clock_gen.vhd":1527947577
|
| 22 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\Rx_async.vhd":1527947577
|
| 23 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\Tx_async.vhd":1527947577
|
| 24 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\fifo_256x8_pa3.vhd":1527947577
|
| 25 |
|
|
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\proasic\\proasic3.vhd":1487912850
|
| 26 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\coreuart_pkg.vhd":1527947577
|
| 27 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreAHBLite_0\\rtl\\vhdl\\core\\components.vhd":1527947577
|
| 28 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\components.vhd":1527947577
|
| 29 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAPB\\1.1.101\\rtl\\vhdl\\o\\CoreAPB.vhd":1527947216
|
| 30 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_masterstage.vhd":1527947216
|
| 31 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_slavestage.vhd":1527947216
|
| 32 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_matrix4x16.vhd":1527947216
|
| 33 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreAHBLite_0\\rtl\\vhdl\\core\\coreahblite.vhd":1527947577
|
| 34 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\CoreUART.vhd":1527947577
|
| 35 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\CoreUARTapb.vhd":1527947577
|
| 36 |
|
|
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\top.vhd":1527947577
|
| 37 |
|
|
|
| 38 |
|
|
1 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd" vhdl
|
| 39 |
|
|
2 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\MuxP2B.vhd" vhdl
|
| 40 |
|
|
3 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd" vhdl
|
| 41 |
|
|
4 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_addrdec.vhd" vhdl
|
| 42 |
|
|
5 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_defaultslavesm.vhd" vhdl
|
| 43 |
|
|
6 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd" vhdl
|
| 44 |
|
|
7 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd" vhdl
|
| 45 |
|
|
8 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavestage.vhd" vhdl
|
| 46 |
|
|
9 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd" vhdl
|
| 47 |
|
|
10 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_pkg.vhd" vhdl
|
| 48 |
|
|
11 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd" vhdl
|
| 49 |
|
|
12 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd" vhdl
|
| 50 |
|
|
13 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd" vhdl
|
| 51 |
|
|
14 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd" vhdl
|
| 52 |
|
|
15 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\fifo_256x8_pa3.vhd" vhdl
|
| 53 |
|
|
16 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\coreuart_pkg.vhd" vhdl
|
| 54 |
|
|
17 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd" vhdl
|
| 55 |
|
|
18 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd" vhdl
|
| 56 |
|
|
19 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\components.vhd" vhdl
|
| 57 |
|
|
20 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\components.vhd" vhdl
|
| 58 |
|
|
21 "C:\Actelprj\test79_AHBmaster\component\work\top\top.vhd" vhdl
|
| 59 |
|
|
|
| 60 |
|
|
# Dependency Lists (Uses list)
|
| 61 |
|
|
|
| 62 |
|
|
1 -1
|
| 63 |
|
|
2 -1
|
| 64 |
|
|
3 2
|
| 65 |
|
|
4 -1
|
| 66 |
|
|
5 -1
|
| 67 |
|
|
6 4 5
|
| 68 |
|
|
7 -1
|
| 69 |
|
|
8 7
|
| 70 |
|
|
9 6 8
|
| 71 |
|
|
10 -1
|
| 72 |
|
|
11 9 10
|
| 73 |
|
|
12 -1
|
| 74 |
|
|
13 -1
|
| 75 |
|
|
14 -1
|
| 76 |
|
|
15 -1
|
| 77 |
|
|
16 -1
|
| 78 |
|
|
17 12 14 13 15 16
|
| 79 |
|
|
18 17 16
|
| 80 |
|
|
19 -1
|
| 81 |
|
|
20 -1
|
| 82 |
|
|
21 0 1 11 3 18 19 20
|
| 83 |
|
|
|
| 84 |
|
|
# Dependency Lists (Users Of)
|
| 85 |
|
|
|
| 86 |
|
|
1 21
|
| 87 |
|
|
2 3
|
| 88 |
|
|
3 21
|
| 89 |
|
|
4 6
|
| 90 |
|
|
5 6
|
| 91 |
|
|
6 9
|
| 92 |
|
|
7 8
|
| 93 |
|
|
8 9
|
| 94 |
|
|
9 11
|
| 95 |
|
|
10 11
|
| 96 |
|
|
11 21
|
| 97 |
|
|
12 17
|
| 98 |
|
|
13 17
|
| 99 |
|
|
14 17
|
| 100 |
|
|
15 17
|
| 101 |
|
|
16 18 17
|
| 102 |
|
|
17 18
|
| 103 |
|
|
18 21
|
| 104 |
|
|
19 21
|
| 105 |
|
|
20 21
|
| 106 |
|
|
21 -1
|
| 107 |
|
|
|
| 108 |
|
|
# Design Unit to File Association
|
| 109 |
|
|
arch work ahbmaster_fic rtl 0
|
| 110 |
|
|
module work ahbmaster_fic 0
|
| 111 |
|
|
arch work coreahb2apb synth 1
|
| 112 |
|
|
module work coreahb2apb 1
|
| 113 |
|
|
arch work coreapb_l coreapb_li0 2
|
| 114 |
|
|
module work coreapb_l 2
|
| 115 |
|
|
arch work coreapb coreapb_o 3
|
| 116 |
|
|
module work coreapb 3
|
| 117 |
|
|
arch coreahblite_lib coreahblite_addrdec coreahblite_addrdec_arch 4
|
| 118 |
|
|
module coreahblite_lib coreahblite_addrdec 4
|
| 119 |
|
|
arch coreahblite_lib coreahblite_defaultslavesm coreahblite_defaultslavesm_arch 5
|
| 120 |
|
|
module coreahblite_lib coreahblite_defaultslavesm 5
|
| 121 |
|
|
arch coreahblite_lib coreahblite_masterstage coreahblite_masterstage_arch 6
|
| 122 |
|
|
module coreahblite_lib coreahblite_masterstage 6
|
| 123 |
|
|
arch coreahblite_lib coreahblite_slavearbiter coreahblite_slavearbiter_arch 7
|
| 124 |
|
|
module coreahblite_lib coreahblite_slavearbiter 7
|
| 125 |
|
|
arch coreahblite_lib coreahblite_slavestage trans 8
|
| 126 |
|
|
module coreahblite_lib coreahblite_slavestage 8
|
| 127 |
|
|
arch coreahblite_lib coreahblite_matrix4x16 coreahblite_matrix4x16_arch 9
|
| 128 |
|
|
module coreahblite_lib coreahblite_matrix4x16 9
|
| 129 |
|
|
arch coreahblite_lib top_coreahblite_0_coreahblite coreahblite_arch 11
|
| 130 |
|
|
module coreahblite_lib top_coreahblite_0_coreahblite 11
|
| 131 |
|
|
arch coreuartapb_lib top_coreuartapb_0_clock_gen rtl 12
|
| 132 |
|
|
module coreuartapb_lib top_coreuartapb_0_clock_gen 12
|
| 133 |
|
|
arch coreuartapb_lib top_coreuartapb_0_rx_async translated 13
|
| 134 |
|
|
module coreuartapb_lib top_coreuartapb_0_rx_async 13
|
| 135 |
|
|
arch coreuartapb_lib top_coreuartapb_0_tx_async translated 14
|
| 136 |
|
|
module coreuartapb_lib top_coreuartapb_0_tx_async 14
|
| 137 |
|
|
arch coreuartapb_lib top_coreuartapb_0_fifo_256x8_pa3 translated 15
|
| 138 |
|
|
module coreuartapb_lib top_coreuartapb_0_fifo_256x8_pa3 15
|
| 139 |
|
|
arch coreuartapb_lib top_coreuartapb_0_fifo_256x8 translated 15
|
| 140 |
|
|
module coreuartapb_lib top_coreuartapb_0_fifo_256x8 15
|
| 141 |
|
|
arch coreuartapb_lib top_coreuartapb_0_coreuart translated 17
|
| 142 |
|
|
module coreuartapb_lib top_coreuartapb_0_coreuart 17
|
| 143 |
|
|
arch coreuartapb_lib top_coreuartapb_0_coreuartapb translated 18
|
| 144 |
|
|
module coreuartapb_lib top_coreuartapb_0_coreuartapb 18
|
| 145 |
|
|
arch work top rtl 21
|
| 146 |
|
|
module work top 21
|
| 147 |
|
|
|
| 148 |
|
|
|
| 149 |
|
|
# Configuration files used
|
