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URL https://opencores.org/ocsvn/ahbmaster/ahbmaster/trunk

Subversion Repositories ahbmaster

[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [synthesis/] [synwork/] [layer0.tlg] - Blame information for rev 3

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Line No. Rev Author Line
1 3 uson
@N: CD231 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vhd2008\std1164.vhd":890:16:890:17|Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000".
2
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\work\top\top.vhd":23:7:23:9|Synthesizing work.top.rtl.
3
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":62:7:62:35|Synthesizing coreuartapb_lib.top_coreuartapb_0_coreuartapb.translated.
4
@N: CD364 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":305:16:305:26|Removing redundant assignment.
5
@N: CD364 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":333:15:333:25|Removing redundant assignment.
6
@W: CD638 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":153:10:153:20|Signal controlreg3 is undriven. Either assign the signal a value or remove the signal declaration.
7
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":34:7:34:32|Synthesizing coreuartapb_lib.top_coreuartapb_0_coreuart.translated.
8
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":265:21:265:31|Signal rx_dout_reg in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
9
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":265:34:265:49|Signal parity_err_xhdl1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
10
@N: CD604 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":392:9:392:22|OTHERS clause is not synthesized.
11
@N: CD364 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":450:13:450:24|Removing redundant assignment.
12
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd":33:7:33:32|Synthesizing coreuartapb_lib.top_coreuartapb_0_rx_async.translated.
13
@N: CD233 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd":64:24:64:25|Using sequential encoding for type receive_states.
14
@N: CD364 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd":233:15:233:29|Removing redundant assignment.
15
@N: CD604 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd":253:21:253:34|OTHERS clause is not synthesized.
16
@N: CD364 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd":256:19:256:26|Removing redundant assignment.
17
@N: CD604 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd":318:19:318:33|OTHERS clause is not synthesized.
18
@N: CD604 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd":423:18:423:32|OTHERS clause is not synthesized.
19
Post processing for coreuartapb_lib.top_coreuartapb_0_rx_async.translated
20
@W: CL177 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd":443:6:443:7|Sharing sequential element clear_framing_error_en_i. Add a syn_preserve attribute to the element to prevent sharing.
21
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd":33:7:33:32|Synthesizing coreuartapb_lib.top_coreuartapb_0_tx_async.translated.
22
@N: CD364 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd":311:12:311:20|Removing redundant assignment.
23
Post processing for coreuartapb_lib.top_coreuartapb_0_tx_async.translated
24
@W: CL190 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd":134:4:134:5|Optimizing register bit fifo_read_en0 to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance.
25
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd":134:4:134:5|Pruning unused register fifo_read_en0. Make sure that there are no unused intermediate registers.
26
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd":35:7:35:33|Synthesizing coreuartapb_lib.top_coreuartapb_0_clock_gen.rtl.
27
@W: CD638 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd":54:7:54:19|Signal baud_cntr_one is undriven. Either assign the signal a value or remove the signal declaration.
28
Post processing for coreuartapb_lib.top_coreuartapb_0_clock_gen.rtl
29
Post processing for coreuartapb_lib.top_coreuartapb_0_coreuart.translated
30
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":439:7:439:8|Pruning unused register overflow_reg_3. Make sure that there are no unused intermediate registers.
31
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":414:7:414:8|Pruning unused register rx_dout_reg_empty_5. Make sure that there are no unused intermediate registers.
32
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":399:6:399:7|Pruning unused register rx_dout_reg_5(7 downto 0). Make sure that there are no unused intermediate registers.
33
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":367:6:367:7|Pruning unused register rx_state_4(1 downto 0). Make sure that there are no unused intermediate registers.
34
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":350:6:350:7|Pruning unused register clear_framing_error_reg0_3. Make sure that there are no unused intermediate registers.
35
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":350:6:350:7|Pruning unused register clear_framing_error_reg_3. Make sure that there are no unused intermediate registers.
36
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":333:6:333:7|Pruning unused register clear_parity_reg0_3. Make sure that there are no unused intermediate registers.
37
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":333:6:333:7|Pruning unused register clear_parity_reg_3. Make sure that there are no unused intermediate registers.
38
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":245:6:245:7|Pruning unused register fifo_write_tx_4. Make sure that there are no unused intermediate registers.
39
Post processing for coreuartapb_lib.top_coreuartapb_0_coreuartapb.translated
40
@W: CL252 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":153:10:153:20|Bit 0 of signal controlReg3 is floating -- simulation mismatch possible.
41
@W: CL252 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":153:10:153:20|Bit 1 of signal controlReg3 is floating -- simulation mismatch possible.
42
@W: CL252 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":153:10:153:20|Bit 2 of signal controlReg3 is floating -- simulation mismatch possible.
43
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":3:7:3:13|Synthesizing work.coreapb.coreapb_o.
44
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\MuxP2B.vhd":3:7:3:15|Synthesizing work.coreapb_l.coreapb_li0.
45
@N: CD604 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\MuxP2B.vhd":144:0:144:13|OTHERS clause is not synthesized.
46
Post processing for work.coreapb_l.coreapb_li0
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Post processing for work.coreapb.coreapb_o
48
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":27:7:27:35|Synthesizing coreahblite_lib.top_coreahblite_0_coreahblite.coreahblite_arch.
49
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":25:7:25:28|Synthesizing coreahblite_lib.coreahblite_matrix4x16.coreahblite_matrix4x16_arch.
50
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavestage.vhd":24:7:24:28|Synthesizing coreahblite_lib.coreahblite_slavestage.trans.
51
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd":22:7:22:30|Synthesizing coreahblite_lib.coreahblite_slavearbiter.coreahblite_slavearbiter_arch.
52
@N: CD604 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd":391:12:391:25|OTHERS clause is not synthesized.
53
Post processing for coreahblite_lib.coreahblite_slavearbiter.coreahblite_slavearbiter_arch
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Post processing for coreahblite_lib.coreahblite_slavestage.trans
55
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":24:7:24:29|Synthesizing coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch.
56
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":339:8:339:17|Signal sdataready in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
57
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":340:8:340:13|Signal shresp in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
58
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":341:8:341:16|Signal hrdata_s0 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
59
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":341:20:341:31|Signal hreadyout_s0 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
60
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":342:8:342:16|Signal hrdata_s1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
61
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":342:20:342:31|Signal hreadyout_s1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
62
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":343:8:343:16|Signal hrdata_s2 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
63
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":343:20:343:31|Signal hreadyout_s2 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
64
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":344:8:344:16|Signal hrdata_s3 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
65
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":344:20:344:31|Signal hreadyout_s3 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
66
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":345:8:345:16|Signal hrdata_s4 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
67
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":345:20:345:31|Signal hreadyout_s4 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
68
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":346:8:346:16|Signal hrdata_s5 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
69
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":346:20:346:31|Signal hreadyout_s5 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
70
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":347:8:347:16|Signal hrdata_s6 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
71
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":347:20:347:31|Signal hreadyout_s6 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
72
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":348:8:348:16|Signal hrdata_s7 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
73
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":348:20:348:31|Signal hreadyout_s7 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
74
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":349:8:349:16|Signal hrdata_s8 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
75
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":349:20:349:31|Signal hreadyout_s8 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
76
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":350:8:350:16|Signal hrdata_s9 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
77
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":350:20:350:31|Signal hreadyout_s9 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
78
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":351:8:351:17|Signal hrdata_s10 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
79
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":351:20:351:32|Signal hreadyout_s10 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
80
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":352:8:352:17|Signal hrdata_s11 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
81
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":352:20:352:32|Signal hreadyout_s11 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
82
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":353:8:353:17|Signal hrdata_s12 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
83
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":353:20:353:32|Signal hreadyout_s12 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
84
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":354:8:354:17|Signal hrdata_s13 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
85
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":354:20:354:32|Signal hreadyout_s13 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
86
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":355:8:355:17|Signal hrdata_s14 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
87
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":355:20:355:32|Signal hreadyout_s14 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
88
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":356:8:356:17|Signal hrdata_s15 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
89
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":356:20:356:32|Signal hreadyout_s15 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
90
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":357:8:357:17|Signal hrdata_s16 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
91
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":357:20:357:32|Signal hreadyout_s16 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
92
@N: CD604 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":637:12:637:25|OTHERS clause is not synthesized.
93
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_defaultslavesm.vhd":22:7:22:32|Synthesizing coreahblite_lib.coreahblite_defaultslavesm.coreahblite_defaultslavesm_arch.
94
@N: CD604 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_defaultslavesm.vhd":63:12:63:25|OTHERS clause is not synthesized.
95
Post processing for coreahblite_lib.coreahblite_defaultslavesm.coreahblite_defaultslavesm_arch
96
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_addrdec.vhd":50:7:50:25|Synthesizing coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch.
97
Post processing for coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch
98
Post processing for coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch
99
@W: CL177 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":644:8:644:9|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
100
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":24:7:24:29|Synthesizing coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch.
101
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":342:8:342:16|Signal hrdata_s1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
102
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":342:20:342:31|Signal hreadyout_s1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
103
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":343:8:343:16|Signal hrdata_s2 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
104
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":343:20:343:31|Signal hreadyout_s2 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
105
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":344:8:344:16|Signal hrdata_s3 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
106
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":344:20:344:31|Signal hreadyout_s3 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
107
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":345:8:345:16|Signal hrdata_s4 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
108
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":345:20:345:31|Signal hreadyout_s4 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
109
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":346:8:346:16|Signal hrdata_s5 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
110
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":346:20:346:31|Signal hreadyout_s5 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
111
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":347:8:347:16|Signal hrdata_s6 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
112
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":347:20:347:31|Signal hreadyout_s6 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
113
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":348:8:348:16|Signal hrdata_s7 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
114
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":348:20:348:31|Signal hreadyout_s7 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
115
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":349:8:349:16|Signal hrdata_s8 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
116
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":349:20:349:31|Signal hreadyout_s8 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
117
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":350:8:350:16|Signal hrdata_s9 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
118
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":350:20:350:31|Signal hreadyout_s9 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
119
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":351:8:351:17|Signal hrdata_s10 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
120
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":351:20:351:32|Signal hreadyout_s10 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
121
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":352:8:352:17|Signal hrdata_s11 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
122
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":352:20:352:32|Signal hreadyout_s11 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
123
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":353:8:353:17|Signal hrdata_s12 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
124
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":353:20:353:32|Signal hreadyout_s12 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
125
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":354:8:354:17|Signal hrdata_s13 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
126
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":354:20:354:32|Signal hreadyout_s13 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
127
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":355:8:355:17|Signal hrdata_s14 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
128
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":355:20:355:32|Signal hreadyout_s14 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
129
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":356:8:356:17|Signal hrdata_s15 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
130
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":356:20:356:32|Signal hreadyout_s15 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
131
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":357:8:357:17|Signal hrdata_s16 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
132
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":357:20:357:32|Signal hreadyout_s16 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
133
@N: CD604 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":637:12:637:25|OTHERS clause is not synthesized.
134
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_addrdec.vhd":50:7:50:25|Synthesizing coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch.
135
Post processing for coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch
136
Post processing for coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch
137
@W: CL177 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":644:8:644:9|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
138
Post processing for coreahblite_lib.coreahblite_matrix4x16.coreahblite_matrix4x16_arch
139
Post processing for coreahblite_lib.top_coreahblite_0_coreahblite.coreahblite_arch
140
@N: CD630 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd":12:7:12:17|Synthesizing work.coreahb2apb.synth.
141
Post processing for work.coreahb2apb.synth
142
@N: CD630 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":32:7:32:19|Synthesizing work.ahbmaster_fic.rtl.
143
@W: CD274 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":118:3:118:6|Incomplete case statement - add more cases or a when others
144
Post processing for work.ahbmaster_fic.rtl
145
@A: CL282 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Feedback mux created for signal HADDR_int[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
146
@A: CL282 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Feedback mux created for signal HWDATA_int[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
147
@W: CL190 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Optimizing register bit HTRANS(0) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
148
@W: CL260 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Pruning register bit 0 of HTRANS(1 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
149
Post processing for work.top.rtl
150
@N: CL201 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Trying to extract state machine for register ahb_fsm_current_state.
151
Extracted state machine for register ahb_fsm_current_state
152
State machine has 7 reachable states with original encodings of:
153
   000
154
   001
155
   010
156
   011
157
   100
158
   101
159
   110
160
@N: CL201 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd":336:4:336:5|Trying to extract state machine for register CurrentState.
161
Extracted state machine for register CurrentState
162
State machine has 8 reachable states with original encodings of:
163
   0000
164
   0001
165
   0100
166
   1001
167
   1010
168
   1011
169
   1110
170
   1111
171
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd":20:4:20:9|Input port bit 0 of htrans(1 downto 0) is unused
172
@W: CL246 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":45:8:45:17|Input port bits 16 to 1 of sdataready(16 downto 0) are unused. Assign logic for all port bits or change the input port size.
173
@W: CL246 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":46:8:46:13|Input port bits 16 to 1 of shresp(16 downto 0) are unused. Assign logic for all port bits or change the input port size.
174
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":57:8:57:16|Input HRDATA_S1 is unused.
175
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":58:8:58:19|Input HREADYOUT_S1 is unused.
176
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":59:8:59:16|Input HRDATA_S2 is unused.
177
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":60:8:60:19|Input HREADYOUT_S2 is unused.
178
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":61:8:61:16|Input HRDATA_S3 is unused.
179
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":62:8:62:19|Input HREADYOUT_S3 is unused.
180
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":63:8:63:16|Input HRDATA_S4 is unused.
181
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":64:8:64:19|Input HREADYOUT_S4 is unused.
182
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":65:8:65:16|Input HRDATA_S5 is unused.
183
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":66:8:66:19|Input HREADYOUT_S5 is unused.
184
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":67:8:67:16|Input HRDATA_S6 is unused.
185
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":68:8:68:19|Input HREADYOUT_S6 is unused.
186
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":69:8:69:16|Input HRDATA_S7 is unused.
187
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":70:8:70:19|Input HREADYOUT_S7 is unused.
188
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":71:8:71:16|Input HRDATA_S8 is unused.
189
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":72:8:72:19|Input HREADYOUT_S8 is unused.
190
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":73:8:73:16|Input HRDATA_S9 is unused.
191
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":74:8:74:19|Input HREADYOUT_S9 is unused.
192
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":75:8:75:17|Input HRDATA_S10 is unused.
193
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":76:8:76:20|Input HREADYOUT_S10 is unused.
194
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":77:8:77:17|Input HRDATA_S11 is unused.
195
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":78:8:78:20|Input HREADYOUT_S11 is unused.
196
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":79:8:79:17|Input HRDATA_S12 is unused.
197
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":80:8:80:20|Input HREADYOUT_S12 is unused.
198
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":81:8:81:17|Input HRDATA_S13 is unused.
199
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":82:8:82:20|Input HREADYOUT_S13 is unused.
200
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":83:8:83:17|Input HRDATA_S14 is unused.
201
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":84:8:84:20|Input HREADYOUT_S14 is unused.
202
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":85:8:85:17|Input HRDATA_S15 is unused.
203
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":86:8:86:20|Input HREADYOUT_S15 is unused.
204
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":87:8:87:17|Input HRDATA_S16 is unused.
205
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":88:8:88:20|Input HREADYOUT_S16 is unused.
206
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":45:8:45:17|Input SDATAREADY is unused.
207
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":46:8:46:13|Input SHRESP is unused.
208
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":55:8:55:16|Input HRDATA_S0 is unused.
209
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":56:8:56:19|Input HREADYOUT_S0 is unused.
210
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":57:8:57:16|Input HRDATA_S1 is unused.
211
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":58:8:58:19|Input HREADYOUT_S1 is unused.
212
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":59:8:59:16|Input HRDATA_S2 is unused.
213
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":60:8:60:19|Input HREADYOUT_S2 is unused.
214
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":61:8:61:16|Input HRDATA_S3 is unused.
215
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":62:8:62:19|Input HREADYOUT_S3 is unused.
216
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":63:8:63:16|Input HRDATA_S4 is unused.
217
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":64:8:64:19|Input HREADYOUT_S4 is unused.
218
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":65:8:65:16|Input HRDATA_S5 is unused.
219
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":66:8:66:19|Input HREADYOUT_S5 is unused.
220
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":67:8:67:16|Input HRDATA_S6 is unused.
221
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":68:8:68:19|Input HREADYOUT_S6 is unused.
222
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":69:8:69:16|Input HRDATA_S7 is unused.
223
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":70:8:70:19|Input HREADYOUT_S7 is unused.
224
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":71:8:71:16|Input HRDATA_S8 is unused.
225
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":72:8:72:19|Input HREADYOUT_S8 is unused.
226
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":73:8:73:16|Input HRDATA_S9 is unused.
227
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":74:8:74:19|Input HREADYOUT_S9 is unused.
228
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":75:8:75:17|Input HRDATA_S10 is unused.
229
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":76:8:76:20|Input HREADYOUT_S10 is unused.
230
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":77:8:77:17|Input HRDATA_S11 is unused.
231
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":78:8:78:20|Input HREADYOUT_S11 is unused.
232
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":79:8:79:17|Input HRDATA_S12 is unused.
233
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":80:8:80:20|Input HREADYOUT_S12 is unused.
234
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":81:8:81:17|Input HRDATA_S13 is unused.
235
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":82:8:82:20|Input HREADYOUT_S13 is unused.
236
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":83:8:83:17|Input HRDATA_S14 is unused.
237
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":84:8:84:20|Input HREADYOUT_S14 is unused.
238
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":85:8:85:17|Input HRDATA_S15 is unused.
239
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":86:8:86:20|Input HREADYOUT_S15 is unused.
240
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":87:8:87:17|Input HRDATA_S16 is unused.
241
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":88:8:88:20|Input HREADYOUT_S16 is unused.
242
@N: CL201 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd":398:8:398:9|Trying to extract state machine for register arbRegSMCurrentState.
243
Extracted state machine for register arbRegSMCurrentState
244
State machine has 16 reachable states with original encodings of:
245
   0000
246
   0001
247
   0010
248
   0011
249
   0100
250
   0101
251
   0110
252
   0111
253
   1000
254
   1001
255
   1010
256
   1011
257
   1100
258
   1101
259
   1110
260
   1111
261
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":54:8:54:16|Input HWDATA_M1 is unused.
262
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":63:8:63:16|Input HWDATA_M2 is unused.
263
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":72:8:72:16|Input HWDATA_M3 is unused.
264
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":87:8:87:16|Input HRDATA_S1 is unused.
265
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":88:8:88:19|Input HREADYOUT_S1 is unused.
266
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":89:8:89:15|Input HRESP_S1 is unused.
267
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":98:8:98:16|Input HRDATA_S2 is unused.
268
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":99:8:99:19|Input HREADYOUT_S2 is unused.
269
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":100:8:100:15|Input HRESP_S2 is unused.
270
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":109:8:109:16|Input HRDATA_S3 is unused.
271
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":110:8:110:19|Input HREADYOUT_S3 is unused.
272
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":111:8:111:15|Input HRESP_S3 is unused.
273
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":120:8:120:16|Input HRDATA_S4 is unused.
274
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":121:8:121:19|Input HREADYOUT_S4 is unused.
275
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":122:8:122:15|Input HRESP_S4 is unused.
276
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":131:8:131:16|Input HRDATA_S5 is unused.
277
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":132:8:132:19|Input HREADYOUT_S5 is unused.
278
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":133:8:133:15|Input HRESP_S5 is unused.
279
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":142:8:142:16|Input HRDATA_S6 is unused.
280
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":143:8:143:19|Input HREADYOUT_S6 is unused.
281
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":144:8:144:15|Input HRESP_S6 is unused.
282
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":153:8:153:16|Input HRDATA_S7 is unused.
283
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":154:8:154:19|Input HREADYOUT_S7 is unused.
284
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":155:8:155:15|Input HRESP_S7 is unused.
285
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":164:8:164:16|Input HRDATA_S8 is unused.
286
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":165:8:165:19|Input HREADYOUT_S8 is unused.
287
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":166:8:166:15|Input HRESP_S8 is unused.
288
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":175:8:175:16|Input HRDATA_S9 is unused.
289
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":176:8:176:19|Input HREADYOUT_S9 is unused.
290
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":177:8:177:15|Input HRESP_S9 is unused.
291
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":186:8:186:17|Input HRDATA_S10 is unused.
292
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":187:8:187:20|Input HREADYOUT_S10 is unused.
293
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":188:8:188:16|Input HRESP_S10 is unused.
294
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":197:8:197:17|Input HRDATA_S11 is unused.
295
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":198:8:198:20|Input HREADYOUT_S11 is unused.
296
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":199:8:199:16|Input HRESP_S11 is unused.
297
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":208:8:208:17|Input HRDATA_S12 is unused.
298
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":209:8:209:20|Input HREADYOUT_S12 is unused.
299
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":210:8:210:16|Input HRESP_S12 is unused.
300
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":219:8:219:17|Input HRDATA_S13 is unused.
301
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":220:8:220:20|Input HREADYOUT_S13 is unused.
302
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":221:8:221:16|Input HRESP_S13 is unused.
303
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":230:8:230:17|Input HRDATA_S14 is unused.
304
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":231:8:231:20|Input HREADYOUT_S14 is unused.
305
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":232:8:232:16|Input HRESP_S14 is unused.
306
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":241:8:241:17|Input HRDATA_S15 is unused.
307
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":242:8:242:20|Input HREADYOUT_S15 is unused.
308
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":243:8:243:16|Input HRESP_S15 is unused.
309
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":252:8:252:17|Input HRDATA_S16 is unused.
310
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":253:8:253:20|Input HREADYOUT_S16 is unused.
311
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd":254:8:254:16|Input HRESP_S16 is unused.
312
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":124:0:124:8|Input port bit 0 of htrans_m0(1 downto 0) is unused
313
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":135:0:135:8|Input port bit 0 of htrans_m1(1 downto 0) is unused
314
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":146:0:146:8|Input port bit 0 of htrans_m2(1 downto 0) is unused
315
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":157:0:157:8|Input port bit 0 of htrans_m3(1 downto 0) is unused
316
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":167:0:167:7|Input port bit 1 of hresp_s0(1 downto 0) is unused
317
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":180:0:180:7|Input port bit 1 of hresp_s1(1 downto 0) is unused
318
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":193:0:193:7|Input port bit 1 of hresp_s2(1 downto 0) is unused
319
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":206:0:206:7|Input port bit 1 of hresp_s3(1 downto 0) is unused
320
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":219:0:219:7|Input port bit 1 of hresp_s4(1 downto 0) is unused
321
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":232:0:232:7|Input port bit 1 of hresp_s5(1 downto 0) is unused
322
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":245:0:245:7|Input port bit 1 of hresp_s6(1 downto 0) is unused
323
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":258:0:258:7|Input port bit 1 of hresp_s7(1 downto 0) is unused
324
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":271:0:271:7|Input port bit 1 of hresp_s8(1 downto 0) is unused
325
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":284:0:284:7|Input port bit 1 of hresp_s9(1 downto 0) is unused
326
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":297:0:297:8|Input port bit 1 of hresp_s10(1 downto 0) is unused
327
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":310:0:310:8|Input port bit 1 of hresp_s11(1 downto 0) is unused
328
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":323:0:323:8|Input port bit 1 of hresp_s12(1 downto 0) is unused
329
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":336:0:336:8|Input port bit 1 of hresp_s13(1 downto 0) is unused
330
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":349:0:349:8|Input port bit 1 of hresp_s14(1 downto 0) is unused
331
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":362:0:362:8|Input port bit 1 of hresp_s15(1 downto 0) is unused
332
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":375:0:375:8|Input port bit 1 of hresp_s16(1 downto 0) is unused
333
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":127:0:127:8|Input HBURST_M0 is unused.
334
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":128:0:128:7|Input HPROT_M0 is unused.
335
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":138:0:138:8|Input HBURST_M1 is unused.
336
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":139:0:139:7|Input HPROT_M1 is unused.
337
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":149:0:149:8|Input HBURST_M2 is unused.
338
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":150:0:150:7|Input HPROT_M2 is unused.
339
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":160:0:160:8|Input HBURST_M3 is unused.
340
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":161:0:161:7|Input HPROT_M3 is unused.
341
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":46:0:46:7|Input PRDATAS1 is unused.
342
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":47:0:47:7|Input PRDATAS2 is unused.
343
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":48:0:48:7|Input PRDATAS3 is unused.
344
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":49:0:49:7|Input PRDATAS4 is unused.
345
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":50:0:50:7|Input PRDATAS5 is unused.
346
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":51:0:51:7|Input PRDATAS6 is unused.
347
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":52:0:52:7|Input PRDATAS7 is unused.
348
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":53:0:53:7|Input PRDATAS8 is unused.
349
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":54:0:54:7|Input PRDATAS9 is unused.
350
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":55:0:55:8|Input PRDATAS10 is unused.
351
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":56:0:56:8|Input PRDATAS11 is unused.
352
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":57:0:57:8|Input PRDATAS12 is unused.
353
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":58:0:58:8|Input PRDATAS13 is unused.
354
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":59:0:59:8|Input PRDATAS14 is unused.
355
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd":60:0:60:8|Input PRDATAS15 is unused.
356
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd":41:20:41:36|Input BAUD_VAL_FRACTION is unused.
357
@N: CL201 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd":134:4:134:5|Trying to extract state machine for register xmit_state.
358
Extracted state machine for register xmit_state
359
State machine has 6 reachable states with original encodings of:
360
   00000000000000000000000000000000
361
   00000000000000000000000000000001
362
   00000000000000000000000000000010
363
   00000000000000000000000000000011
364
   00000000000000000000000000000100
365
   00000000000000000000000000000101
366
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd":45:9:45:19|Input tx_dout_reg is unused.
367
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd":46:9:46:18|Input fifo_empty is unused.
368
@N: CL159 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd":47:9:47:17|Input fifo_full is unused.
369
@N: CL201 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd":264:6:264:7|Trying to extract state machine for register rx_state.
370
Extracted state machine for register rx_state
371
State machine has 4 reachable states with original encodings of:
372
   00
373
   01
374
   10
375
   11
376
@W: CL246 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":83:6:83:10|Input port bits 1 to 0 of paddr(4 downto 0) are unused. Assign logic for all port bits or change the input port size.

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