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-- Version: v11.8 SP3 11.8.3.6
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library ieee;
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use ieee.std_logic_1164.all;
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library proasic3;
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use proasic3.all;
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entity AHBMASTER_FIC is
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port( AHBMASTER_FIC_0_AHBmaster_HADDR_0 : out std_logic;
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AHBMASTER_FIC_0_AHBmaster_HADDR_1 : out std_logic;
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AHBMASTER_FIC_0_AHBmaster_HADDR_2 : out std_logic;
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AHBMASTER_FIC_0_AHBmaster_HADDR_22 : out std_logic;
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AHBMASTER_FIC_0_AHBmaster_HADDR_23 : out std_logic;
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AHBMASTER_FIC_0_AHBmaster_HADDR_24 : out std_logic;
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AHBMASTER_FIC_0_AHBmaster_HADDR_25 : out std_logic;
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AHBMASTER_FIC_0_AHBmaster_HADDR_26 : out std_logic;
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AHBMASTER_FIC_0_AHBmaster_HADDR_27 : out std_logic;
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AHBMASTER_FIC_0_AHBmaster_HADDR_28 : out std_logic;
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AHBMASTER_FIC_0_AHBmaster_HADDR_29 : out std_logic;
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AHBMASTER_FIC_0_AHBmaster_HRDATA : in std_logic_vector(7 downto 0);
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DATAOUT_c : out std_logic_vector(7 downto 0);
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DATAIN_c : in std_logic_vector(7 downto 0);
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AHBMASTER_FIC_0_AHBmaster_HWDATA : out std_logic_vector(7 downto 0);
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AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : out std_logic;
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ADDR_c_29 : in std_logic;
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ADDR_c_23 : in std_logic;
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ADDR_c_26 : in std_logic;
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ADDR_c_22 : in std_logic;
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ADDR_c_24 : in std_logic;
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ADDR_c_25 : in std_logic;
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ADDR_c_27 : in std_logic;
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ADDR_c_1 : in std_logic;
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ADDR_c_0 : in std_logic;
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ADDR_c_28 : in std_logic;
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ADDR_c_2 : in std_logic;
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AHBMASTER_FIC_0_AHBmaster_HWRITE : out std_logic;
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HCLK_c : in std_logic;
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ahb_busy_c : out std_logic;
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HRESETn_c : in std_logic;
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PREVDATASLAVEREADY_iv_i_0_i_o4_0 : in std_logic;
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N_163 : in std_logic;
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LWRITE_c : in std_logic;
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LREAD_c : in std_logic;
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N_398 : in std_logic;
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PREVDATASLAVEREADY_iv_i_0_i_o4_1 : in std_logic;
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N_340 : in std_logic
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);
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end AHBMASTER_FIC;
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architecture DEF_ARCH of AHBMASTER_FIC is
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component DFN1E0
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port( D : in std_logic := 'U';
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CLK : in std_logic := 'U';
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E : in std_logic := 'U';
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Q : out std_logic
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);
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end component;
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component DFN1C0
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port( D : in std_logic := 'U';
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CLK : in std_logic := 'U';
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CLR : in std_logic := 'U';
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Q : out std_logic
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);
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end component;
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component DFN1E0C0
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port( D : in std_logic := 'U';
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CLK : in std_logic := 'U';
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CLR : in std_logic := 'U';
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E : in std_logic := 'U';
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Q : out std_logic
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);
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end component;
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component DFN1E1C0
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port( D : in std_logic := 'U';
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CLK : in std_logic := 'U';
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CLR : in std_logic := 'U';
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E : in std_logic := 'U';
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Q : out std_logic
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);
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end component;
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component AO1A
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port( A : in std_logic := 'U';
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B : in std_logic := 'U';
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C : in std_logic := 'U';
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Y : out std_logic
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);
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end component;
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component NOR2A
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port( A : in std_logic := 'U';
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B : in std_logic := 'U';
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Y : out std_logic
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);
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end component;
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component AO1
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port( A : in std_logic := 'U';
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B : in std_logic := 'U';
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C : in std_logic := 'U';
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Y : out std_logic
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);
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end component;
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component OR2
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port( A : in std_logic := 'U';
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B : in std_logic := 'U';
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Y : out std_logic
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);
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end component;
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component NOR2B
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port( A : in std_logic := 'U';
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B : in std_logic := 'U';
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Y : out std_logic
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);
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end component;
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component AOI1
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port( A : in std_logic := 'U';
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B : in std_logic := 'U';
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C : in std_logic := 'U';
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Y : out std_logic
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);
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end component;
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component MX2C
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port( A : in std_logic := 'U';
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B : in std_logic := 'U';
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S : in std_logic := 'U';
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Y : out std_logic
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);
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end component;
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component NOR3A
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port( A : in std_logic := 'U';
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B : in std_logic := 'U';
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C : in std_logic := 'U';
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Y : out std_logic
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);
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end component;
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component VCC
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port( Y : out std_logic
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);
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end component;
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component OR3C
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port( A : in std_logic := 'U';
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B : in std_logic := 'U';
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C : in std_logic := 'U';
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Y : out std_logic
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);
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end component;
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component DFN1P0
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port( D : in std_logic := 'U';
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CLK : in std_logic := 'U';
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PRE : in std_logic := 'U';
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Q : out std_logic
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);
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end component;
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component NOR2
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port( A : in std_logic := 'U';
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B : in std_logic := 'U';
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Y : out std_logic
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);
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end component;
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component OR2A
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port( A : in std_logic := 'U';
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B : in std_logic := 'U';
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Y : out std_logic
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);
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end component;
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component OR3
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port( A : in std_logic := 'U';
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B : in std_logic := 'U';
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C : in std_logic := 'U';
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Y : out std_logic
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);
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end component;
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component NOR3B
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port( A : in std_logic := 'U';
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B : in std_logic := 'U';
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C : in std_logic := 'U';
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Y : out std_logic
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);
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end component;
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component GND
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port( Y : out std_logic
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);
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end component;
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component NOR3
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port( A : in std_logic := 'U';
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B : in std_logic := 'U';
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C : in std_logic := 'U';
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Y : out std_logic
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);
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end component;
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signal \ahb_fsm_current_state_ns_i_0_2[0]\, N_125,
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un1_ahb_fsm_current_state_12_i_0, N_87,
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\ahb_fsm_current_state[5]_net_1\,
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\ahb_fsm_current_state[2]_net_1\, \HADDR_7_i_0[31]\,
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\HADDR_int[31]_net_1\, \HADDR_7_i_0[25]\,
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\HADDR_int[25]_net_1\, \HADDR_7_i_0[28]\,
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\HADDR_int[28]_net_1\, \HADDR_7_i_0[24]\,
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\HADDR_int[24]_net_1\, \HADDR_7_i_0[26]\,
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\HADDR_int[26]_net_1\, \HADDR_7_i_0[27]\,
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\HADDR_int[27]_net_1\, \HADDR_7_i_0[29]\,
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\HADDR_int[29]_net_1\, \HADDR_7_i_0[3]\,
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\HADDR_int[3]_net_1\, \HADDR_7_i_0[2]\,
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\HADDR_int[2]_net_1\, \HADDR_7_i_0[30]\,
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\HADDR_int[30]_net_1\, \HADDR_7_i_0[4]\,
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\HADDR_int[4]_net_1\, \ahb_fsm_current_state[0]_net_1\,
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un1_ahb_fsm_current_state_12_i_3,
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un1_ahb_fsm_current_state_12_i_0_a1_0,
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un1_ahb_fsm_current_state_12_i_2,
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\ahb_fsm_current_state[3]_net_1\, N_197,
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DATAOUT_0_sqmuxa_i_0, un1_ahb_fsm_current_state_7_i_0_0,
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\ahb_fsm_current_state[6]_net_1\,
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un1_ahb_fsm_current_state_7_i_0_a4_0_1,
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\ahb_fsm_current_state[1]_net_1\, N_N_3_mux,
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un1_ahb_fsm_current_state_8_0_2,
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un1_ahb_fsm_current_state_8_0_1,
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\ahb_fsm_current_state[4]_net_1\,
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HWDATA_1_sqmuxa_0_a5_0_a4_2_0,
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un1_ahb_fsm_current_state_12_i_0_a0_1,
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un1_ahb_fsm_current_state_8_0_0_a0_0, N_34, N_N_5_mux,
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\ahb_fsm_current_state_ns[4]\, N_74, N_188,
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HWDATA_1_sqmuxa, N_78,
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\ahb_fsm_current_state_RNO[6]_net_1\, N_89, N_582, N_26,
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N_583, N_30, N_581, N_580, N_369, N_129, N_32, N_76,
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\ahb_fsm_current_state_RNIP1UTR[1]_net_1\, \HWRITE_RNO_2\,
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\HWRITE_RNO_0\, un1_ahb_fsm_current_state_8, N_355,
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\DATAOUT_0_sqmuxa_i_0_a0\, N_91,
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\ahb_fsm_current_state_ns[3]\,
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\ahb_fsm_current_state_ns[5]\,
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\ahb_fsm_current_state_ns[6]\, ahb_busy_6, HWRITE_4,
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\ahb_fsm_current_state_RNO[5]_net_1\, N_379, N_86, N_84,
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\HWDATA_int[0]_net_1\, \HWDATA_int[1]_net_1\,
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\HWDATA_int[2]_net_1\, \HWDATA_int[3]_net_1\,
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\HWDATA_int[4]_net_1\, \HWDATA_int[5]_net_1\,
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\HWDATA_int[6]_net_1\, \HWDATA_int[7]_net_1\, \GND\,
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\VCC\ : std_logic;
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begin
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\HADDR_int[29]\ : DFN1E0
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port map(D => ADDR_c_27, CLK => HCLK_c, E => N_86, Q =>
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\HADDR_int[29]_net_1\);
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\ahb_fsm_current_state[2]\ : DFN1C0
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port map(D => \ahb_fsm_current_state_ns[4]\, CLK => HCLK_c,
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CLR => HRESETn_c, Q => \ahb_fsm_current_state[2]_net_1\);
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\DATAOUT[6]\ : DFN1E0C0
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port map(D => AHBMASTER_FIC_0_AHBmaster_HRDATA(6), CLK =>
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HCLK_c, CLR => HRESETn_c, E => N_355, Q => DATAOUT_c(6));
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\ahb_fsm_current_state[1]\ : DFN1C0
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port map(D => \ahb_fsm_current_state_ns[5]\, CLK => HCLK_c,
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CLR => HRESETn_c, Q => \ahb_fsm_current_state[1]_net_1\);
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HWRITE : DFN1E1C0
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port map(D => HWRITE_4, CLK => HCLK_c, CLR => HRESETn_c, E
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=> un1_ahb_fsm_current_state_8, Q =>
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AHBMASTER_FIC_0_AHBmaster_HWRITE);
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\HADDR[4]\ : DFN1E0C0
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port map(D => N_74, CLK => HCLK_c, CLR => HRESETn_c, E =>
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\ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q =>
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AHBMASTER_FIC_0_AHBmaster_HADDR_2);
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\HADDR_RNO_0[4]\ : AO1A
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port map(A => \HADDR_int[4]_net_1\, B => N_87, C =>
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\ahb_fsm_current_state[0]_net_1\, Y => \HADDR_7_i_0[4]\);
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\ahb_fsm_current_state_RNO_1[6]\ : NOR2A
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port map(A => N_91, B => N_89, Y => N_125);
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\ahb_fsm_current_state_RNIN71O4[4]\ : NOR2A
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port map(A => \ahb_fsm_current_state[4]_net_1\, B => N_340,
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Y => HWDATA_1_sqmuxa_0_a5_0_a4_2_0);
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\ahb_fsm_current_state_RNO[1]\ : AO1
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port map(A => \ahb_fsm_current_state[1]_net_1\, B => N_163,
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C => \ahb_fsm_current_state[2]_net_1\, Y =>
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\ahb_fsm_current_state_ns[5]\);
|
| 303 |
|
|
|
| 304 |
|
|
\ahb_fsm_current_state_RNI151J[3]\ : OR2
|
| 305 |
|
|
port map(A => \ahb_fsm_current_state[3]_net_1\, B =>
|
| 306 |
|
|
\ahb_fsm_current_state[0]_net_1\, Y => N_89);
|
| 307 |
|
|
|
| 308 |
|
|
\ahb_fsm_current_state_RNO[5]\ : NOR2B
|
| 309 |
|
|
port map(A => LWRITE_c, B =>
|
| 310 |
|
|
\ahb_fsm_current_state[6]_net_1\, Y =>
|
| 311 |
|
|
\ahb_fsm_current_state_RNO[5]_net_1\);
|
| 312 |
|
|
|
| 313 |
|
|
\ahb_fsm_current_state_RNI2H6Q[1]\ : NOR2B
|
| 314 |
|
|
port map(A => \ahb_fsm_current_state[1]_net_1\, B => N_398,
|
| 315 |
|
|
Y => un1_ahb_fsm_current_state_8_0_0_a0_0);
|
| 316 |
|
|
|
| 317 |
|
|
\ahb_fsm_current_state_RNO[6]\ : AOI1
|
| 318 |
|
|
port map(A => N_89, B => N_163, C =>
|
| 319 |
|
|
\ahb_fsm_current_state_ns_i_0_2[0]\, Y =>
|
| 320 |
|
|
\ahb_fsm_current_state_RNO[6]_net_1\);
|
| 321 |
|
|
|
| 322 |
|
|
\HADDR[30]\ : DFN1E0C0
|
| 323 |
|
|
port map(D => N_581, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 324 |
|
|
\ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q =>
|
| 325 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_28);
|
| 326 |
|
|
|
| 327 |
|
|
\DATAOUT[1]\ : DFN1E0C0
|
| 328 |
|
|
port map(D => AHBMASTER_FIC_0_AHBmaster_HRDATA(1), CLK =>
|
| 329 |
|
|
HCLK_c, CLR => HRESETn_c, E => N_355, Q => DATAOUT_c(1));
|
| 330 |
|
|
|
| 331 |
|
|
\ahb_fsm_current_state_RNO[3]\ : AO1
|
| 332 |
|
|
port map(A => \ahb_fsm_current_state[3]_net_1\, B => N_163,
|
| 333 |
|
|
C => HWDATA_1_sqmuxa, Y => \ahb_fsm_current_state_ns[3]\);
|
| 334 |
|
|
|
| 335 |
|
|
\HADDR_RNO[2]\ : NOR2A
|
| 336 |
|
|
port map(A => N_N_5_mux, B => \HADDR_7_i_0[2]\, Y => N_78);
|
| 337 |
|
|
|
| 338 |
|
|
\HADDR_int[27]\ : DFN1E0
|
| 339 |
|
|
port map(D => ADDR_c_25, CLK => HCLK_c, E => N_86, Q =>
|
| 340 |
|
|
\HADDR_int[27]_net_1\);
|
| 341 |
|
|
|
| 342 |
|
|
\HADDR_int[25]\ : DFN1E0
|
| 343 |
|
|
port map(D => ADDR_c_23, CLK => HCLK_c, E => N_86, Q =>
|
| 344 |
|
|
\HADDR_int[25]_net_1\);
|
| 345 |
|
|
|
| 346 |
|
|
\ahb_fsm_current_state_RNIKNNML[1]\ : NOR2A
|
| 347 |
|
|
port map(A => un1_ahb_fsm_current_state_7_i_0_a4_0_1, B =>
|
| 348 |
|
|
\DATAOUT_0_sqmuxa_i_0_a0\, Y => N_129);
|
| 349 |
|
|
|
| 350 |
|
|
\ahb_fsm_current_state_RNO[0]\ : AO1
|
| 351 |
|
|
port map(A => \ahb_fsm_current_state[0]_net_1\, B => N_163,
|
| 352 |
|
|
C => N_129, Y => \ahb_fsm_current_state_ns[6]\);
|
| 353 |
|
|
|
| 354 |
|
|
\HTRANS_1_RNO_0[1]\ : OR2
|
| 355 |
|
|
port map(A => \ahb_fsm_current_state[3]_net_1\, B =>
|
| 356 |
|
|
\ahb_fsm_current_state[6]_net_1\, Y =>
|
| 357 |
|
|
un1_ahb_fsm_current_state_7_i_0_0);
|
| 358 |
|
|
|
| 359 |
|
|
\HADDR_RNO_0[27]\ : MX2C
|
| 360 |
|
|
port map(A => ADDR_c_25, B => \HADDR_int[27]_net_1\, S =>
|
| 361 |
|
|
N_87, Y => \HADDR_7_i_0[27]\);
|
| 362 |
|
|
|
| 363 |
|
|
\HWDATA_int[5]\ : DFN1E0
|
| 364 |
|
|
port map(D => DATAIN_c(5), CLK => HCLK_c, E => N_84, Q =>
|
| 365 |
|
|
\HWDATA_int[5]_net_1\);
|
| 366 |
|
|
|
| 367 |
|
|
\ahb_fsm_current_state_RNI0AID8[1]\ : NOR3A
|
| 368 |
|
|
port map(A => \ahb_fsm_current_state[1]_net_1\, B => N_340,
|
| 369 |
|
|
C => PREVDATASLAVEREADY_iv_i_0_i_o4_1, Y =>
|
| 370 |
|
|
un1_ahb_fsm_current_state_12_i_0_a0_1);
|
| 371 |
|
|
|
| 372 |
|
|
\HADDR_RNO_0[29]\ : MX2C
|
| 373 |
|
|
port map(A => ADDR_c_27, B => \HADDR_int[29]_net_1\, S =>
|
| 374 |
|
|
N_87, Y => \HADDR_7_i_0[29]\);
|
| 375 |
|
|
|
| 376 |
|
|
\DATAOUT[0]\ : DFN1E0C0
|
| 377 |
|
|
port map(D => AHBMASTER_FIC_0_AHBmaster_HRDATA(0), CLK =>
|
| 378 |
|
|
HCLK_c, CLR => HRESETn_c, E => N_355, Q => DATAOUT_c(0));
|
| 379 |
|
|
|
| 380 |
|
|
\ahb_fsm_current_state_RNIP1UTR[1]\ : AO1A
|
| 381 |
|
|
port map(A => PREVDATASLAVEREADY_iv_i_0_i_o4_0, B =>
|
| 382 |
|
|
un1_ahb_fsm_current_state_12_i_0_a0_1, C =>
|
| 383 |
|
|
un1_ahb_fsm_current_state_12_i_3, Y =>
|
| 384 |
|
|
\ahb_fsm_current_state_RNIP1UTR[1]_net_1\);
|
| 385 |
|
|
|
| 386 |
|
|
VCC_i : VCC
|
| 387 |
|
|
port map(Y => \VCC\);
|
| 388 |
|
|
|
| 389 |
|
|
\HADDR_RNO_0[25]\ : MX2C
|
| 390 |
|
|
port map(A => ADDR_c_23, B => \HADDR_int[25]_net_1\, S =>
|
| 391 |
|
|
N_87, Y => \HADDR_7_i_0[25]\);
|
| 392 |
|
|
|
| 393 |
|
|
\HADDR[31]\ : DFN1E0C0
|
| 394 |
|
|
port map(D => N_580, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 395 |
|
|
\ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q =>
|
| 396 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_29);
|
| 397 |
|
|
|
| 398 |
|
|
\ahb_fsm_current_state_RNIPSK31[6]\ : OR3C
|
| 399 |
|
|
port map(A => \ahb_fsm_current_state[6]_net_1\, B =>
|
| 400 |
|
|
HRESETn_c, C => N_91, Y => N_86);
|
| 401 |
|
|
|
| 402 |
|
|
\ahb_fsm_current_state[6]\ : DFN1P0
|
| 403 |
|
|
port map(D => \ahb_fsm_current_state_RNO[6]_net_1\, CLK =>
|
| 404 |
|
|
HCLK_c, PRE => HRESETn_c, Q =>
|
| 405 |
|
|
\ahb_fsm_current_state[6]_net_1\);
|
| 406 |
|
|
|
| 407 |
|
|
\ahb_fsm_current_state[0]\ : DFN1C0
|
| 408 |
|
|
port map(D => \ahb_fsm_current_state_ns[6]\, CLK => HCLK_c,
|
| 409 |
|
|
CLR => HRESETn_c, Q => \ahb_fsm_current_state[0]_net_1\);
|
| 410 |
|
|
|
| 411 |
|
|
\HADDR_RNO_1[4]\ : NOR2
|
| 412 |
|
|
port map(A => ADDR_c_2, B => N_87, Y => N_188);
|
| 413 |
|
|
|
| 414 |
|
|
\HADDR_RNO[24]\ : NOR2A
|
| 415 |
|
|
port map(A => N_N_5_mux, B => \HADDR_7_i_0[24]\, Y => N_34);
|
| 416 |
|
|
|
| 417 |
|
|
\ahb_fsm_current_state_RNI98I87[1]\ : AO1A
|
| 418 |
|
|
port map(A => N_340, B =>
|
| 419 |
|
|
un1_ahb_fsm_current_state_12_i_0_a1_0, C =>
|
| 420 |
|
|
un1_ahb_fsm_current_state_12_i_2, Y =>
|
| 421 |
|
|
un1_ahb_fsm_current_state_12_i_3);
|
| 422 |
|
|
|
| 423 |
|
|
\HTRANS_1_RNO[1]\ : OR2
|
| 424 |
|
|
port map(A => un1_ahb_fsm_current_state_7_i_0_0, B => N_129,
|
| 425 |
|
|
Y => N_369);
|
| 426 |
|
|
|
| 427 |
|
|
\DATAOUT[4]\ : DFN1E0C0
|
| 428 |
|
|
port map(D => AHBMASTER_FIC_0_AHBmaster_HRDATA(4), CLK =>
|
| 429 |
|
|
HCLK_c, CLR => HRESETn_c, E => N_355, Q => DATAOUT_c(4));
|
| 430 |
|
|
|
| 431 |
|
|
\HADDR_int[31]\ : DFN1E0
|
| 432 |
|
|
port map(D => ADDR_c_29, CLK => HCLK_c, E => N_86, Q =>
|
| 433 |
|
|
\HADDR_int[31]_net_1\);
|
| 434 |
|
|
|
| 435 |
|
|
\HADDR_int[26]\ : DFN1E0
|
| 436 |
|
|
port map(D => ADDR_c_24, CLK => HCLK_c, E => N_86, Q =>
|
| 437 |
|
|
\HADDR_int[26]_net_1\);
|
| 438 |
|
|
|
| 439 |
|
|
\HWDATA[0]\ : DFN1E1C0
|
| 440 |
|
|
port map(D => \HWDATA_int[0]_net_1\, CLK => HCLK_c, CLR =>
|
| 441 |
|
|
HRESETn_c, E => HWDATA_1_sqmuxa, Q =>
|
| 442 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(0));
|
| 443 |
|
|
|
| 444 |
|
|
\HADDR_RNO_0[31]\ : MX2C
|
| 445 |
|
|
port map(A => ADDR_c_29, B => \HADDR_int[31]_net_1\, S =>
|
| 446 |
|
|
N_87, Y => \HADDR_7_i_0[31]\);
|
| 447 |
|
|
|
| 448 |
|
|
\HWDATA_int[0]\ : DFN1E0
|
| 449 |
|
|
port map(D => DATAIN_c(0), CLK => HCLK_c, E => N_84, Q =>
|
| 450 |
|
|
\HWDATA_int[0]_net_1\);
|
| 451 |
|
|
|
| 452 |
|
|
\HWDATA[4]\ : DFN1E1C0
|
| 453 |
|
|
port map(D => \HWDATA_int[4]_net_1\, CLK => HCLK_c, CLR =>
|
| 454 |
|
|
HRESETn_c, E => HWDATA_1_sqmuxa, Q =>
|
| 455 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(4));
|
| 456 |
|
|
|
| 457 |
|
|
\HWDATA_int[1]\ : DFN1E0
|
| 458 |
|
|
port map(D => DATAIN_c(1), CLK => HCLK_c, E => N_84, Q =>
|
| 459 |
|
|
\HWDATA_int[1]_net_1\);
|
| 460 |
|
|
|
| 461 |
|
|
\HADDR_RNO_0[3]\ : MX2C
|
| 462 |
|
|
port map(A => ADDR_c_1, B => \HADDR_int[3]_net_1\, S =>
|
| 463 |
|
|
N_87, Y => \HADDR_7_i_0[3]\);
|
| 464 |
|
|
|
| 465 |
|
|
ahb_busy_RNO : OR2A
|
| 466 |
|
|
port map(A => N_89, B => N_163, Y => ahb_busy_6);
|
| 467 |
|
|
|
| 468 |
|
|
\HADDR_RNO_0[2]\ : MX2C
|
| 469 |
|
|
port map(A => ADDR_c_0, B => \HADDR_int[2]_net_1\, S =>
|
| 470 |
|
|
N_87, Y => \HADDR_7_i_0[2]\);
|
| 471 |
|
|
|
| 472 |
|
|
\ahb_fsm_current_state_RNI298U8[1]\ : NOR3A
|
| 473 |
|
|
port map(A => \ahb_fsm_current_state[1]_net_1\, B => N_340,
|
| 474 |
|
|
C => N_N_3_mux, Y =>
|
| 475 |
|
|
un1_ahb_fsm_current_state_7_i_0_a4_0_1);
|
| 476 |
|
|
|
| 477 |
|
|
\HADDR_RNO[29]\ : NOR2A
|
| 478 |
|
|
port map(A => N_N_5_mux, B => \HADDR_7_i_0[29]\, Y => N_582);
|
| 479 |
|
|
|
| 480 |
|
|
HWRITE_RNO_1 : AO1
|
| 481 |
|
|
port map(A => \ahb_fsm_current_state[1]_net_1\, B => N_340,
|
| 482 |
|
|
C => un1_ahb_fsm_current_state_8_0_1, Y =>
|
| 483 |
|
|
un1_ahb_fsm_current_state_8_0_2);
|
| 484 |
|
|
|
| 485 |
|
|
\HADDR_int[28]\ : DFN1E0
|
| 486 |
|
|
port map(D => ADDR_c_26, CLK => HCLK_c, E => N_86, Q =>
|
| 487 |
|
|
\HADDR_int[28]_net_1\);
|
| 488 |
|
|
|
| 489 |
|
|
\ahb_fsm_current_state[3]\ : DFN1C0
|
| 490 |
|
|
port map(D => \ahb_fsm_current_state_ns[3]\, CLK => HCLK_c,
|
| 491 |
|
|
CLR => HRESETn_c, Q => \ahb_fsm_current_state[3]_net_1\);
|
| 492 |
|
|
|
| 493 |
|
|
\ahb_fsm_current_state_RNIJ4RV1[3]\ : OR3
|
| 494 |
|
|
port map(A => un1_ahb_fsm_current_state_12_i_0, B =>
|
| 495 |
|
|
\ahb_fsm_current_state[3]_net_1\, C => N_197, Y =>
|
| 496 |
|
|
un1_ahb_fsm_current_state_12_i_2);
|
| 497 |
|
|
|
| 498 |
|
|
\HADDR_RNO[31]\ : NOR2A
|
| 499 |
|
|
port map(A => N_N_5_mux, B => \HADDR_7_i_0[31]\, Y => N_580);
|
| 500 |
|
|
|
| 501 |
|
|
\HADDR[3]\ : DFN1E0C0
|
| 502 |
|
|
port map(D => N_76, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 503 |
|
|
\ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q =>
|
| 504 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_1);
|
| 505 |
|
|
|
| 506 |
|
|
\HADDR[24]\ : DFN1E0C0
|
| 507 |
|
|
port map(D => N_34, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 508 |
|
|
\ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q =>
|
| 509 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_22);
|
| 510 |
|
|
|
| 511 |
|
|
N_m1_e : NOR2B
|
| 512 |
|
|
port map(A => PREVDATASLAVEREADY_iv_i_0_i_o4_1, B => N_398,
|
| 513 |
|
|
Y => N_N_3_mux);
|
| 514 |
|
|
|
| 515 |
|
|
HWRITE_RNO_3 : OR3
|
| 516 |
|
|
port map(A => \ahb_fsm_current_state[5]_net_1\, B =>
|
| 517 |
|
|
\ahb_fsm_current_state[4]_net_1\, C =>
|
| 518 |
|
|
\ahb_fsm_current_state[2]_net_1\, Y =>
|
| 519 |
|
|
un1_ahb_fsm_current_state_8_0_1);
|
| 520 |
|
|
|
| 521 |
|
|
\HADDR_RNO_0[28]\ : MX2C
|
| 522 |
|
|
port map(A => ADDR_c_26, B => \HADDR_int[28]_net_1\, S =>
|
| 523 |
|
|
N_87, Y => \HADDR_7_i_0[28]\);
|
| 524 |
|
|
|
| 525 |
|
|
\HWDATA_int[7]\ : DFN1E0
|
| 526 |
|
|
port map(D => DATAIN_c(7), CLK => HCLK_c, E => N_84, Q =>
|
| 527 |
|
|
\HWDATA_int[7]_net_1\);
|
| 528 |
|
|
|
| 529 |
|
|
\HWDATA_int[3]\ : DFN1E0
|
| 530 |
|
|
port map(D => DATAIN_c(3), CLK => HCLK_c, E => N_84, Q =>
|
| 531 |
|
|
\HWDATA_int[3]_net_1\);
|
| 532 |
|
|
|
| 533 |
|
|
\ahb_fsm_current_state_RNO[2]\ : NOR3B
|
| 534 |
|
|
port map(A => LREAD_c, B =>
|
| 535 |
|
|
\ahb_fsm_current_state[6]_net_1\, C => LWRITE_c, Y =>
|
| 536 |
|
|
\ahb_fsm_current_state_ns[4]\);
|
| 537 |
|
|
|
| 538 |
|
|
\ahb_fsm_current_state_RNI2H6Q_0[1]\ : NOR2A
|
| 539 |
|
|
port map(A => \ahb_fsm_current_state[1]_net_1\, B => N_398,
|
| 540 |
|
|
Y => un1_ahb_fsm_current_state_12_i_0_a1_0);
|
| 541 |
|
|
|
| 542 |
|
|
\HADDR_RNO[3]\ : NOR2A
|
| 543 |
|
|
port map(A => N_N_5_mux, B => \HADDR_7_i_0[3]\, Y => N_76);
|
| 544 |
|
|
|
| 545 |
|
|
\ahb_fsm_current_state_RNI371J[4]\ : OR2
|
| 546 |
|
|
port map(A => \ahb_fsm_current_state[1]_net_1\, B =>
|
| 547 |
|
|
\ahb_fsm_current_state[4]_net_1\, Y => N_87);
|
| 548 |
|
|
|
| 549 |
|
|
HWRITE_RNO : OR3
|
| 550 |
|
|
port map(A => \HWRITE_RNO_0\, B =>
|
| 551 |
|
|
un1_ahb_fsm_current_state_8_0_2, C => \HWRITE_RNO_2\, Y
|
| 552 |
|
|
=> un1_ahb_fsm_current_state_8);
|
| 553 |
|
|
|
| 554 |
|
|
\HADDR_RNO[27]\ : NOR2A
|
| 555 |
|
|
port map(A => N_N_5_mux, B => \HADDR_7_i_0[27]\, Y => N_583);
|
| 556 |
|
|
|
| 557 |
|
|
\HADDR_RNO[25]\ : NOR2A
|
| 558 |
|
|
port map(A => N_N_5_mux, B => \HADDR_7_i_0[25]\, Y => N_32);
|
| 559 |
|
|
|
| 560 |
|
|
\HWDATA[3]\ : DFN1E1C0
|
| 561 |
|
|
port map(D => \HWDATA_int[3]_net_1\, CLK => HCLK_c, CLR =>
|
| 562 |
|
|
HRESETn_c, E => HWDATA_1_sqmuxa, Q =>
|
| 563 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(3));
|
| 564 |
|
|
|
| 565 |
|
|
\HADDR[29]\ : DFN1E0C0
|
| 566 |
|
|
port map(D => N_582, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 567 |
|
|
\ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q =>
|
| 568 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_27);
|
| 569 |
|
|
|
| 570 |
|
|
\HADDR[25]\ : DFN1E0C0
|
| 571 |
|
|
port map(D => N_32, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 572 |
|
|
\ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q =>
|
| 573 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_23);
|
| 574 |
|
|
|
| 575 |
|
|
GND_i : GND
|
| 576 |
|
|
port map(Y => \GND\);
|
| 577 |
|
|
|
| 578 |
|
|
\ahb_fsm_current_state[5]\ : DFN1C0
|
| 579 |
|
|
port map(D => \ahb_fsm_current_state_RNO[5]_net_1\, CLK =>
|
| 580 |
|
|
HCLK_c, CLR => HRESETn_c, Q =>
|
| 581 |
|
|
\ahb_fsm_current_state[5]_net_1\);
|
| 582 |
|
|
|
| 583 |
|
|
\ahb_fsm_current_state_RNITLON[6]\ : OR3C
|
| 584 |
|
|
port map(A => \ahb_fsm_current_state[6]_net_1\, B =>
|
| 585 |
|
|
HRESETn_c, C => LWRITE_c, Y => N_84);
|
| 586 |
|
|
|
| 587 |
|
|
HWRITE_RNO_0 : NOR2B
|
| 588 |
|
|
port map(A => un1_ahb_fsm_current_state_8_0_0_a0_0, B =>
|
| 589 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_1, Y => \HWRITE_RNO_0\);
|
| 590 |
|
|
|
| 591 |
|
|
\ahb_fsm_current_state[4]\ : DFN1C0
|
| 592 |
|
|
port map(D => HWRITE_4, CLK => HCLK_c, CLR => HRESETn_c, Q
|
| 593 |
|
|
=> \ahb_fsm_current_state[4]_net_1\);
|
| 594 |
|
|
|
| 595 |
|
|
\HWDATA[5]\ : DFN1E1C0
|
| 596 |
|
|
port map(D => \HWDATA_int[5]_net_1\, CLK => HCLK_c, CLR =>
|
| 597 |
|
|
HRESETn_c, E => HWDATA_1_sqmuxa, Q =>
|
| 598 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(5));
|
| 599 |
|
|
|
| 600 |
|
|
\HADDR[27]\ : DFN1E0C0
|
| 601 |
|
|
port map(D => N_583, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 602 |
|
|
\ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q =>
|
| 603 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_25);
|
| 604 |
|
|
|
| 605 |
|
|
\HADDR_int[3]\ : DFN1E0
|
| 606 |
|
|
port map(D => ADDR_c_1, CLK => HCLK_c, E => N_86, Q =>
|
| 607 |
|
|
\HADDR_int[3]_net_1\);
|
| 608 |
|
|
|
| 609 |
|
|
\HADDR_int[2]\ : DFN1E0
|
| 610 |
|
|
port map(D => ADDR_c_0, CLK => HCLK_c, E => N_86, Q =>
|
| 611 |
|
|
\HADDR_int[2]_net_1\);
|
| 612 |
|
|
|
| 613 |
|
|
\HADDR[26]\ : DFN1E0C0
|
| 614 |
|
|
port map(D => N_30, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 615 |
|
|
\ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q =>
|
| 616 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_24);
|
| 617 |
|
|
|
| 618 |
|
|
\ahb_fsm_current_state_RNIPHIFL[5]\ : AO1
|
| 619 |
|
|
port map(A => \ahb_fsm_current_state[4]_net_1\, B => N_163,
|
| 620 |
|
|
C => \ahb_fsm_current_state[5]_net_1\, Y => HWRITE_4);
|
| 621 |
|
|
|
| 622 |
|
|
\ahb_fsm_current_state_RNIJ31O4[0]\ : OR2A
|
| 623 |
|
|
port map(A => \ahb_fsm_current_state[0]_net_1\, B => N_340,
|
| 624 |
|
|
Y => DATAOUT_0_sqmuxa_i_0);
|
| 625 |
|
|
|
| 626 |
|
|
DATAOUT_0_sqmuxa_i_0_a0 : NOR2B
|
| 627 |
|
|
port map(A => N_398, B => PREVDATASLAVEREADY_iv_i_0_i_o4_0,
|
| 628 |
|
|
Y => \DATAOUT_0_sqmuxa_i_0_a0\);
|
| 629 |
|
|
|
| 630 |
|
|
\HADDR[28]\ : DFN1E0C0
|
| 631 |
|
|
port map(D => N_26, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 632 |
|
|
\ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q =>
|
| 633 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_26);
|
| 634 |
|
|
|
| 635 |
|
|
\ahb_fsm_current_state_RNINQNML[4]\ : NOR3A
|
| 636 |
|
|
port map(A => HWDATA_1_sqmuxa_0_a5_0_a4_2_0, B =>
|
| 637 |
|
|
\DATAOUT_0_sqmuxa_i_0_a0\, C => N_N_3_mux, Y =>
|
| 638 |
|
|
HWDATA_1_sqmuxa);
|
| 639 |
|
|
|
| 640 |
|
|
\DATAOUT[3]\ : DFN1E0C0
|
| 641 |
|
|
port map(D => AHBMASTER_FIC_0_AHBmaster_HRDATA(3), CLK =>
|
| 642 |
|
|
HCLK_c, CLR => HRESETn_c, E => N_355, Q => DATAOUT_c(3));
|
| 643 |
|
|
|
| 644 |
|
|
\HWDATA[7]\ : DFN1E1C0
|
| 645 |
|
|
port map(D => \HWDATA_int[7]_net_1\, CLK => HCLK_c, CLR =>
|
| 646 |
|
|
HRESETn_c, E => HWDATA_1_sqmuxa, Q =>
|
| 647 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(7));
|
| 648 |
|
|
|
| 649 |
|
|
\HADDR_RNO[26]\ : NOR2A
|
| 650 |
|
|
port map(A => N_N_5_mux, B => \HADDR_7_i_0[26]\, Y => N_30);
|
| 651 |
|
|
|
| 652 |
|
|
\ahb_fsm_current_state_RNIMB80M[0]\ : NOR2
|
| 653 |
|
|
port map(A => \ahb_fsm_current_state[0]_net_1\, B =>
|
| 654 |
|
|
HWDATA_1_sqmuxa, Y => N_N_5_mux);
|
| 655 |
|
|
|
| 656 |
|
|
\DATAOUT[7]\ : DFN1E0C0
|
| 657 |
|
|
port map(D => AHBMASTER_FIC_0_AHBmaster_HRDATA(7), CLK =>
|
| 658 |
|
|
HCLK_c, CLR => HRESETn_c, E => N_355, Q => DATAOUT_c(7));
|
| 659 |
|
|
|
| 660 |
|
|
\HWDATA[1]\ : DFN1E1C0
|
| 661 |
|
|
port map(D => \HWDATA_int[1]_net_1\, CLK => HCLK_c, CLR =>
|
| 662 |
|
|
HRESETn_c, E => HWDATA_1_sqmuxa, Q =>
|
| 663 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(1));
|
| 664 |
|
|
|
| 665 |
|
|
\HADDR_RNO_0[24]\ : MX2C
|
| 666 |
|
|
port map(A => ADDR_c_22, B => \HADDR_int[24]_net_1\, S =>
|
| 667 |
|
|
N_87, Y => \HADDR_7_i_0[24]\);
|
| 668 |
|
|
|
| 669 |
|
|
\HADDR_int[30]\ : DFN1E0
|
| 670 |
|
|
port map(D => ADDR_c_28, CLK => HCLK_c, E => N_86, Q =>
|
| 671 |
|
|
\HADDR_int[30]_net_1\);
|
| 672 |
|
|
|
| 673 |
|
|
\HWDATA[6]\ : DFN1E1C0
|
| 674 |
|
|
port map(D => \HWDATA_int[6]_net_1\, CLK => HCLK_c, CLR =>
|
| 675 |
|
|
HRESETn_c, E => HWDATA_1_sqmuxa, Q =>
|
| 676 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(6));
|
| 677 |
|
|
|
| 678 |
|
|
\ahb_fsm_current_state_RNO_0[6]\ : OR3
|
| 679 |
|
|
port map(A => N_125, B => un1_ahb_fsm_current_state_12_i_0,
|
| 680 |
|
|
C => N_87, Y => \ahb_fsm_current_state_ns_i_0_2[0]\);
|
| 681 |
|
|
|
| 682 |
|
|
\HTRANS_1[1]\ : DFN1E0C0
|
| 683 |
|
|
port map(D => N_N_5_mux, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 684 |
|
|
=> N_369, Q => AHBMASTER_FIC_0_AHBmaster_HTRANS_0);
|
| 685 |
|
|
|
| 686 |
|
|
\HADDR_RNO[4]\ : NOR3
|
| 687 |
|
|
port map(A => \HADDR_7_i_0[4]\, B => N_188, C =>
|
| 688 |
|
|
HWDATA_1_sqmuxa, Y => N_74);
|
| 689 |
|
|
|
| 690 |
|
|
\DATAOUT[2]\ : DFN1E0C0
|
| 691 |
|
|
port map(D => AHBMASTER_FIC_0_AHBmaster_HRDATA(2), CLK =>
|
| 692 |
|
|
HCLK_c, CLR => HRESETn_c, E => N_355, Q => DATAOUT_c(2));
|
| 693 |
|
|
|
| 694 |
|
|
\ahb_fsm_current_state_RNI591J[2]\ : OR2
|
| 695 |
|
|
port map(A => \ahb_fsm_current_state[5]_net_1\, B =>
|
| 696 |
|
|
\ahb_fsm_current_state[2]_net_1\, Y =>
|
| 697 |
|
|
un1_ahb_fsm_current_state_12_i_0);
|
| 698 |
|
|
|
| 699 |
|
|
\ahb_fsm_current_state_ns_i_0_o3_0[0]\ : OR2
|
| 700 |
|
|
port map(A => LREAD_c, B => LWRITE_c, Y => N_91);
|
| 701 |
|
|
|
| 702 |
|
|
\HWDATA[2]\ : DFN1E1C0
|
| 703 |
|
|
port map(D => \HWDATA_int[2]_net_1\, CLK => HCLK_c, CLR =>
|
| 704 |
|
|
HRESETn_c, E => HWDATA_1_sqmuxa, Q =>
|
| 705 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(2));
|
| 706 |
|
|
|
| 707 |
|
|
\HADDR_RNO[28]\ : NOR2A
|
| 708 |
|
|
port map(A => N_N_5_mux, B => \HADDR_7_i_0[28]\, Y => N_26);
|
| 709 |
|
|
|
| 710 |
|
|
\DATAOUT[5]\ : DFN1E0C0
|
| 711 |
|
|
port map(D => AHBMASTER_FIC_0_AHBmaster_HRDATA(5), CLK =>
|
| 712 |
|
|
HCLK_c, CLR => HRESETn_c, E => N_355, Q => DATAOUT_c(5));
|
| 713 |
|
|
|
| 714 |
|
|
ahb_busy : DFN1E0C0
|
| 715 |
|
|
port map(D => ahb_busy_6, CLK => HCLK_c, CLR => HRESETn_c,
|
| 716 |
|
|
E => N_379, Q => ahb_busy_c);
|
| 717 |
|
|
|
| 718 |
|
|
HWRITE_RNO_2 : NOR2B
|
| 719 |
|
|
port map(A => un1_ahb_fsm_current_state_8_0_0_a0_0, B =>
|
| 720 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_0, Y => \HWRITE_RNO_2\);
|
| 721 |
|
|
|
| 722 |
|
|
\HADDR_int[24]\ : DFN1E0
|
| 723 |
|
|
port map(D => ADDR_c_22, CLK => HCLK_c, E => N_86, Q =>
|
| 724 |
|
|
\HADDR_int[24]_net_1\);
|
| 725 |
|
|
|
| 726 |
|
|
\HADDR_RNO_0[26]\ : MX2C
|
| 727 |
|
|
port map(A => ADDR_c_24, B => \HADDR_int[26]_net_1\, S =>
|
| 728 |
|
|
N_87, Y => \HADDR_7_i_0[26]\);
|
| 729 |
|
|
|
| 730 |
|
|
\HADDR_RNO[30]\ : NOR2A
|
| 731 |
|
|
port map(A => N_N_5_mux, B => \HADDR_7_i_0[30]\, Y => N_581);
|
| 732 |
|
|
|
| 733 |
|
|
\ahb_fsm_current_state_RNIC7931[6]\ : NOR2A
|
| 734 |
|
|
port map(A => \ahb_fsm_current_state[6]_net_1\, B => N_91,
|
| 735 |
|
|
Y => N_197);
|
| 736 |
|
|
|
| 737 |
|
|
ahb_busy_RNO_0 : OR2
|
| 738 |
|
|
port map(A => N_197, B => N_129, Y => N_379);
|
| 739 |
|
|
|
| 740 |
|
|
\HADDR_RNO_0[30]\ : MX2C
|
| 741 |
|
|
port map(A => ADDR_c_28, B => \HADDR_int[30]_net_1\, S =>
|
| 742 |
|
|
N_87, Y => \HADDR_7_i_0[30]\);
|
| 743 |
|
|
|
| 744 |
|
|
\HADDR[2]\ : DFN1E0C0
|
| 745 |
|
|
port map(D => N_78, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 746 |
|
|
\ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q =>
|
| 747 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_0);
|
| 748 |
|
|
|
| 749 |
|
|
\HWDATA_int[6]\ : DFN1E0
|
| 750 |
|
|
port map(D => DATAIN_c(6), CLK => HCLK_c, E => N_84, Q =>
|
| 751 |
|
|
\HWDATA_int[6]_net_1\);
|
| 752 |
|
|
|
| 753 |
|
|
\HWDATA_int[4]\ : DFN1E0
|
| 754 |
|
|
port map(D => DATAIN_c(4), CLK => HCLK_c, E => N_84, Q =>
|
| 755 |
|
|
\HWDATA_int[4]_net_1\);
|
| 756 |
|
|
|
| 757 |
|
|
\HADDR_int[4]\ : DFN1E0
|
| 758 |
|
|
port map(D => ADDR_c_2, CLK => HCLK_c, E => N_86, Q =>
|
| 759 |
|
|
\HADDR_int[4]_net_1\);
|
| 760 |
|
|
|
| 761 |
|
|
\ahb_fsm_current_state_RNIJMNML[0]\ : OR3
|
| 762 |
|
|
port map(A => N_N_3_mux, B => DATAOUT_0_sqmuxa_i_0, C =>
|
| 763 |
|
|
\DATAOUT_0_sqmuxa_i_0_a0\, Y => N_355);
|
| 764 |
|
|
|
| 765 |
|
|
\HWDATA_int[2]\ : DFN1E0
|
| 766 |
|
|
port map(D => DATAIN_c(2), CLK => HCLK_c, E => N_84, Q =>
|
| 767 |
|
|
\HWDATA_int[2]_net_1\);
|
| 768 |
|
|
|
| 769 |
|
|
|
| 770 |
|
|
end DEF_ARCH;
|
| 771 |
|
|
|
| 772 |
|
|
library ieee;
|
| 773 |
|
|
use ieee.std_logic_1164.all;
|
| 774 |
|
|
library proasic3;
|
| 775 |
|
|
use proasic3.all;
|
| 776 |
|
|
|
| 777 |
|
|
entity COReAPB_l is
|
| 778 |
|
|
|
| 779 |
|
|
port( CoreAHB2APB_0_APBmaster_PSELx : in std_logic_vector(15 downto 1);
|
| 780 |
|
|
PRDATA_0_sqmuxa_0_a2_12 : out std_logic;
|
| 781 |
|
|
CoreAPB_0_APBmslave0_PSELx : in std_logic;
|
| 782 |
|
|
PRDATA_0_sqmuxa_0_a2_13 : out std_logic
|
| 783 |
|
|
);
|
| 784 |
|
|
|
| 785 |
|
|
end COReAPB_l;
|
| 786 |
|
|
|
| 787 |
|
|
architecture DEF_ARCH of COReAPB_l is
|
| 788 |
|
|
|
| 789 |
|
|
component NOR3A
|
| 790 |
|
|
port( A : in std_logic := 'U';
|
| 791 |
|
|
B : in std_logic := 'U';
|
| 792 |
|
|
C : in std_logic := 'U';
|
| 793 |
|
|
Y : out std_logic
|
| 794 |
|
|
);
|
| 795 |
|
|
end component;
|
| 796 |
|
|
|
| 797 |
|
|
component NOR2
|
| 798 |
|
|
port( A : in std_logic := 'U';
|
| 799 |
|
|
B : in std_logic := 'U';
|
| 800 |
|
|
Y : out std_logic
|
| 801 |
|
|
);
|
| 802 |
|
|
end component;
|
| 803 |
|
|
|
| 804 |
|
|
component NOR3C
|
| 805 |
|
|
port( A : in std_logic := 'U';
|
| 806 |
|
|
B : in std_logic := 'U';
|
| 807 |
|
|
C : in std_logic := 'U';
|
| 808 |
|
|
Y : out std_logic
|
| 809 |
|
|
);
|
| 810 |
|
|
end component;
|
| 811 |
|
|
|
| 812 |
|
|
component VCC
|
| 813 |
|
|
port( Y : out std_logic
|
| 814 |
|
|
);
|
| 815 |
|
|
end component;
|
| 816 |
|
|
|
| 817 |
|
|
component GND
|
| 818 |
|
|
port( Y : out std_logic
|
| 819 |
|
|
);
|
| 820 |
|
|
end component;
|
| 821 |
|
|
|
| 822 |
|
|
component NOR3
|
| 823 |
|
|
port( A : in std_logic := 'U';
|
| 824 |
|
|
B : in std_logic := 'U';
|
| 825 |
|
|
C : in std_logic := 'U';
|
| 826 |
|
|
Y : out std_logic
|
| 827 |
|
|
);
|
| 828 |
|
|
end component;
|
| 829 |
|
|
|
| 830 |
|
|
signal \PRDATA_0_sqmuxa_0_a2_7\, \PRDATA_0_sqmuxa_0_a2_10\,
|
| 831 |
|
|
\PRDATA_0_sqmuxa_0_a2_2\, \PRDATA_0_sqmuxa_0_a2_1\,
|
| 832 |
|
|
\PRDATA_0_sqmuxa_0_a2_9\, \PRDATA_0_sqmuxa_0_a2_6\,
|
| 833 |
|
|
\PRDATA_0_sqmuxa_0_a2_4\, \GND\, \VCC\ : std_logic;
|
| 834 |
|
|
|
| 835 |
|
|
begin
|
| 836 |
|
|
|
| 837 |
|
|
|
| 838 |
|
|
PRDATA_0_sqmuxa_0_a2_10 : NOR3A
|
| 839 |
|
|
port map(A => \PRDATA_0_sqmuxa_0_a2_6\, B =>
|
| 840 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(3), C =>
|
| 841 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(2), Y =>
|
| 842 |
|
|
\PRDATA_0_sqmuxa_0_a2_10\);
|
| 843 |
|
|
|
| 844 |
|
|
PRDATA_0_sqmuxa_0_a2_9 : NOR3A
|
| 845 |
|
|
port map(A => \PRDATA_0_sqmuxa_0_a2_4\, B =>
|
| 846 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(5), C =>
|
| 847 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(9), Y =>
|
| 848 |
|
|
\PRDATA_0_sqmuxa_0_a2_9\);
|
| 849 |
|
|
|
| 850 |
|
|
PRDATA_0_sqmuxa_0_a2_6 : NOR2
|
| 851 |
|
|
port map(A => CoreAHB2APB_0_APBmaster_PSELx(1), B =>
|
| 852 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(12), Y =>
|
| 853 |
|
|
\PRDATA_0_sqmuxa_0_a2_6\);
|
| 854 |
|
|
|
| 855 |
|
|
PRDATA_0_sqmuxa_0_a2_2 : NOR2
|
| 856 |
|
|
port map(A => CoreAHB2APB_0_APBmaster_PSELx(11), B =>
|
| 857 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(7), Y =>
|
| 858 |
|
|
\PRDATA_0_sqmuxa_0_a2_2\);
|
| 859 |
|
|
|
| 860 |
|
|
\PRDATA_0_sqmuxa_0_a2_12\ : NOR3C
|
| 861 |
|
|
port map(A => \PRDATA_0_sqmuxa_0_a2_2\, B =>
|
| 862 |
|
|
\PRDATA_0_sqmuxa_0_a2_1\, C => \PRDATA_0_sqmuxa_0_a2_9\,
|
| 863 |
|
|
Y => PRDATA_0_sqmuxa_0_a2_12);
|
| 864 |
|
|
|
| 865 |
|
|
PRDATA_0_sqmuxa_0_a2_1 : NOR2
|
| 866 |
|
|
port map(A => CoreAHB2APB_0_APBmaster_PSELx(15), B =>
|
| 867 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(8), Y =>
|
| 868 |
|
|
\PRDATA_0_sqmuxa_0_a2_1\);
|
| 869 |
|
|
|
| 870 |
|
|
VCC_i : VCC
|
| 871 |
|
|
port map(Y => \VCC\);
|
| 872 |
|
|
|
| 873 |
|
|
\PRDATA_0_sqmuxa_0_a2_13\ : NOR3C
|
| 874 |
|
|
port map(A => \PRDATA_0_sqmuxa_0_a2_7\, B =>
|
| 875 |
|
|
CoreAPB_0_APBmslave0_PSELx, C =>
|
| 876 |
|
|
\PRDATA_0_sqmuxa_0_a2_10\, Y => PRDATA_0_sqmuxa_0_a2_13);
|
| 877 |
|
|
|
| 878 |
|
|
GND_i : GND
|
| 879 |
|
|
port map(Y => \GND\);
|
| 880 |
|
|
|
| 881 |
|
|
PRDATA_0_sqmuxa_0_a2_7 : NOR3
|
| 882 |
|
|
port map(A => CoreAHB2APB_0_APBmaster_PSELx(13), B =>
|
| 883 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(10), C =>
|
| 884 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(14), Y =>
|
| 885 |
|
|
\PRDATA_0_sqmuxa_0_a2_7\);
|
| 886 |
|
|
|
| 887 |
|
|
PRDATA_0_sqmuxa_0_a2_4 : NOR2
|
| 888 |
|
|
port map(A => CoreAHB2APB_0_APBmaster_PSELx(6), B =>
|
| 889 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(4), Y =>
|
| 890 |
|
|
\PRDATA_0_sqmuxa_0_a2_4\);
|
| 891 |
|
|
|
| 892 |
|
|
|
| 893 |
|
|
end DEF_ARCH;
|
| 894 |
|
|
|
| 895 |
|
|
library ieee;
|
| 896 |
|
|
use ieee.std_logic_1164.all;
|
| 897 |
|
|
library proasic3;
|
| 898 |
|
|
use proasic3.all;
|
| 899 |
|
|
|
| 900 |
|
|
entity COREAPB is
|
| 901 |
|
|
|
| 902 |
|
|
port( CoreAHB2APB_0_APBmaster_PSELx : in std_logic_vector(15 downto 1);
|
| 903 |
|
|
PRDATA_0_sqmuxa_0_a2_13 : out std_logic;
|
| 904 |
|
|
CoreAPB_0_APBmslave0_PSELx : in std_logic;
|
| 905 |
|
|
PRDATA_0_sqmuxa_0_a2_12 : out std_logic
|
| 906 |
|
|
);
|
| 907 |
|
|
|
| 908 |
|
|
end COREAPB;
|
| 909 |
|
|
|
| 910 |
|
|
architecture DEF_ARCH of COREAPB is
|
| 911 |
|
|
|
| 912 |
|
|
component COReAPB_l
|
| 913 |
|
|
port( CoreAHB2APB_0_APBmaster_PSELx : in std_logic_vector(15 downto 1) := (others => 'U');
|
| 914 |
|
|
PRDATA_0_sqmuxa_0_a2_12 : out std_logic;
|
| 915 |
|
|
CoreAPB_0_APBmslave0_PSELx : in std_logic := 'U';
|
| 916 |
|
|
PRDATA_0_sqmuxa_0_a2_13 : out std_logic
|
| 917 |
|
|
);
|
| 918 |
|
|
end component;
|
| 919 |
|
|
|
| 920 |
|
|
component VCC
|
| 921 |
|
|
port( Y : out std_logic
|
| 922 |
|
|
);
|
| 923 |
|
|
end component;
|
| 924 |
|
|
|
| 925 |
|
|
component GND
|
| 926 |
|
|
port( Y : out std_logic
|
| 927 |
|
|
);
|
| 928 |
|
|
end component;
|
| 929 |
|
|
|
| 930 |
|
|
signal \GND\, \VCC\ : std_logic;
|
| 931 |
|
|
|
| 932 |
|
|
for all : COReAPB_l
|
| 933 |
|
|
Use entity work.COReAPB_l(DEF_ARCH);
|
| 934 |
|
|
begin
|
| 935 |
|
|
|
| 936 |
|
|
|
| 937 |
|
|
COREAPB_oi0 : COReAPB_l
|
| 938 |
|
|
port map(CoreAHB2APB_0_APBmaster_PSELx(15) =>
|
| 939 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(15),
|
| 940 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(14) =>
|
| 941 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(14),
|
| 942 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(13) =>
|
| 943 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(13),
|
| 944 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(12) =>
|
| 945 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(12),
|
| 946 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(11) =>
|
| 947 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(11),
|
| 948 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(10) =>
|
| 949 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(10),
|
| 950 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(9) =>
|
| 951 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(9),
|
| 952 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(8) =>
|
| 953 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(8),
|
| 954 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(7) =>
|
| 955 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(7),
|
| 956 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(6) =>
|
| 957 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(6),
|
| 958 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(5) =>
|
| 959 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(5),
|
| 960 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(4) =>
|
| 961 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(4),
|
| 962 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(3) =>
|
| 963 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(3),
|
| 964 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(2) =>
|
| 965 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(2),
|
| 966 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(1) =>
|
| 967 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(1), PRDATA_0_sqmuxa_0_a2_12
|
| 968 |
|
|
=> PRDATA_0_sqmuxa_0_a2_12, CoreAPB_0_APBmslave0_PSELx
|
| 969 |
|
|
=> CoreAPB_0_APBmslave0_PSELx, PRDATA_0_sqmuxa_0_a2_13
|
| 970 |
|
|
=> PRDATA_0_sqmuxa_0_a2_13);
|
| 971 |
|
|
|
| 972 |
|
|
VCC_i : VCC
|
| 973 |
|
|
port map(Y => \VCC\);
|
| 974 |
|
|
|
| 975 |
|
|
GND_i : GND
|
| 976 |
|
|
port map(Y => \GND\);
|
| 977 |
|
|
|
| 978 |
|
|
|
| 979 |
|
|
end DEF_ARCH;
|
| 980 |
|
|
|
| 981 |
|
|
library ieee;
|
| 982 |
|
|
use ieee.std_logic_1164.all;
|
| 983 |
|
|
library proasic3;
|
| 984 |
|
|
use proasic3.all;
|
| 985 |
|
|
|
| 986 |
|
|
entity COREAHBLITE_SLAVEARBITER_0 is
|
| 987 |
|
|
|
| 988 |
|
|
port( arbRegSMCurrentState_i_0_3 : out std_logic;
|
| 989 |
|
|
arbRegSMCurrentState_i_0_0 : out std_logic;
|
| 990 |
|
|
masterAddrInProg : out std_logic_vector(3 downto 1);
|
| 991 |
|
|
masterAddrInProg_i_1_0 : out std_logic;
|
| 992 |
|
|
arbRegSMCurrentState_RNICAHF7_0 : out std_logic;
|
| 993 |
|
|
xhdl1221_0 : in std_logic;
|
| 994 |
|
|
HRESETn_c : in std_logic;
|
| 995 |
|
|
HCLK_c : in std_logic;
|
| 996 |
|
|
N_300 : in std_logic;
|
| 997 |
|
|
N_18 : out std_logic;
|
| 998 |
|
|
N_326 : in std_logic;
|
| 999 |
|
|
N_135 : out std_logic;
|
| 1000 |
|
|
N_301 : in std_logic;
|
| 1001 |
|
|
N_20 : out std_logic;
|
| 1002 |
|
|
N_302 : in std_logic;
|
| 1003 |
|
|
N_22 : out std_logic;
|
| 1004 |
|
|
N_323 : in std_logic;
|
| 1005 |
|
|
N_120 : out std_logic;
|
| 1006 |
|
|
N_322 : in std_logic;
|
| 1007 |
|
|
N_324 : in std_logic;
|
| 1008 |
|
|
N_325 : in std_logic;
|
| 1009 |
|
|
N_124 : out std_logic;
|
| 1010 |
|
|
HADDR_26_0_a3_i_a0_3 : in std_logic;
|
| 1011 |
|
|
N_128 : out std_logic;
|
| 1012 |
|
|
un4_m5_0_a3_2 : in std_logic;
|
| 1013 |
|
|
HADDR_24_0_a3_i_out : out std_logic;
|
| 1014 |
|
|
HTRANS_0_a3_i_a2_2_0 : in std_logic;
|
| 1015 |
|
|
HTRANS_0_a3_i_a2_0_a0_1 : in std_logic;
|
| 1016 |
|
|
N_363 : out std_logic;
|
| 1017 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx : out std_logic;
|
| 1018 |
|
|
un1_N_11_mux_i_5_a1_1 : in std_logic;
|
| 1019 |
|
|
N_403 : in std_logic;
|
| 1020 |
|
|
N_367 : out std_logic;
|
| 1021 |
|
|
un1_m1_e_0_0 : in std_logic;
|
| 1022 |
|
|
HADDR_m5_0_m3 : in std_logic;
|
| 1023 |
|
|
HSEL_1_0_0_a1_0 : in std_logic;
|
| 1024 |
|
|
HSEL_1_0_0_a0_0 : in std_logic;
|
| 1025 |
|
|
N_254 : in std_logic;
|
| 1026 |
|
|
N_263 : out std_logic;
|
| 1027 |
|
|
N_171 : out std_logic;
|
| 1028 |
|
|
N_330 : in std_logic;
|
| 1029 |
|
|
HSEL_1_0_0_1_0 : in std_logic;
|
| 1030 |
|
|
N_397 : in std_logic;
|
| 1031 |
|
|
N_327 : in std_logic;
|
| 1032 |
|
|
un4_m5_0_a3_1 : in std_logic;
|
| 1033 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY : in std_logic
|
| 1034 |
|
|
);
|
| 1035 |
|
|
|
| 1036 |
|
|
end COREAHBLITE_SLAVEARBITER_0;
|
| 1037 |
|
|
|
| 1038 |
|
|
architecture DEF_ARCH of COREAHBLITE_SLAVEARBITER_0 is
|
| 1039 |
|
|
|
| 1040 |
|
|
component NOR2B
|
| 1041 |
|
|
port( A : in std_logic := 'U';
|
| 1042 |
|
|
B : in std_logic := 'U';
|
| 1043 |
|
|
Y : out std_logic
|
| 1044 |
|
|
);
|
| 1045 |
|
|
end component;
|
| 1046 |
|
|
|
| 1047 |
|
|
component DFN1P0
|
| 1048 |
|
|
port( D : in std_logic := 'U';
|
| 1049 |
|
|
CLK : in std_logic := 'U';
|
| 1050 |
|
|
PRE : in std_logic := 'U';
|
| 1051 |
|
|
Q : out std_logic
|
| 1052 |
|
|
);
|
| 1053 |
|
|
end component;
|
| 1054 |
|
|
|
| 1055 |
|
|
component OA1C
|
| 1056 |
|
|
port( A : in std_logic := 'U';
|
| 1057 |
|
|
B : in std_logic := 'U';
|
| 1058 |
|
|
C : in std_logic := 'U';
|
| 1059 |
|
|
Y : out std_logic
|
| 1060 |
|
|
);
|
| 1061 |
|
|
end component;
|
| 1062 |
|
|
|
| 1063 |
|
|
component AO1A
|
| 1064 |
|
|
port( A : in std_logic := 'U';
|
| 1065 |
|
|
B : in std_logic := 'U';
|
| 1066 |
|
|
C : in std_logic := 'U';
|
| 1067 |
|
|
Y : out std_logic
|
| 1068 |
|
|
);
|
| 1069 |
|
|
end component;
|
| 1070 |
|
|
|
| 1071 |
|
|
component NOR3B
|
| 1072 |
|
|
port( A : in std_logic := 'U';
|
| 1073 |
|
|
B : in std_logic := 'U';
|
| 1074 |
|
|
C : in std_logic := 'U';
|
| 1075 |
|
|
Y : out std_logic
|
| 1076 |
|
|
);
|
| 1077 |
|
|
end component;
|
| 1078 |
|
|
|
| 1079 |
|
|
component DFN1C0
|
| 1080 |
|
|
port( D : in std_logic := 'U';
|
| 1081 |
|
|
CLK : in std_logic := 'U';
|
| 1082 |
|
|
CLR : in std_logic := 'U';
|
| 1083 |
|
|
Q : out std_logic
|
| 1084 |
|
|
);
|
| 1085 |
|
|
end component;
|
| 1086 |
|
|
|
| 1087 |
|
|
component NOR3C
|
| 1088 |
|
|
port( A : in std_logic := 'U';
|
| 1089 |
|
|
B : in std_logic := 'U';
|
| 1090 |
|
|
C : in std_logic := 'U';
|
| 1091 |
|
|
Y : out std_logic
|
| 1092 |
|
|
);
|
| 1093 |
|
|
end component;
|
| 1094 |
|
|
|
| 1095 |
|
|
component NOR2
|
| 1096 |
|
|
port( A : in std_logic := 'U';
|
| 1097 |
|
|
B : in std_logic := 'U';
|
| 1098 |
|
|
Y : out std_logic
|
| 1099 |
|
|
);
|
| 1100 |
|
|
end component;
|
| 1101 |
|
|
|
| 1102 |
|
|
component OR2A
|
| 1103 |
|
|
port( A : in std_logic := 'U';
|
| 1104 |
|
|
B : in std_logic := 'U';
|
| 1105 |
|
|
Y : out std_logic
|
| 1106 |
|
|
);
|
| 1107 |
|
|
end component;
|
| 1108 |
|
|
|
| 1109 |
|
|
component NOR3A
|
| 1110 |
|
|
port( A : in std_logic := 'U';
|
| 1111 |
|
|
B : in std_logic := 'U';
|
| 1112 |
|
|
C : in std_logic := 'U';
|
| 1113 |
|
|
Y : out std_logic
|
| 1114 |
|
|
);
|
| 1115 |
|
|
end component;
|
| 1116 |
|
|
|
| 1117 |
|
|
component NOR2A
|
| 1118 |
|
|
port( A : in std_logic := 'U';
|
| 1119 |
|
|
B : in std_logic := 'U';
|
| 1120 |
|
|
Y : out std_logic
|
| 1121 |
|
|
);
|
| 1122 |
|
|
end component;
|
| 1123 |
|
|
|
| 1124 |
|
|
component VCC
|
| 1125 |
|
|
port( Y : out std_logic
|
| 1126 |
|
|
);
|
| 1127 |
|
|
end component;
|
| 1128 |
|
|
|
| 1129 |
|
|
component OR2
|
| 1130 |
|
|
port( A : in std_logic := 'U';
|
| 1131 |
|
|
B : in std_logic := 'U';
|
| 1132 |
|
|
Y : out std_logic
|
| 1133 |
|
|
);
|
| 1134 |
|
|
end component;
|
| 1135 |
|
|
|
| 1136 |
|
|
component OA1A
|
| 1137 |
|
|
port( A : in std_logic := 'U';
|
| 1138 |
|
|
B : in std_logic := 'U';
|
| 1139 |
|
|
C : in std_logic := 'U';
|
| 1140 |
|
|
Y : out std_logic
|
| 1141 |
|
|
);
|
| 1142 |
|
|
end component;
|
| 1143 |
|
|
|
| 1144 |
|
|
component AO1
|
| 1145 |
|
|
port( A : in std_logic := 'U';
|
| 1146 |
|
|
B : in std_logic := 'U';
|
| 1147 |
|
|
C : in std_logic := 'U';
|
| 1148 |
|
|
Y : out std_logic
|
| 1149 |
|
|
);
|
| 1150 |
|
|
end component;
|
| 1151 |
|
|
|
| 1152 |
|
|
component NOR3
|
| 1153 |
|
|
port( A : in std_logic := 'U';
|
| 1154 |
|
|
B : in std_logic := 'U';
|
| 1155 |
|
|
C : in std_logic := 'U';
|
| 1156 |
|
|
Y : out std_logic
|
| 1157 |
|
|
);
|
| 1158 |
|
|
end component;
|
| 1159 |
|
|
|
| 1160 |
|
|
component OA1
|
| 1161 |
|
|
port( A : in std_logic := 'U';
|
| 1162 |
|
|
B : in std_logic := 'U';
|
| 1163 |
|
|
C : in std_logic := 'U';
|
| 1164 |
|
|
Y : out std_logic
|
| 1165 |
|
|
);
|
| 1166 |
|
|
end component;
|
| 1167 |
|
|
|
| 1168 |
|
|
component GND
|
| 1169 |
|
|
port( Y : out std_logic
|
| 1170 |
|
|
);
|
| 1171 |
|
|
end component;
|
| 1172 |
|
|
|
| 1173 |
|
|
component AO1C
|
| 1174 |
|
|
port( A : in std_logic := 'U';
|
| 1175 |
|
|
B : in std_logic := 'U';
|
| 1176 |
|
|
C : in std_logic := 'U';
|
| 1177 |
|
|
Y : out std_logic
|
| 1178 |
|
|
);
|
| 1179 |
|
|
end component;
|
| 1180 |
|
|
|
| 1181 |
|
|
component AO1B
|
| 1182 |
|
|
port( A : in std_logic := 'U';
|
| 1183 |
|
|
B : in std_logic := 'U';
|
| 1184 |
|
|
C : in std_logic := 'U';
|
| 1185 |
|
|
Y : out std_logic
|
| 1186 |
|
|
);
|
| 1187 |
|
|
end component;
|
| 1188 |
|
|
|
| 1189 |
|
|
component OR3
|
| 1190 |
|
|
port( A : in std_logic := 'U';
|
| 1191 |
|
|
B : in std_logic := 'U';
|
| 1192 |
|
|
C : in std_logic := 'U';
|
| 1193 |
|
|
Y : out std_logic
|
| 1194 |
|
|
);
|
| 1195 |
|
|
end component;
|
| 1196 |
|
|
|
| 1197 |
|
|
component AOI1B
|
| 1198 |
|
|
port( A : in std_logic := 'U';
|
| 1199 |
|
|
B : in std_logic := 'U';
|
| 1200 |
|
|
C : in std_logic := 'U';
|
| 1201 |
|
|
Y : out std_logic
|
| 1202 |
|
|
);
|
| 1203 |
|
|
end component;
|
| 1204 |
|
|
|
| 1205 |
|
|
component MIN3X
|
| 1206 |
|
|
port( A : in std_logic := 'U';
|
| 1207 |
|
|
B : in std_logic := 'U';
|
| 1208 |
|
|
C : in std_logic := 'U';
|
| 1209 |
|
|
Y : out std_logic
|
| 1210 |
|
|
);
|
| 1211 |
|
|
end component;
|
| 1212 |
|
|
|
| 1213 |
|
|
signal \arbRegSMCurrentState_ns_i_a2_1[1]\,
|
| 1214 |
|
|
\arbRegSMCurrentState_i_0[14]\,
|
| 1215 |
|
|
\arbRegSMCurrentState_i_0[13]\,
|
| 1216 |
|
|
\arbRegSMCurrentState_i_0[15]\,
|
| 1217 |
|
|
\arbRegSMCurrentState_ns_i_a2_0_0[1]\, HSEL_1_0_4,
|
| 1218 |
|
|
HSEL_1_0_0_a0_4, HSEL_1_0_2, HSEL_1_0_3, HSEL_1_0_0,
|
| 1219 |
|
|
\arbRegSMCurrentState_RNIAS4K1_0[0]_net_1\,
|
| 1220 |
|
|
\arbRegSMCurrentState_RNIJM9G2[0]_net_1\, HSEL_1_0_0_a4_0,
|
| 1221 |
|
|
HSEL_1_0_0_a7_0, HSEL_1_0_0_0_tz, HADDR_26_0_a3_i_a0_2,
|
| 1222 |
|
|
\N_171\, HADDR_26_0_a3_i_out, HADDR_27_0_a3_i_a0_2,
|
| 1223 |
|
|
HADDR_27_0_a3_i_out, \N_263\, HSEL_1_0_0_a0_1,
|
| 1224 |
|
|
HSEL_1_0_0_a1_2, HADDR_m5_0_a3_1,
|
| 1225 |
|
|
\arbRegSMCurrentState_ns_i_a2_0_0[0]\,
|
| 1226 |
|
|
\arbRegSMCurrentState[2]_net_1\, N_156, N_172, N_171_1,
|
| 1227 |
|
|
\arbRegSMCurrentState_RNIG8815[14]_net_1\,
|
| 1228 |
|
|
\arbRegSMCurrentState_RNIB4DT5[0]_net_1\,
|
| 1229 |
|
|
\HADDR_24_0_a3_i_out\, \masterAddrInProg_i_1[0]\,
|
| 1230 |
|
|
\arbRegSMCurrentState_RNI289E2[0]_net_1\,
|
| 1231 |
|
|
\arbRegSMCurrentState_RNI069E2[0]_net_1\,
|
| 1232 |
|
|
\masterAddrInProg[3]\, \masterAddrInProg[2]\,
|
| 1233 |
|
|
\masterAddrInProg[1]\,
|
| 1234 |
|
|
\arbRegSMCurrentState_RNO[15]_net_1\, N_152,
|
| 1235 |
|
|
\arbRegSMCurrentState_RNO[14]_net_1\, N_153,
|
| 1236 |
|
|
\arbRegSMCurrentState_RNO[13]_net_1\,
|
| 1237 |
|
|
\arbRegSMCurrentState_i_0[12]\,
|
| 1238 |
|
|
\arbRegSMCurrentState_RNO[12]_net_1\,
|
| 1239 |
|
|
\arbRegSMCurrentState[6]_net_1\,
|
| 1240 |
|
|
\arbRegSMCurrentState[10]_net_1\,
|
| 1241 |
|
|
\arbRegSMCurrentState_ns[5]\,
|
| 1242 |
|
|
\arbRegSMCurrentState[9]_net_1\,
|
| 1243 |
|
|
\arbRegSMCurrentState_ns[9]\,
|
| 1244 |
|
|
\arbRegSMCurrentState[5]_net_1\,
|
| 1245 |
|
|
\arbRegSMCurrentState_ns[13]\,
|
| 1246 |
|
|
\arbRegSMCurrentState[1]_net_1\,
|
| 1247 |
|
|
\arbRegSMCurrentState_RNO[5]_net_1\,
|
| 1248 |
|
|
\arbRegSMCurrentState_RNO[4]_net_1\,
|
| 1249 |
|
|
\arbRegSMCurrentState_RNO[1]_net_1\,
|
| 1250 |
|
|
\arbRegSMCurrentState_RNO[0]_net_1\,
|
| 1251 |
|
|
\arbRegSMCurrentState_RNO[9]_net_1\,
|
| 1252 |
|
|
\arbRegSMCurrentState_RNO[8]_net_1\, \GND\, \VCC\
|
| 1253 |
|
|
: std_logic;
|
| 1254 |
|
|
|
| 1255 |
|
|
begin
|
| 1256 |
|
|
|
| 1257 |
|
|
arbRegSMCurrentState_i_0_3 <= \arbRegSMCurrentState_i_0[15]\;
|
| 1258 |
|
|
arbRegSMCurrentState_i_0_0 <= \arbRegSMCurrentState_i_0[12]\;
|
| 1259 |
|
|
masterAddrInProg(3) <= \masterAddrInProg[3]\;
|
| 1260 |
|
|
masterAddrInProg(2) <= \masterAddrInProg[2]\;
|
| 1261 |
|
|
masterAddrInProg(1) <= \masterAddrInProg[1]\;
|
| 1262 |
|
|
masterAddrInProg_i_1_0 <= \masterAddrInProg_i_1[0]\;
|
| 1263 |
|
|
HADDR_24_0_a3_i_out <= \HADDR_24_0_a3_i_out\;
|
| 1264 |
|
|
N_263 <= \N_263\;
|
| 1265 |
|
|
N_171 <= \N_171\;
|
| 1266 |
|
|
|
| 1267 |
|
|
\arbRegSMCurrentState_RNO[1]\ : NOR2B
|
| 1268 |
|
|
port map(A => \masterAddrInProg[3]\, B =>
|
| 1269 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY, Y =>
|
| 1270 |
|
|
\arbRegSMCurrentState_RNO[1]_net_1\);
|
| 1271 |
|
|
|
| 1272 |
|
|
\arbRegSMCurrentState[12]\ : DFN1P0
|
| 1273 |
|
|
port map(D => \arbRegSMCurrentState_RNO[12]_net_1\, CLK =>
|
| 1274 |
|
|
HCLK_c, PRE => HRESETn_c, Q =>
|
| 1275 |
|
|
\arbRegSMCurrentState_i_0[12]\);
|
| 1276 |
|
|
|
| 1277 |
|
|
\arbRegSMCurrentState_RNICAHF7[0]\ : OA1C
|
| 1278 |
|
|
port map(A => un1_m1_e_0_0, B =>
|
| 1279 |
|
|
\arbRegSMCurrentState_RNIG8815[14]_net_1\, C =>
|
| 1280 |
|
|
\HADDR_24_0_a3_i_out\, Y =>
|
| 1281 |
|
|
arbRegSMCurrentState_RNICAHF7_0);
|
| 1282 |
|
|
|
| 1283 |
|
|
\arbRegSMCurrentState_RNO[2]\ : AO1A
|
| 1284 |
|
|
port map(A => xhdl1221_0, B =>
|
| 1285 |
|
|
\arbRegSMCurrentState[2]_net_1\, C =>
|
| 1286 |
|
|
\arbRegSMCurrentState[1]_net_1\, Y =>
|
| 1287 |
|
|
\arbRegSMCurrentState_ns[13]\);
|
| 1288 |
|
|
|
| 1289 |
|
|
\arbRegSMCurrentState_RNIR8JU2[0]\ : NOR3B
|
| 1290 |
|
|
port map(A => HSEL_1_0_0_a1_0, B => \N_263\, C => \N_171\,
|
| 1291 |
|
|
Y => HSEL_1_0_0_a1_2);
|
| 1292 |
|
|
|
| 1293 |
|
|
\arbRegSMCurrentState[8]\ : DFN1C0
|
| 1294 |
|
|
port map(D => \arbRegSMCurrentState_RNO[8]_net_1\, CLK =>
|
| 1295 |
|
|
HCLK_c, CLR => HRESETn_c, Q => \masterAddrInProg[1]\);
|
| 1296 |
|
|
|
| 1297 |
|
|
\arbRegSMCurrentState[10]\ : DFN1C0
|
| 1298 |
|
|
port map(D => \arbRegSMCurrentState_ns[5]\, CLK => HCLK_c,
|
| 1299 |
|
|
CLR => HRESETn_c, Q => \arbRegSMCurrentState[10]_net_1\);
|
| 1300 |
|
|
|
| 1301 |
|
|
\arbRegSMCurrentState_RNO_4[14]\ : NOR3C
|
| 1302 |
|
|
port map(A => \arbRegSMCurrentState_i_0[14]\, B =>
|
| 1303 |
|
|
\arbRegSMCurrentState_i_0[13]\, C =>
|
| 1304 |
|
|
\arbRegSMCurrentState_i_0[15]\, Y =>
|
| 1305 |
|
|
\arbRegSMCurrentState_ns_i_a2_1[1]\);
|
| 1306 |
|
|
|
| 1307 |
|
|
\arbRegSMCurrentState_RNI069E2[0]\ : NOR2
|
| 1308 |
|
|
port map(A => HADDR_26_0_a3_i_out, B => un1_m1_e_0_0, Y =>
|
| 1309 |
|
|
\arbRegSMCurrentState_RNI069E2[0]_net_1\);
|
| 1310 |
|
|
|
| 1311 |
|
|
\arbRegSMCurrentState_RNO_0[15]\ : OR2A
|
| 1312 |
|
|
port map(A => xhdl1221_0, B => \N_171\, Y => N_152);
|
| 1313 |
|
|
|
| 1314 |
|
|
\arbRegSMCurrentState_RNIQQIS2[14]\ : NOR3A
|
| 1315 |
|
|
port map(A => HADDR_m5_0_m3, B => \N_171\, C => N_327, Y
|
| 1316 |
|
|
=> HADDR_m5_0_a3_1);
|
| 1317 |
|
|
|
| 1318 |
|
|
\arbRegSMCurrentState_RNIECHF7[0]\ : NOR3A
|
| 1319 |
|
|
port map(A => \masterAddrInProg_i_1[0]\, B => N_323, C =>
|
| 1320 |
|
|
\N_263\, Y => N_120);
|
| 1321 |
|
|
|
| 1322 |
|
|
\arbRegSMCurrentState_RNI289E2[0]\ : NOR2
|
| 1323 |
|
|
port map(A => HADDR_27_0_a3_i_out, B => un1_m1_e_0_0, Y =>
|
| 1324 |
|
|
\arbRegSMCurrentState_RNI289E2[0]_net_1\);
|
| 1325 |
|
|
|
| 1326 |
|
|
\arbRegSMCurrentState_RNO_0[14]\ : NOR2A
|
| 1327 |
|
|
port map(A => \arbRegSMCurrentState_i_0[13]\, B =>
|
| 1328 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY, Y =>
|
| 1329 |
|
|
\arbRegSMCurrentState_ns_i_a2_0_0[1]\);
|
| 1330 |
|
|
|
| 1331 |
|
|
VCC_i : VCC
|
| 1332 |
|
|
port map(Y => \VCC\);
|
| 1333 |
|
|
|
| 1334 |
|
|
\arbRegSMCurrentState_RNINQPT1[0]\ : OR2
|
| 1335 |
|
|
port map(A => \N_263\, B => N_325, Y => HADDR_27_0_a3_i_out);
|
| 1336 |
|
|
|
| 1337 |
|
|
\arbRegSMCurrentState_RNO_2[14]\ : OA1A
|
| 1338 |
|
|
port map(A => xhdl1221_0, B => N_172, C =>
|
| 1339 |
|
|
\arbRegSMCurrentState_ns_i_a2_1[1]\, Y => N_156);
|
| 1340 |
|
|
|
| 1341 |
|
|
\arbRegSMCurrentState_RNIJM9G2[0]\ : NOR2A
|
| 1342 |
|
|
port map(A => HSEL_1_0_0_a4_0, B => N_254, Y =>
|
| 1343 |
|
|
\arbRegSMCurrentState_RNIJM9G2[0]_net_1\);
|
| 1344 |
|
|
|
| 1345 |
|
|
\arbRegSMCurrentState_RNILM274[0]\ : AO1A
|
| 1346 |
|
|
port map(A => HSEL_1_0_0_a7_0, B => HSEL_1_0_0_1_0, C =>
|
| 1347 |
|
|
HSEL_1_0_0_0_tz, Y => HSEL_1_0_0);
|
| 1348 |
|
|
|
| 1349 |
|
|
\arbRegSMCurrentState_RNITMNO1[14]\ : NOR2B
|
| 1350 |
|
|
port map(A => \N_171\, B => un1_m1_e_0_0, Y =>
|
| 1351 |
|
|
HSEL_1_0_0_a7_0);
|
| 1352 |
|
|
|
| 1353 |
|
|
\arbRegSMCurrentState_RNI9BBD9[0]\ : AO1
|
| 1354 |
|
|
port map(A => HADDR_26_0_a3_i_a0_3, B =>
|
| 1355 |
|
|
HADDR_27_0_a3_i_a0_2, C =>
|
| 1356 |
|
|
\arbRegSMCurrentState_RNI289E2[0]_net_1\, Y => N_128);
|
| 1357 |
|
|
|
| 1358 |
|
|
\arbRegSMCurrentState_RNI8ECA7[0]\ : NOR3A
|
| 1359 |
|
|
port map(A => \masterAddrInProg_i_1[0]\, B => \N_263\, C
|
| 1360 |
|
|
=> N_302, Y => N_22);
|
| 1361 |
|
|
|
| 1362 |
|
|
\arbRegSMCurrentState_RNO[0]\ : NOR2A
|
| 1363 |
|
|
port map(A => \masterAddrInProg[3]\, B =>
|
| 1364 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY, Y =>
|
| 1365 |
|
|
\arbRegSMCurrentState_RNO[0]_net_1\);
|
| 1366 |
|
|
|
| 1367 |
|
|
\arbRegSMCurrentState[0]\ : DFN1C0
|
| 1368 |
|
|
port map(D => \arbRegSMCurrentState_RNO[0]_net_1\, CLK =>
|
| 1369 |
|
|
HCLK_c, CLR => HRESETn_c, Q => \masterAddrInProg[3]\);
|
| 1370 |
|
|
|
| 1371 |
|
|
\arbRegSMCurrentState_RNI6CCA7[0]\ : NOR3A
|
| 1372 |
|
|
port map(A => \masterAddrInProg_i_1[0]\, B => \N_263\, C
|
| 1373 |
|
|
=> N_301, Y => N_20);
|
| 1374 |
|
|
|
| 1375 |
|
|
\arbRegSMCurrentState_RNO[12]\ : OR2
|
| 1376 |
|
|
port map(A => \arbRegSMCurrentState_i_0[12]\, B =>
|
| 1377 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY, Y =>
|
| 1378 |
|
|
\arbRegSMCurrentState_RNO[12]_net_1\);
|
| 1379 |
|
|
|
| 1380 |
|
|
\arbRegSMCurrentState_RNO[15]\ : AO1
|
| 1381 |
|
|
port map(A => N_152, B => \arbRegSMCurrentState_i_0[15]\, C
|
| 1382 |
|
|
=> CoreAHBLite_0_AHBmslave0_HREADY, Y =>
|
| 1383 |
|
|
\arbRegSMCurrentState_RNO[15]_net_1\);
|
| 1384 |
|
|
|
| 1385 |
|
|
\arbRegSMCurrentState_RNO[8]\ : NOR2A
|
| 1386 |
|
|
port map(A => \masterAddrInProg[1]\, B =>
|
| 1387 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY, Y =>
|
| 1388 |
|
|
\arbRegSMCurrentState_RNO[8]_net_1\);
|
| 1389 |
|
|
|
| 1390 |
|
|
\arbRegSMCurrentState[14]\ : DFN1P0
|
| 1391 |
|
|
port map(D => \arbRegSMCurrentState_RNO[14]_net_1\, CLK =>
|
| 1392 |
|
|
HCLK_c, PRE => HRESETn_c, Q =>
|
| 1393 |
|
|
\arbRegSMCurrentState_i_0[14]\);
|
| 1394 |
|
|
|
| 1395 |
|
|
\arbRegSMCurrentState_RNIL5804[0]\ : NOR3
|
| 1396 |
|
|
port map(A => N_330, B => \N_171\, C => HADDR_26_0_a3_i_out,
|
| 1397 |
|
|
Y => HADDR_26_0_a3_i_a0_2);
|
| 1398 |
|
|
|
| 1399 |
|
|
\arbRegSMCurrentState[6]\ : DFN1C0
|
| 1400 |
|
|
port map(D => \arbRegSMCurrentState_ns[9]\, CLK => HCLK_c,
|
| 1401 |
|
|
CLR => HRESETn_c, Q => \arbRegSMCurrentState[6]_net_1\);
|
| 1402 |
|
|
|
| 1403 |
|
|
\arbRegSMCurrentState_RNI57BD9[0]\ : AO1
|
| 1404 |
|
|
port map(A => HADDR_26_0_a3_i_a0_3, B =>
|
| 1405 |
|
|
HADDR_26_0_a3_i_a0_2, C =>
|
| 1406 |
|
|
\arbRegSMCurrentState_RNI069E2[0]_net_1\, Y => N_124);
|
| 1407 |
|
|
|
| 1408 |
|
|
\arbRegSMCurrentState[1]\ : DFN1C0
|
| 1409 |
|
|
port map(D => \arbRegSMCurrentState_RNO[1]_net_1\, CLK =>
|
| 1410 |
|
|
HCLK_c, CLR => HRESETn_c, Q =>
|
| 1411 |
|
|
\arbRegSMCurrentState[1]_net_1\);
|
| 1412 |
|
|
|
| 1413 |
|
|
\arbRegSMCurrentState_RNO[6]\ : AO1A
|
| 1414 |
|
|
port map(A => xhdl1221_0, B =>
|
| 1415 |
|
|
\arbRegSMCurrentState[6]_net_1\, C =>
|
| 1416 |
|
|
\arbRegSMCurrentState[5]_net_1\, Y =>
|
| 1417 |
|
|
\arbRegSMCurrentState_ns[9]\);
|
| 1418 |
|
|
|
| 1419 |
|
|
\arbRegSMCurrentState_RNO[10]\ : AO1A
|
| 1420 |
|
|
port map(A => xhdl1221_0, B =>
|
| 1421 |
|
|
\arbRegSMCurrentState[10]_net_1\, C =>
|
| 1422 |
|
|
\arbRegSMCurrentState[9]_net_1\, Y =>
|
| 1423 |
|
|
\arbRegSMCurrentState_ns[5]\);
|
| 1424 |
|
|
|
| 1425 |
|
|
\arbRegSMCurrentState_RNIN7804[0]\ : NOR3
|
| 1426 |
|
|
port map(A => N_330, B => \N_171\, C => HADDR_27_0_a3_i_out,
|
| 1427 |
|
|
Y => HADDR_27_0_a3_i_a0_2);
|
| 1428 |
|
|
|
| 1429 |
|
|
\arbRegSMCurrentState_RNO[4]\ : NOR2A
|
| 1430 |
|
|
port map(A => \masterAddrInProg[2]\, B =>
|
| 1431 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY, Y =>
|
| 1432 |
|
|
\arbRegSMCurrentState_RNO[4]_net_1\);
|
| 1433 |
|
|
|
| 1434 |
|
|
\arbRegSMCurrentState_RNO[13]\ : OR2A
|
| 1435 |
|
|
port map(A => CoreAHBLite_0_AHBmslave0_HREADY, B =>
|
| 1436 |
|
|
\arbRegSMCurrentState_i_0[12]\, Y =>
|
| 1437 |
|
|
\arbRegSMCurrentState_RNO[13]_net_1\);
|
| 1438 |
|
|
|
| 1439 |
|
|
\arbRegSMCurrentState_RNIDJS95[0]\ : OA1
|
| 1440 |
|
|
port map(A => HTRANS_0_a3_i_a2_0_a0_1, B => \N_263\, C =>
|
| 1441 |
|
|
HTRANS_0_a3_i_a2_2_0, Y => N_363);
|
| 1442 |
|
|
|
| 1443 |
|
|
GND_i : GND
|
| 1444 |
|
|
port map(Y => \GND\);
|
| 1445 |
|
|
|
| 1446 |
|
|
\arbRegSMCurrentState_RNO_1[14]\ : OR2
|
| 1447 |
|
|
port map(A => \arbRegSMCurrentState_i_0[14]\, B =>
|
| 1448 |
|
|
xhdl1221_0, Y => N_153);
|
| 1449 |
|
|
|
| 1450 |
|
|
\arbRegSMCurrentState_RNIP44K[10]\ : NOR2
|
| 1451 |
|
|
port map(A => \arbRegSMCurrentState[6]_net_1\, B =>
|
| 1452 |
|
|
\arbRegSMCurrentState[10]_net_1\, Y => N_171_1);
|
| 1453 |
|
|
|
| 1454 |
|
|
\arbRegSMCurrentState_RNIP3DR3[0]\ : NOR3C
|
| 1455 |
|
|
port map(A => \N_263\, B => HSEL_1_0_0_a0_1, C => N_254, Y
|
| 1456 |
|
|
=> HSEL_1_0_0_a0_4);
|
| 1457 |
|
|
|
| 1458 |
|
|
\arbRegSMCurrentState_RNO_3[14]\ : NOR2A
|
| 1459 |
|
|
port map(A => N_171_1, B => \arbRegSMCurrentState[2]_net_1\,
|
| 1460 |
|
|
Y => N_172);
|
| 1461 |
|
|
|
| 1462 |
|
|
\arbRegSMCurrentState_RNO[14]\ : AO1
|
| 1463 |
|
|
port map(A => \arbRegSMCurrentState_ns_i_a2_0_0[1]\, B =>
|
| 1464 |
|
|
N_153, C => N_156, Y =>
|
| 1465 |
|
|
\arbRegSMCurrentState_RNO[14]_net_1\);
|
| 1466 |
|
|
|
| 1467 |
|
|
\arbRegSMCurrentState[9]\ : DFN1C0
|
| 1468 |
|
|
port map(D => \arbRegSMCurrentState_RNO[9]_net_1\, CLK =>
|
| 1469 |
|
|
HCLK_c, CLR => HRESETn_c, Q =>
|
| 1470 |
|
|
\arbRegSMCurrentState[9]_net_1\);
|
| 1471 |
|
|
|
| 1472 |
|
|
\arbRegSMCurrentState[4]\ : DFN1C0
|
| 1473 |
|
|
port map(D => \arbRegSMCurrentState_RNO[4]_net_1\, CLK =>
|
| 1474 |
|
|
HCLK_c, CLR => HRESETn_c, Q => \masterAddrInProg[2]\);
|
| 1475 |
|
|
|
| 1476 |
|
|
\arbRegSMCurrentState[13]\ : DFN1P0
|
| 1477 |
|
|
port map(D => \arbRegSMCurrentState_RNO[13]_net_1\, CLK =>
|
| 1478 |
|
|
HCLK_c, PRE => HRESETn_c, Q =>
|
| 1479 |
|
|
\arbRegSMCurrentState_i_0[13]\);
|
| 1480 |
|
|
|
| 1481 |
|
|
\arbRegSMCurrentState_RNIP44K[14]\ : NOR2A
|
| 1482 |
|
|
port map(A => \arbRegSMCurrentState_i_0[14]\, B =>
|
| 1483 |
|
|
\arbRegSMCurrentState[2]_net_1\, Y =>
|
| 1484 |
|
|
\arbRegSMCurrentState_ns_i_a2_0_0[0]\);
|
| 1485 |
|
|
|
| 1486 |
|
|
\arbRegSMCurrentState[2]\ : DFN1P0
|
| 1487 |
|
|
port map(D => \arbRegSMCurrentState_ns[13]\, CLK => HCLK_c,
|
| 1488 |
|
|
PRE => HRESETn_c, Q => \arbRegSMCurrentState[2]_net_1\);
|
| 1489 |
|
|
|
| 1490 |
|
|
\arbRegSMCurrentState_RNILOPT1[0]\ : OR2
|
| 1491 |
|
|
port map(A => \N_263\, B => N_324, Y => HADDR_26_0_a3_i_out);
|
| 1492 |
|
|
|
| 1493 |
|
|
\arbRegSMCurrentState_RNIHTPM3[0]\ : AO1C
|
| 1494 |
|
|
port map(A => N_327, B => N_397, C => HSEL_1_0_0_a4_0, Y
|
| 1495 |
|
|
=> HSEL_1_0_2);
|
| 1496 |
|
|
|
| 1497 |
|
|
\arbRegSMCurrentState_RNIAS4K1_0[0]\ : NOR2A
|
| 1498 |
|
|
port map(A => \N_263\, B => un1_m1_e_0_0, Y =>
|
| 1499 |
|
|
\arbRegSMCurrentState_RNIAS4K1_0[0]_net_1\);
|
| 1500 |
|
|
|
| 1501 |
|
|
\arbRegSMCurrentState_RNI4ACA7[0]\ : NOR3A
|
| 1502 |
|
|
port map(A => \masterAddrInProg_i_1[0]\, B => \N_263\, C
|
| 1503 |
|
|
=> N_300, Y => N_18);
|
| 1504 |
|
|
|
| 1505 |
|
|
\arbRegSMCurrentState_RNIAS4K1[0]\ : NOR2A
|
| 1506 |
|
|
port map(A => un1_m1_e_0_0, B => HSEL_1_0_0_0_tz, Y =>
|
| 1507 |
|
|
HSEL_1_0_0_a4_0);
|
| 1508 |
|
|
|
| 1509 |
|
|
\arbRegSMCurrentState_RNIG8815[14]\ : NOR3C
|
| 1510 |
|
|
port map(A => N_254, B => N_397, C => HADDR_m5_0_a3_1, Y
|
| 1511 |
|
|
=> \arbRegSMCurrentState_RNIG8815[14]_net_1\);
|
| 1512 |
|
|
|
| 1513 |
|
|
MASTERADDRINPROG_m2_0_a2 : AO1B
|
| 1514 |
|
|
port map(A => un4_m5_0_a3_2, B => un4_m5_0_a3_1, C =>
|
| 1515 |
|
|
un1_m1_e_0_0, Y => \masterAddrInProg_i_1[0]\);
|
| 1516 |
|
|
|
| 1517 |
|
|
\arbRegSMCurrentState_RNIVEL31[0]\ : OR3
|
| 1518 |
|
|
port map(A => \masterAddrInProg[3]\, B =>
|
| 1519 |
|
|
\masterAddrInProg[2]\, C => \masterAddrInProg[1]\, Y =>
|
| 1520 |
|
|
\N_263\);
|
| 1521 |
|
|
|
| 1522 |
|
|
\arbRegSMCurrentState_RNIHKPT1[0]\ : OR2
|
| 1523 |
|
|
port map(A => \N_263\, B => N_322, Y =>
|
| 1524 |
|
|
\HADDR_24_0_a3_i_out\);
|
| 1525 |
|
|
|
| 1526 |
|
|
\arbRegSMCurrentState[5]\ : DFN1C0
|
| 1527 |
|
|
port map(D => \arbRegSMCurrentState_RNO[5]_net_1\, CLK =>
|
| 1528 |
|
|
HCLK_c, CLR => HRESETn_c, Q =>
|
| 1529 |
|
|
\arbRegSMCurrentState[5]_net_1\);
|
| 1530 |
|
|
|
| 1531 |
|
|
\arbRegSMCurrentState_RNIHQIR1[14]\ : NOR2A
|
| 1532 |
|
|
port map(A => HSEL_1_0_0_a0_0, B => \N_171\, Y =>
|
| 1533 |
|
|
HSEL_1_0_0_a0_1);
|
| 1534 |
|
|
|
| 1535 |
|
|
\arbRegSMCurrentState[15]\ : DFN1P0
|
| 1536 |
|
|
port map(D => \arbRegSMCurrentState_RNO[15]_net_1\, CLK =>
|
| 1537 |
|
|
HCLK_c, PRE => HRESETn_c, Q =>
|
| 1538 |
|
|
\arbRegSMCurrentState_i_0[15]\);
|
| 1539 |
|
|
|
| 1540 |
|
|
\arbRegSMCurrentState_RNII9881[14]\ : NOR2B
|
| 1541 |
|
|
port map(A => \arbRegSMCurrentState_ns_i_a2_0_0[0]\, B =>
|
| 1542 |
|
|
N_171_1, Y => \N_171\);
|
| 1543 |
|
|
|
| 1544 |
|
|
\arbRegSMCurrentState_RNII9HB8[0]\ : NOR3A
|
| 1545 |
|
|
port map(A => HSEL_1_0_0, B =>
|
| 1546 |
|
|
\arbRegSMCurrentState_RNIAS4K1_0[0]_net_1\, C =>
|
| 1547 |
|
|
\arbRegSMCurrentState_RNIJM9G2[0]_net_1\, Y => HSEL_1_0_3);
|
| 1548 |
|
|
|
| 1549 |
|
|
\arbRegSMCurrentState_RNIEGQTN[0]\ : NOR3B
|
| 1550 |
|
|
port map(A => HSEL_1_0_3, B => HSEL_1_0_4, C =>
|
| 1551 |
|
|
\arbRegSMCurrentState_RNIB4DT5[0]_net_1\, Y =>
|
| 1552 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx);
|
| 1553 |
|
|
|
| 1554 |
|
|
\arbRegSMCurrentState_RNIDJS95_0[0]\ : OA1
|
| 1555 |
|
|
port map(A => N_403, B => \N_263\, C =>
|
| 1556 |
|
|
un1_N_11_mux_i_5_a1_1, Y => N_367);
|
| 1557 |
|
|
|
| 1558 |
|
|
\arbRegSMCurrentState_RNIB4DT5[0]\ : NOR3C
|
| 1559 |
|
|
port map(A => N_254, B => HSEL_1_0_0_a1_2, C =>
|
| 1560 |
|
|
un4_m5_0_a3_1, Y =>
|
| 1561 |
|
|
\arbRegSMCurrentState_RNIB4DT5[0]_net_1\);
|
| 1562 |
|
|
|
| 1563 |
|
|
\arbRegSMCurrentState_RNIH2SK9[0]\ : AOI1B
|
| 1564 |
|
|
port map(A => HSEL_1_0_0_a0_4, B => un4_m5_0_a3_1, C =>
|
| 1565 |
|
|
HSEL_1_0_2, Y => HSEL_1_0_4);
|
| 1566 |
|
|
|
| 1567 |
|
|
\arbRegSMCurrentState_RNIGOLP7[0]\ : NOR3A
|
| 1568 |
|
|
port map(A => \masterAddrInProg_i_1[0]\, B => \N_263\, C
|
| 1569 |
|
|
=> N_326, Y => N_135);
|
| 1570 |
|
|
|
| 1571 |
|
|
\arbRegSMCurrentState_RNO[5]\ : NOR2B
|
| 1572 |
|
|
port map(A => \masterAddrInProg[2]\, B =>
|
| 1573 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY, Y =>
|
| 1574 |
|
|
\arbRegSMCurrentState_RNO[5]_net_1\);
|
| 1575 |
|
|
|
| 1576 |
|
|
\arbRegSMCurrentState_RNO[9]\ : NOR2B
|
| 1577 |
|
|
port map(A => \masterAddrInProg[1]\, B =>
|
| 1578 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY, Y =>
|
| 1579 |
|
|
\arbRegSMCurrentState_RNO[9]_net_1\);
|
| 1580 |
|
|
|
| 1581 |
|
|
\arbRegSMCurrentState_RNIVEL31_0[0]\ : MIN3X
|
| 1582 |
|
|
port map(A => \masterAddrInProg[3]\, B =>
|
| 1583 |
|
|
\masterAddrInProg[2]\, C => \masterAddrInProg[1]\, Y =>
|
| 1584 |
|
|
HSEL_1_0_0_0_tz);
|
| 1585 |
|
|
|
| 1586 |
|
|
|
| 1587 |
|
|
end DEF_ARCH;
|
| 1588 |
|
|
|
| 1589 |
|
|
library ieee;
|
| 1590 |
|
|
use ieee.std_logic_1164.all;
|
| 1591 |
|
|
library proasic3;
|
| 1592 |
|
|
use proasic3.all;
|
| 1593 |
|
|
|
| 1594 |
|
|
entity COREAHBLITE_SLAVESTAGE_16 is
|
| 1595 |
|
|
|
| 1596 |
|
|
port( xhdl1221_0 : in std_logic;
|
| 1597 |
|
|
arbRegSMCurrentState_RNICAHF7_0 : out std_logic;
|
| 1598 |
|
|
arbRegSMCurrentState_i_0_3 : out std_logic;
|
| 1599 |
|
|
arbRegSMCurrentState_i_0_0 : out std_logic;
|
| 1600 |
|
|
masterAddrInProg_i_1_0 : out std_logic;
|
| 1601 |
|
|
regHADDR_29 : in std_logic;
|
| 1602 |
|
|
regHADDR_22 : in std_logic;
|
| 1603 |
|
|
regHADDR_23 : in std_logic;
|
| 1604 |
|
|
regHADDR_24 : in std_logic;
|
| 1605 |
|
|
regHADDR_25 : in std_logic;
|
| 1606 |
|
|
regHADDR_2 : in std_logic;
|
| 1607 |
|
|
regHADDR_1 : in std_logic;
|
| 1608 |
|
|
regHADDR_0 : in std_logic;
|
| 1609 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_29 : in std_logic;
|
| 1610 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_22 : in std_logic;
|
| 1611 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_23 : in std_logic;
|
| 1612 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_24 : in std_logic;
|
| 1613 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_25 : in std_logic;
|
| 1614 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_2 : in std_logic;
|
| 1615 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_1 : in std_logic;
|
| 1616 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_0 : in std_logic;
|
| 1617 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA : in std_logic_vector(7 downto 0);
|
| 1618 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA : out std_logic_vector(7 downto 0);
|
| 1619 |
|
|
AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : in std_logic;
|
| 1620 |
|
|
masterDataInProg_0 : out std_logic;
|
| 1621 |
|
|
SDATASELInt_2 : in std_logic;
|
| 1622 |
|
|
SDATASELInt_4 : in std_logic;
|
| 1623 |
|
|
SDATASELInt_0 : in std_logic;
|
| 1624 |
|
|
N_327 : in std_logic;
|
| 1625 |
|
|
N_397 : in std_logic;
|
| 1626 |
|
|
N_330 : in std_logic;
|
| 1627 |
|
|
N_171 : out std_logic;
|
| 1628 |
|
|
N_263 : out std_logic;
|
| 1629 |
|
|
N_367 : out std_logic;
|
| 1630 |
|
|
N_403 : in std_logic;
|
| 1631 |
|
|
un1_N_11_mux_i_5_a1_1 : in std_logic;
|
| 1632 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx : out std_logic;
|
| 1633 |
|
|
N_363 : out std_logic;
|
| 1634 |
|
|
HADDR_24_0_a3_i_out : out std_logic;
|
| 1635 |
|
|
un4_m5_0_a3_2 : in std_logic;
|
| 1636 |
|
|
N_128 : out std_logic;
|
| 1637 |
|
|
N_124 : out std_logic;
|
| 1638 |
|
|
N_120 : out std_logic;
|
| 1639 |
|
|
N_22 : out std_logic;
|
| 1640 |
|
|
N_20 : out std_logic;
|
| 1641 |
|
|
N_135 : out std_logic;
|
| 1642 |
|
|
N_18 : out std_logic;
|
| 1643 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY : in std_logic;
|
| 1644 |
|
|
HRESETn_c : in std_logic;
|
| 1645 |
|
|
HCLK_c : in std_logic;
|
| 1646 |
|
|
regHWRITE : in std_logic;
|
| 1647 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWRITE : in std_logic;
|
| 1648 |
|
|
N_326 : out std_logic;
|
| 1649 |
|
|
N_323 : out std_logic;
|
| 1650 |
|
|
regHTRANS : in std_logic;
|
| 1651 |
|
|
N_389 : in std_logic;
|
| 1652 |
|
|
N_377 : in std_logic;
|
| 1653 |
|
|
N_378 : in std_logic;
|
| 1654 |
|
|
N_390 : in std_logic;
|
| 1655 |
|
|
N_379 : in std_logic;
|
| 1656 |
|
|
N_380 : in std_logic;
|
| 1657 |
|
|
HTRANS_0_a3_i_a2_3_0 : out std_logic;
|
| 1658 |
|
|
HTRANS_0_a3_i_a2_4_0 : out std_logic;
|
| 1659 |
|
|
N_392 : in std_logic;
|
| 1660 |
|
|
N_365_1 : out std_logic;
|
| 1661 |
|
|
N_365 : out std_logic;
|
| 1662 |
|
|
N_394 : in std_logic;
|
| 1663 |
|
|
N_364_1 : out std_logic;
|
| 1664 |
|
|
N_364 : out std_logic;
|
| 1665 |
|
|
N_391 : in std_logic;
|
| 1666 |
|
|
un1_m1_e_0_0 : in std_logic;
|
| 1667 |
|
|
N_393 : out std_logic;
|
| 1668 |
|
|
N_398 : in std_logic;
|
| 1669 |
|
|
masterRegAddrSel : in std_logic;
|
| 1670 |
|
|
un4_m5_0_a3_1 : in std_logic;
|
| 1671 |
|
|
N_254 : out std_logic
|
| 1672 |
|
|
);
|
| 1673 |
|
|
|
| 1674 |
|
|
end COREAHBLITE_SLAVESTAGE_16;
|
| 1675 |
|
|
|
| 1676 |
|
|
architecture DEF_ARCH of COREAHBLITE_SLAVESTAGE_16 is
|
| 1677 |
|
|
|
| 1678 |
|
|
component DFN1E1C0
|
| 1679 |
|
|
port( D : in std_logic := 'U';
|
| 1680 |
|
|
CLK : in std_logic := 'U';
|
| 1681 |
|
|
CLR : in std_logic := 'U';
|
| 1682 |
|
|
E : in std_logic := 'U';
|
| 1683 |
|
|
Q : out std_logic
|
| 1684 |
|
|
);
|
| 1685 |
|
|
end component;
|
| 1686 |
|
|
|
| 1687 |
|
|
component MX2C
|
| 1688 |
|
|
port( A : in std_logic := 'U';
|
| 1689 |
|
|
B : in std_logic := 'U';
|
| 1690 |
|
|
S : in std_logic := 'U';
|
| 1691 |
|
|
Y : out std_logic
|
| 1692 |
|
|
);
|
| 1693 |
|
|
end component;
|
| 1694 |
|
|
|
| 1695 |
|
|
component NOR3C
|
| 1696 |
|
|
port( A : in std_logic := 'U';
|
| 1697 |
|
|
B : in std_logic := 'U';
|
| 1698 |
|
|
C : in std_logic := 'U';
|
| 1699 |
|
|
Y : out std_logic
|
| 1700 |
|
|
);
|
| 1701 |
|
|
end component;
|
| 1702 |
|
|
|
| 1703 |
|
|
component NOR3A
|
| 1704 |
|
|
port( A : in std_logic := 'U';
|
| 1705 |
|
|
B : in std_logic := 'U';
|
| 1706 |
|
|
C : in std_logic := 'U';
|
| 1707 |
|
|
Y : out std_logic
|
| 1708 |
|
|
);
|
| 1709 |
|
|
end component;
|
| 1710 |
|
|
|
| 1711 |
|
|
component NOR3
|
| 1712 |
|
|
port( A : in std_logic := 'U';
|
| 1713 |
|
|
B : in std_logic := 'U';
|
| 1714 |
|
|
C : in std_logic := 'U';
|
| 1715 |
|
|
Y : out std_logic
|
| 1716 |
|
|
);
|
| 1717 |
|
|
end component;
|
| 1718 |
|
|
|
| 1719 |
|
|
component NOR2A
|
| 1720 |
|
|
port( A : in std_logic := 'U';
|
| 1721 |
|
|
B : in std_logic := 'U';
|
| 1722 |
|
|
Y : out std_logic
|
| 1723 |
|
|
);
|
| 1724 |
|
|
end component;
|
| 1725 |
|
|
|
| 1726 |
|
|
component VCC
|
| 1727 |
|
|
port( Y : out std_logic
|
| 1728 |
|
|
);
|
| 1729 |
|
|
end component;
|
| 1730 |
|
|
|
| 1731 |
|
|
component NOR2B
|
| 1732 |
|
|
port( A : in std_logic := 'U';
|
| 1733 |
|
|
B : in std_logic := 'U';
|
| 1734 |
|
|
Y : out std_logic
|
| 1735 |
|
|
);
|
| 1736 |
|
|
end component;
|
| 1737 |
|
|
|
| 1738 |
|
|
component NOR2
|
| 1739 |
|
|
port( A : in std_logic := 'U';
|
| 1740 |
|
|
B : in std_logic := 'U';
|
| 1741 |
|
|
Y : out std_logic
|
| 1742 |
|
|
);
|
| 1743 |
|
|
end component;
|
| 1744 |
|
|
|
| 1745 |
|
|
component OR2A
|
| 1746 |
|
|
port( A : in std_logic := 'U';
|
| 1747 |
|
|
B : in std_logic := 'U';
|
| 1748 |
|
|
Y : out std_logic
|
| 1749 |
|
|
);
|
| 1750 |
|
|
end component;
|
| 1751 |
|
|
|
| 1752 |
|
|
component GND
|
| 1753 |
|
|
port( Y : out std_logic
|
| 1754 |
|
|
);
|
| 1755 |
|
|
end component;
|
| 1756 |
|
|
|
| 1757 |
|
|
component COREAHBLITE_SLAVEARBITER_0
|
| 1758 |
|
|
port( arbRegSMCurrentState_i_0_3 : out std_logic;
|
| 1759 |
|
|
arbRegSMCurrentState_i_0_0 : out std_logic;
|
| 1760 |
|
|
masterAddrInProg : out std_logic_vector(3 downto 1);
|
| 1761 |
|
|
masterAddrInProg_i_1_0 : out std_logic;
|
| 1762 |
|
|
arbRegSMCurrentState_RNICAHF7_0 : out std_logic;
|
| 1763 |
|
|
xhdl1221_0 : in std_logic := 'U';
|
| 1764 |
|
|
HRESETn_c : in std_logic := 'U';
|
| 1765 |
|
|
HCLK_c : in std_logic := 'U';
|
| 1766 |
|
|
N_300 : in std_logic := 'U';
|
| 1767 |
|
|
N_18 : out std_logic;
|
| 1768 |
|
|
N_326 : in std_logic := 'U';
|
| 1769 |
|
|
N_135 : out std_logic;
|
| 1770 |
|
|
N_301 : in std_logic := 'U';
|
| 1771 |
|
|
N_20 : out std_logic;
|
| 1772 |
|
|
N_302 : in std_logic := 'U';
|
| 1773 |
|
|
N_22 : out std_logic;
|
| 1774 |
|
|
N_323 : in std_logic := 'U';
|
| 1775 |
|
|
N_120 : out std_logic;
|
| 1776 |
|
|
N_322 : in std_logic := 'U';
|
| 1777 |
|
|
N_324 : in std_logic := 'U';
|
| 1778 |
|
|
N_325 : in std_logic := 'U';
|
| 1779 |
|
|
N_124 : out std_logic;
|
| 1780 |
|
|
HADDR_26_0_a3_i_a0_3 : in std_logic := 'U';
|
| 1781 |
|
|
N_128 : out std_logic;
|
| 1782 |
|
|
un4_m5_0_a3_2 : in std_logic := 'U';
|
| 1783 |
|
|
HADDR_24_0_a3_i_out : out std_logic;
|
| 1784 |
|
|
HTRANS_0_a3_i_a2_2_0 : in std_logic := 'U';
|
| 1785 |
|
|
HTRANS_0_a3_i_a2_0_a0_1 : in std_logic := 'U';
|
| 1786 |
|
|
N_363 : out std_logic;
|
| 1787 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx : out std_logic;
|
| 1788 |
|
|
un1_N_11_mux_i_5_a1_1 : in std_logic := 'U';
|
| 1789 |
|
|
N_403 : in std_logic := 'U';
|
| 1790 |
|
|
N_367 : out std_logic;
|
| 1791 |
|
|
un1_m1_e_0_0 : in std_logic := 'U';
|
| 1792 |
|
|
HADDR_m5_0_m3 : in std_logic := 'U';
|
| 1793 |
|
|
HSEL_1_0_0_a1_0 : in std_logic := 'U';
|
| 1794 |
|
|
HSEL_1_0_0_a0_0 : in std_logic := 'U';
|
| 1795 |
|
|
N_254 : in std_logic := 'U';
|
| 1796 |
|
|
N_263 : out std_logic;
|
| 1797 |
|
|
N_171 : out std_logic;
|
| 1798 |
|
|
N_330 : in std_logic := 'U';
|
| 1799 |
|
|
HSEL_1_0_0_1_0 : in std_logic := 'U';
|
| 1800 |
|
|
N_397 : in std_logic := 'U';
|
| 1801 |
|
|
N_327 : in std_logic := 'U';
|
| 1802 |
|
|
un4_m5_0_a3_1 : in std_logic := 'U';
|
| 1803 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY : in std_logic := 'U'
|
| 1804 |
|
|
);
|
| 1805 |
|
|
end component;
|
| 1806 |
|
|
|
| 1807 |
|
|
component MX2
|
| 1808 |
|
|
port( A : in std_logic := 'U';
|
| 1809 |
|
|
B : in std_logic := 'U';
|
| 1810 |
|
|
S : in std_logic := 'U';
|
| 1811 |
|
|
Y : out std_logic
|
| 1812 |
|
|
);
|
| 1813 |
|
|
end component;
|
| 1814 |
|
|
|
| 1815 |
|
|
component XA1
|
| 1816 |
|
|
port( A : in std_logic := 'U';
|
| 1817 |
|
|
B : in std_logic := 'U';
|
| 1818 |
|
|
C : in std_logic := 'U';
|
| 1819 |
|
|
Y : out std_logic
|
| 1820 |
|
|
);
|
| 1821 |
|
|
end component;
|
| 1822 |
|
|
|
| 1823 |
|
|
component OA1
|
| 1824 |
|
|
port( A : in std_logic := 'U';
|
| 1825 |
|
|
B : in std_logic := 'U';
|
| 1826 |
|
|
C : in std_logic := 'U';
|
| 1827 |
|
|
Y : out std_logic
|
| 1828 |
|
|
);
|
| 1829 |
|
|
end component;
|
| 1830 |
|
|
|
| 1831 |
|
|
signal \HADDR_26_0_a3_i_a0_3\, \N_254\, \HSEL_1_0_0_a0_0\,
|
| 1832 |
|
|
\HSEL_1_0_0_a1_0\, \HTRANS_0_a3_i_a2_2_0\, \N_393\,
|
| 1833 |
|
|
\HSEL_1_0_0_1_0\, \HSEL_1_0_0_1_tz_tz\,
|
| 1834 |
|
|
\HTRANS_0_a3_i_a2_0_a0_1_0\, hwdata10_1,
|
| 1835 |
|
|
\masterDataInProg[0]_net_1\, \masterDataInProg[3]_net_1\,
|
| 1836 |
|
|
hwdata10_0, \masterDataInProg[1]_net_1\,
|
| 1837 |
|
|
\masterDataInProg[2]_net_1\, \N_364_1\, \N_365_1\,
|
| 1838 |
|
|
\HTRANS_0_a3_i_a2_0_a0_1\, \HADDR_m5_0_m3\, N_322,
|
| 1839 |
|
|
\N_323\, N_324, N_325, N_302, N_301, \N_326\, N_300,
|
| 1840 |
|
|
\masterAddrInProg_i_1[0]\, \masterAddrInProg[1]\,
|
| 1841 |
|
|
\masterAddrInProg[2]\, \masterAddrInProg[3]\, \GND\,
|
| 1842 |
|
|
\VCC\ : std_logic;
|
| 1843 |
|
|
|
| 1844 |
|
|
for all : COREAHBLITE_SLAVEARBITER_0
|
| 1845 |
|
|
Use entity work.COREAHBLITE_SLAVEARBITER_0(DEF_ARCH);
|
| 1846 |
|
|
begin
|
| 1847 |
|
|
|
| 1848 |
|
|
masterAddrInProg_i_1_0 <= \masterAddrInProg_i_1[0]\;
|
| 1849 |
|
|
masterDataInProg_0 <= \masterDataInProg[0]_net_1\;
|
| 1850 |
|
|
N_326 <= \N_326\;
|
| 1851 |
|
|
N_323 <= \N_323\;
|
| 1852 |
|
|
N_365_1 <= \N_365_1\;
|
| 1853 |
|
|
N_364_1 <= \N_364_1\;
|
| 1854 |
|
|
N_393 <= \N_393\;
|
| 1855 |
|
|
N_254 <= \N_254\;
|
| 1856 |
|
|
|
| 1857 |
|
|
\masterDataInProg[3]\ : DFN1E1C0
|
| 1858 |
|
|
port map(D => \masterAddrInProg[3]\, CLK => HCLK_c, CLR =>
|
| 1859 |
|
|
HRESETn_c, E => CoreAHBLite_0_AHBmslave0_HREADY, Q =>
|
| 1860 |
|
|
\masterDataInProg[3]_net_1\);
|
| 1861 |
|
|
|
| 1862 |
|
|
HADDR_26_0_a3_i_m2 : MX2C
|
| 1863 |
|
|
port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_24, B =>
|
| 1864 |
|
|
regHADDR_24, S => masterRegAddrSel, Y => N_324);
|
| 1865 |
|
|
|
| 1866 |
|
|
\masterDataInProg_RNI6OM22[1]\ : NOR3C
|
| 1867 |
|
|
port map(A => hwdata10_0, B => hwdata10_1, C =>
|
| 1868 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(2), Y =>
|
| 1869 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(2));
|
| 1870 |
|
|
|
| 1871 |
|
|
\HTRANS_0_a3_i_a2_4_0\ : NOR3A
|
| 1872 |
|
|
port map(A => SDATASELInt_0, B => SDATASELInt_4, C =>
|
| 1873 |
|
|
SDATASELInt_2, Y => HTRANS_0_a3_i_a2_4_0);
|
| 1874 |
|
|
|
| 1875 |
|
|
\masterDataInProg_RNIBTM22[1]\ : NOR3C
|
| 1876 |
|
|
port map(A => hwdata10_0, B => hwdata10_1, C =>
|
| 1877 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(7), Y =>
|
| 1878 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(7));
|
| 1879 |
|
|
|
| 1880 |
|
|
HADDR_4_0_a3_i_m2 : MX2C
|
| 1881 |
|
|
port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_2, B =>
|
| 1882 |
|
|
regHADDR_2, S => masterRegAddrSel, Y => N_302);
|
| 1883 |
|
|
|
| 1884 |
|
|
HTRANS_m2_e_0_0 : NOR3
|
| 1885 |
|
|
port map(A => SDATASELInt_4, B => SDATASELInt_2, C =>
|
| 1886 |
|
|
SDATASELInt_0, Y => \N_393\);
|
| 1887 |
|
|
|
| 1888 |
|
|
HTRANS_0_a3_i_a2_0_a0_1_0 : NOR2A
|
| 1889 |
|
|
port map(A => N_391, B => SDATASELInt_0, Y =>
|
| 1890 |
|
|
\HTRANS_0_a3_i_a2_0_a0_1_0\);
|
| 1891 |
|
|
|
| 1892 |
|
|
\masterDataInProg_RNI4MM22[1]\ : NOR3C
|
| 1893 |
|
|
port map(A => hwdata10_0, B => hwdata10_1, C =>
|
| 1894 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(0), Y =>
|
| 1895 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(0));
|
| 1896 |
|
|
|
| 1897 |
|
|
VCC_i : VCC
|
| 1898 |
|
|
port map(Y => \VCC\);
|
| 1899 |
|
|
|
| 1900 |
|
|
\masterDataInProg[2]\ : DFN1E1C0
|
| 1901 |
|
|
port map(D => \masterAddrInProg[2]\, CLK => HCLK_c, CLR =>
|
| 1902 |
|
|
HRESETn_c, E => CoreAHBLite_0_AHBmslave0_HREADY, Q =>
|
| 1903 |
|
|
\masterDataInProg[2]_net_1\);
|
| 1904 |
|
|
|
| 1905 |
|
|
\masterDataInProg_RNI5NM22[1]\ : NOR3C
|
| 1906 |
|
|
port map(A => hwdata10_0, B => hwdata10_1, C =>
|
| 1907 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(1), Y =>
|
| 1908 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(1));
|
| 1909 |
|
|
|
| 1910 |
|
|
HADDR_3_0_a3_i_m2 : MX2C
|
| 1911 |
|
|
port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_1, B =>
|
| 1912 |
|
|
regHADDR_1, S => masterRegAddrSel, Y => N_301);
|
| 1913 |
|
|
|
| 1914 |
|
|
HADDR_2_0_a3_i_m2 : MX2C
|
| 1915 |
|
|
port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_0, B =>
|
| 1916 |
|
|
regHADDR_0, S => masterRegAddrSel, Y => N_300);
|
| 1917 |
|
|
|
| 1918 |
|
|
HADDR_24_0_a3_i_m2 : MX2C
|
| 1919 |
|
|
port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_22, B =>
|
| 1920 |
|
|
regHADDR_22, S => masterRegAddrSel, Y => N_322);
|
| 1921 |
|
|
|
| 1922 |
|
|
HADDR_25_0_a3_i_m2 : MX2C
|
| 1923 |
|
|
port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_23, B =>
|
| 1924 |
|
|
regHADDR_23, S => masterRegAddrSel, Y => \N_323\);
|
| 1925 |
|
|
|
| 1926 |
|
|
\HTRANS_0_a3_i_a2_3_0\ : NOR2B
|
| 1927 |
|
|
port map(A => N_398, B => \N_393\, Y =>
|
| 1928 |
|
|
HTRANS_0_a3_i_a2_3_0);
|
| 1929 |
|
|
|
| 1930 |
|
|
HWRITE_0_0_a3_i_m2 : MX2C
|
| 1931 |
|
|
port map(A => AHBMASTER_FIC_0_AHBmaster_HWRITE, B =>
|
| 1932 |
|
|
regHWRITE, S => masterRegAddrSel, Y => \N_326\);
|
| 1933 |
|
|
|
| 1934 |
|
|
\masterDataInProg[1]\ : DFN1E1C0
|
| 1935 |
|
|
port map(D => \masterAddrInProg[1]\, CLK => HCLK_c, CLR =>
|
| 1936 |
|
|
HRESETn_c, E => CoreAHBLite_0_AHBmslave0_HREADY, Q =>
|
| 1937 |
|
|
\masterDataInProg[1]_net_1\);
|
| 1938 |
|
|
|
| 1939 |
|
|
\masterDataInProg[0]\ : DFN1E1C0
|
| 1940 |
|
|
port map(D => \masterAddrInProg_i_1[0]\, CLK => HCLK_c, CLR
|
| 1941 |
|
|
=> HRESETn_c, E => CoreAHBLite_0_AHBmslave0_HREADY, Q
|
| 1942 |
|
|
=> \masterDataInProg[0]_net_1\);
|
| 1943 |
|
|
|
| 1944 |
|
|
\masterDataInProg_RNIVM5U[1]\ : NOR2
|
| 1945 |
|
|
port map(A => \masterDataInProg[1]_net_1\, B =>
|
| 1946 |
|
|
\masterDataInProg[2]_net_1\, Y => hwdata10_0);
|
| 1947 |
|
|
|
| 1948 |
|
|
\masterDataInProg_RNI8QM22[1]\ : NOR3C
|
| 1949 |
|
|
port map(A => hwdata10_0, B => hwdata10_1, C =>
|
| 1950 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(4), Y =>
|
| 1951 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(4));
|
| 1952 |
|
|
|
| 1953 |
|
|
\masterDataInProg_RNIASM22[1]\ : NOR3C
|
| 1954 |
|
|
port map(A => hwdata10_0, B => hwdata10_1, C =>
|
| 1955 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(6), Y =>
|
| 1956 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(6));
|
| 1957 |
|
|
|
| 1958 |
|
|
HSEL_1_0_0_1_0 : OR2A
|
| 1959 |
|
|
port map(A => un1_m1_e_0_0, B => \HSEL_1_0_0_1_tz_tz\, Y
|
| 1960 |
|
|
=> \HSEL_1_0_0_1_0\);
|
| 1961 |
|
|
|
| 1962 |
|
|
GND_i : GND
|
| 1963 |
|
|
port map(Y => \GND\);
|
| 1964 |
|
|
|
| 1965 |
|
|
HTRANS_0_a3_i_a2_1 : NOR3C
|
| 1966 |
|
|
port map(A => N_398, B => \N_364_1\, C => N_394, Y => N_364);
|
| 1967 |
|
|
|
| 1968 |
|
|
HSEL_1_0_0_a1_0 : NOR2A
|
| 1969 |
|
|
port map(A => masterRegAddrSel, B => regHADDR_29, Y =>
|
| 1970 |
|
|
\HSEL_1_0_0_a1_0\);
|
| 1971 |
|
|
|
| 1972 |
|
|
\masterDataInProg_RNI7PM22[1]\ : NOR3C
|
| 1973 |
|
|
port map(A => hwdata10_0, B => hwdata10_1, C =>
|
| 1974 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(3), Y =>
|
| 1975 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(3));
|
| 1976 |
|
|
|
| 1977 |
|
|
HSEL_1_0_0_a0_0 : NOR2
|
| 1978 |
|
|
port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_29, B =>
|
| 1979 |
|
|
masterRegAddrSel, Y => \HSEL_1_0_0_a0_0\);
|
| 1980 |
|
|
|
| 1981 |
|
|
\masterDataInProg_RNIVM5U[3]\ : NOR2A
|
| 1982 |
|
|
port map(A => \masterDataInProg[0]_net_1\, B =>
|
| 1983 |
|
|
\masterDataInProg[3]_net_1\, Y => hwdata10_1);
|
| 1984 |
|
|
|
| 1985 |
|
|
HADDR_m5_0_m3 : MX2C
|
| 1986 |
|
|
port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_29, B =>
|
| 1987 |
|
|
regHADDR_29, S => masterRegAddrSel, Y => \HADDR_m5_0_m3\);
|
| 1988 |
|
|
|
| 1989 |
|
|
HADDR_26_0_a3_i_a0_3 : NOR2B
|
| 1990 |
|
|
port map(A => \N_254\, B => un4_m5_0_a3_1, Y =>
|
| 1991 |
|
|
\HADDR_26_0_a3_i_a0_3\);
|
| 1992 |
|
|
|
| 1993 |
|
|
HTRANS_m2_e_0 : NOR3C
|
| 1994 |
|
|
port map(A => N_394, B => \N_365_1\, C => N_398, Y => N_365);
|
| 1995 |
|
|
|
| 1996 |
|
|
slave_arbiter : COREAHBLITE_SLAVEARBITER_0
|
| 1997 |
|
|
port map(arbRegSMCurrentState_i_0_3 =>
|
| 1998 |
|
|
arbRegSMCurrentState_i_0_3, arbRegSMCurrentState_i_0_0
|
| 1999 |
|
|
=> arbRegSMCurrentState_i_0_0, masterAddrInProg(3) =>
|
| 2000 |
|
|
\masterAddrInProg[3]\, masterAddrInProg(2) =>
|
| 2001 |
|
|
\masterAddrInProg[2]\, masterAddrInProg(1) =>
|
| 2002 |
|
|
\masterAddrInProg[1]\, masterAddrInProg_i_1_0 =>
|
| 2003 |
|
|
\masterAddrInProg_i_1[0]\,
|
| 2004 |
|
|
arbRegSMCurrentState_RNICAHF7_0 =>
|
| 2005 |
|
|
arbRegSMCurrentState_RNICAHF7_0, xhdl1221_0 => xhdl1221_0,
|
| 2006 |
|
|
HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, N_300 => N_300,
|
| 2007 |
|
|
N_18 => N_18, N_326 => \N_326\, N_135 => N_135, N_301 =>
|
| 2008 |
|
|
N_301, N_20 => N_20, N_302 => N_302, N_22 => N_22, N_323
|
| 2009 |
|
|
=> \N_323\, N_120 => N_120, N_322 => N_322, N_324 =>
|
| 2010 |
|
|
N_324, N_325 => N_325, N_124 => N_124,
|
| 2011 |
|
|
HADDR_26_0_a3_i_a0_3 => \HADDR_26_0_a3_i_a0_3\, N_128 =>
|
| 2012 |
|
|
N_128, un4_m5_0_a3_2 => un4_m5_0_a3_2,
|
| 2013 |
|
|
HADDR_24_0_a3_i_out => HADDR_24_0_a3_i_out,
|
| 2014 |
|
|
HTRANS_0_a3_i_a2_2_0 => \HTRANS_0_a3_i_a2_2_0\,
|
| 2015 |
|
|
HTRANS_0_a3_i_a2_0_a0_1 => \HTRANS_0_a3_i_a2_0_a0_1\,
|
| 2016 |
|
|
N_363 => N_363, CoreAHBLite_0_AHBmslave0_HSELx =>
|
| 2017 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx, un1_N_11_mux_i_5_a1_1 =>
|
| 2018 |
|
|
un1_N_11_mux_i_5_a1_1, N_403 => N_403, N_367 => N_367,
|
| 2019 |
|
|
un1_m1_e_0_0 => un1_m1_e_0_0, HADDR_m5_0_m3 =>
|
| 2020 |
|
|
\HADDR_m5_0_m3\, HSEL_1_0_0_a1_0 => \HSEL_1_0_0_a1_0\,
|
| 2021 |
|
|
HSEL_1_0_0_a0_0 => \HSEL_1_0_0_a0_0\, N_254 => \N_254\,
|
| 2022 |
|
|
N_263 => N_263, N_171 => N_171, N_330 => N_330,
|
| 2023 |
|
|
HSEL_1_0_0_1_0 => \HSEL_1_0_0_1_0\, N_397 => N_397, N_327
|
| 2024 |
|
|
=> N_327, un4_m5_0_a3_1 => un4_m5_0_a3_1,
|
| 2025 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY =>
|
| 2026 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY);
|
| 2027 |
|
|
|
| 2028 |
|
|
HTRANS_0_a3_i_a2_0_a0_1 : NOR2B
|
| 2029 |
|
|
port map(A => \HTRANS_0_a3_i_a2_0_a0_1_0\, B => N_392, Y
|
| 2030 |
|
|
=> \HTRANS_0_a3_i_a2_0_a0_1\);
|
| 2031 |
|
|
|
| 2032 |
|
|
HTRANS_0_a3_i_o4 : MX2
|
| 2033 |
|
|
port map(A => AHBMASTER_FIC_0_AHBmaster_HTRANS_0, B =>
|
| 2034 |
|
|
regHTRANS, S => masterRegAddrSel, Y => \N_254\);
|
| 2035 |
|
|
|
| 2036 |
|
|
HTRANS_0_a3_i_a2_2_0 : XA1
|
| 2037 |
|
|
port map(A => SDATASELInt_2, B => SDATASELInt_4, C => N_398,
|
| 2038 |
|
|
Y => \HTRANS_0_a3_i_a2_2_0\);
|
| 2039 |
|
|
|
| 2040 |
|
|
HTRANS_0_a3_i_a2_2_1 : OA1
|
| 2041 |
|
|
port map(A => N_378, B => N_377, C => N_389, Y => \N_365_1\);
|
| 2042 |
|
|
|
| 2043 |
|
|
HADDR_27_0_a3_i_m2 : MX2C
|
| 2044 |
|
|
port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_25, B =>
|
| 2045 |
|
|
regHADDR_25, S => masterRegAddrSel, Y => N_325);
|
| 2046 |
|
|
|
| 2047 |
|
|
HTRANS_0_a3_i_a2_1_1 : OA1
|
| 2048 |
|
|
port map(A => N_380, B => N_379, C => N_390, Y => \N_364_1\);
|
| 2049 |
|
|
|
| 2050 |
|
|
HSEL_1_0_0_1_tz_tz : MX2C
|
| 2051 |
|
|
port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_29, B =>
|
| 2052 |
|
|
regHADDR_29, S => masterRegAddrSel, Y =>
|
| 2053 |
|
|
\HSEL_1_0_0_1_tz_tz\);
|
| 2054 |
|
|
|
| 2055 |
|
|
\masterDataInProg_RNI9RM22[1]\ : NOR3C
|
| 2056 |
|
|
port map(A => hwdata10_0, B => hwdata10_1, C =>
|
| 2057 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(5), Y =>
|
| 2058 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(5));
|
| 2059 |
|
|
|
| 2060 |
|
|
|
| 2061 |
|
|
end DEF_ARCH;
|
| 2062 |
|
|
|
| 2063 |
|
|
library ieee;
|
| 2064 |
|
|
use ieee.std_logic_1164.all;
|
| 2065 |
|
|
library proasic3;
|
| 2066 |
|
|
use proasic3.all;
|
| 2067 |
|
|
|
| 2068 |
|
|
entity COREAHBLITE_DEFAULTSLAVESM_0 is
|
| 2069 |
|
|
|
| 2070 |
|
|
port( HRESETn_c : in std_logic;
|
| 2071 |
|
|
HCLK_c : in std_logic;
|
| 2072 |
|
|
N_382 : in std_logic;
|
| 2073 |
|
|
N_383 : in std_logic;
|
| 2074 |
|
|
N_390 : in std_logic;
|
| 2075 |
|
|
N_389 : in std_logic;
|
| 2076 |
|
|
N_393 : in std_logic;
|
| 2077 |
|
|
N_391 : out std_logic;
|
| 2078 |
|
|
N_394 : out std_logic;
|
| 2079 |
|
|
N_392 : out std_logic;
|
| 2080 |
|
|
N_399 : out std_logic;
|
| 2081 |
|
|
defSlaveSMCurrentState : out std_logic
|
| 2082 |
|
|
);
|
| 2083 |
|
|
|
| 2084 |
|
|
end COREAHBLITE_DEFAULTSLAVESM_0;
|
| 2085 |
|
|
|
| 2086 |
|
|
architecture DEF_ARCH of COREAHBLITE_DEFAULTSLAVESM_0 is
|
| 2087 |
|
|
|
| 2088 |
|
|
component NOR2B
|
| 2089 |
|
|
port( A : in std_logic := 'U';
|
| 2090 |
|
|
B : in std_logic := 'U';
|
| 2091 |
|
|
Y : out std_logic
|
| 2092 |
|
|
);
|
| 2093 |
|
|
end component;
|
| 2094 |
|
|
|
| 2095 |
|
|
component VCC
|
| 2096 |
|
|
port( Y : out std_logic
|
| 2097 |
|
|
);
|
| 2098 |
|
|
end component;
|
| 2099 |
|
|
|
| 2100 |
|
|
component NOR2
|
| 2101 |
|
|
port( A : in std_logic := 'U';
|
| 2102 |
|
|
B : in std_logic := 'U';
|
| 2103 |
|
|
Y : out std_logic
|
| 2104 |
|
|
);
|
| 2105 |
|
|
end component;
|
| 2106 |
|
|
|
| 2107 |
|
|
component GND
|
| 2108 |
|
|
port( Y : out std_logic
|
| 2109 |
|
|
);
|
| 2110 |
|
|
end component;
|
| 2111 |
|
|
|
| 2112 |
|
|
component DFN1C0
|
| 2113 |
|
|
port( D : in std_logic := 'U';
|
| 2114 |
|
|
CLK : in std_logic := 'U';
|
| 2115 |
|
|
CLR : in std_logic := 'U';
|
| 2116 |
|
|
Q : out std_logic
|
| 2117 |
|
|
);
|
| 2118 |
|
|
end component;
|
| 2119 |
|
|
|
| 2120 |
|
|
signal N_28, defSlaveSMCurrentState_net_1, \N_399\, \N_392\,
|
| 2121 |
|
|
\N_394\, \N_391\, \GND\, \VCC\ : std_logic;
|
| 2122 |
|
|
|
| 2123 |
|
|
begin
|
| 2124 |
|
|
|
| 2125 |
|
|
N_391 <= \N_391\;
|
| 2126 |
|
|
N_394 <= \N_394\;
|
| 2127 |
|
|
N_392 <= \N_392\;
|
| 2128 |
|
|
N_399 <= \N_399\;
|
| 2129 |
|
|
defSlaveSMCurrentState <= defSlaveSMCurrentState_net_1;
|
| 2130 |
|
|
|
| 2131 |
|
|
defSlaveSMNextState_i_0_a2_0 : NOR2B
|
| 2132 |
|
|
port map(A => \N_391\, B => N_393, Y => \N_394\);
|
| 2133 |
|
|
|
| 2134 |
|
|
VCC_i : VCC
|
| 2135 |
|
|
port map(Y => \VCC\);
|
| 2136 |
|
|
|
| 2137 |
|
|
defSlaveSMNextState_i_0_a4 : NOR2B
|
| 2138 |
|
|
port map(A => \N_392\, B => \N_394\, Y => \N_399\);
|
| 2139 |
|
|
|
| 2140 |
|
|
defSlaveSMNextState_i_0_a2 : NOR2B
|
| 2141 |
|
|
port map(A => N_389, B => N_390, Y => \N_392\);
|
| 2142 |
|
|
|
| 2143 |
|
|
defSlaveSMCurrentState_RNO : NOR2
|
| 2144 |
|
|
port map(A => defSlaveSMCurrentState_net_1, B => \N_399\, Y
|
| 2145 |
|
|
=> N_28);
|
| 2146 |
|
|
|
| 2147 |
|
|
GND_i : GND
|
| 2148 |
|
|
port map(Y => \GND\);
|
| 2149 |
|
|
|
| 2150 |
|
|
defSlaveSMNextState_i_0_a2_1 : NOR2B
|
| 2151 |
|
|
port map(A => N_383, B => N_382, Y => \N_391\);
|
| 2152 |
|
|
|
| 2153 |
|
|
\defSlaveSMCurrentState\ : DFN1C0
|
| 2154 |
|
|
port map(D => N_28, CLK => HCLK_c, CLR => HRESETn_c, Q =>
|
| 2155 |
|
|
defSlaveSMCurrentState_net_1);
|
| 2156 |
|
|
|
| 2157 |
|
|
|
| 2158 |
|
|
end DEF_ARCH;
|
| 2159 |
|
|
|
| 2160 |
|
|
library ieee;
|
| 2161 |
|
|
use ieee.std_logic_1164.all;
|
| 2162 |
|
|
library proasic3;
|
| 2163 |
|
|
use proasic3.all;
|
| 2164 |
|
|
|
| 2165 |
|
|
entity COREAHBLITE_MASTERSTAGE_1_1_0_1_0 is
|
| 2166 |
|
|
|
| 2167 |
|
|
port( AHBMASTER_FIC_0_AHBmaster_HADDR_26 : in std_logic;
|
| 2168 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_27 : in std_logic;
|
| 2169 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_28 : in std_logic;
|
| 2170 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_29 : in std_logic;
|
| 2171 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_0 : in std_logic;
|
| 2172 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_1 : in std_logic;
|
| 2173 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_2 : in std_logic;
|
| 2174 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_22 : in std_logic;
|
| 2175 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_23 : in std_logic;
|
| 2176 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_24 : in std_logic;
|
| 2177 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_25 : in std_logic;
|
| 2178 |
|
|
regHADDR_29 : out std_logic;
|
| 2179 |
|
|
regHADDR_0 : out std_logic;
|
| 2180 |
|
|
regHADDR_1 : out std_logic;
|
| 2181 |
|
|
regHADDR_2 : out std_logic;
|
| 2182 |
|
|
regHADDR_22 : out std_logic;
|
| 2183 |
|
|
regHADDR_23 : out std_logic;
|
| 2184 |
|
|
regHADDR_24 : out std_logic;
|
| 2185 |
|
|
regHADDR_25 : out std_logic;
|
| 2186 |
|
|
masterDataInProg_0 : in std_logic;
|
| 2187 |
|
|
masterAddrInProg_i_1_0 : in std_logic;
|
| 2188 |
|
|
xhdl1221_0 : out std_logic;
|
| 2189 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA : out std_logic_vector(7 downto 0);
|
| 2190 |
|
|
SDATASELInt_4 : out std_logic;
|
| 2191 |
|
|
SDATASELInt_2 : out std_logic;
|
| 2192 |
|
|
SDATASELInt_0 : out std_logic;
|
| 2193 |
|
|
xhdl1222_0 : out std_logic;
|
| 2194 |
|
|
CoreAPB_0_APBmslave0_PRDATA : in std_logic_vector(7 downto 0);
|
| 2195 |
|
|
AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : in std_logic;
|
| 2196 |
|
|
defSlaveSMCurrentState : out std_logic;
|
| 2197 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWRITE : in std_logic;
|
| 2198 |
|
|
regHWRITE : out std_logic;
|
| 2199 |
|
|
HRESETn_c : in std_logic;
|
| 2200 |
|
|
HCLK_c : in std_logic;
|
| 2201 |
|
|
N_163 : out std_logic;
|
| 2202 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY : in std_logic;
|
| 2203 |
|
|
N_254 : in std_logic;
|
| 2204 |
|
|
N_395 : out std_logic;
|
| 2205 |
|
|
N_393 : in std_logic;
|
| 2206 |
|
|
N_265 : out std_logic;
|
| 2207 |
|
|
N_390 : out std_logic;
|
| 2208 |
|
|
N_389 : out std_logic;
|
| 2209 |
|
|
N_380 : out std_logic;
|
| 2210 |
|
|
N_379 : out std_logic;
|
| 2211 |
|
|
N_378 : out std_logic;
|
| 2212 |
|
|
N_377 : out std_logic;
|
| 2213 |
|
|
N_339_c : out std_logic;
|
| 2214 |
|
|
N_394 : out std_logic;
|
| 2215 |
|
|
N_364_1 : in std_logic;
|
| 2216 |
|
|
N_365_1 : in std_logic;
|
| 2217 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_0 : out std_logic;
|
| 2218 |
|
|
N_403 : out std_logic;
|
| 2219 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_1 : out std_logic;
|
| 2220 |
|
|
N_392 : out std_logic;
|
| 2221 |
|
|
N_391 : out std_logic;
|
| 2222 |
|
|
PRDATA_0_sqmuxa_0_a2_13 : in std_logic;
|
| 2223 |
|
|
PRDATA_0_sqmuxa_0_a2_12 : in std_logic;
|
| 2224 |
|
|
N_327 : out std_logic;
|
| 2225 |
|
|
regHTRANS : out std_logic;
|
| 2226 |
|
|
masterRegAddrSel : out std_logic;
|
| 2227 |
|
|
N_340 : out std_logic;
|
| 2228 |
|
|
N_330 : out std_logic;
|
| 2229 |
|
|
N_397 : out std_logic;
|
| 2230 |
|
|
N_398 : in std_logic
|
| 2231 |
|
|
);
|
| 2232 |
|
|
|
| 2233 |
|
|
end COREAHBLITE_MASTERSTAGE_1_1_0_1_0;
|
| 2234 |
|
|
|
| 2235 |
|
|
architecture DEF_ARCH of COREAHBLITE_MASTERSTAGE_1_1_0_1_0 is
|
| 2236 |
|
|
|
| 2237 |
|
|
component NOR3B
|
| 2238 |
|
|
port( A : in std_logic := 'U';
|
| 2239 |
|
|
B : in std_logic := 'U';
|
| 2240 |
|
|
C : in std_logic := 'U';
|
| 2241 |
|
|
Y : out std_logic
|
| 2242 |
|
|
);
|
| 2243 |
|
|
end component;
|
| 2244 |
|
|
|
| 2245 |
|
|
component NOR2
|
| 2246 |
|
|
port( A : in std_logic := 'U';
|
| 2247 |
|
|
B : in std_logic := 'U';
|
| 2248 |
|
|
Y : out std_logic
|
| 2249 |
|
|
);
|
| 2250 |
|
|
end component;
|
| 2251 |
|
|
|
| 2252 |
|
|
component NOR3C
|
| 2253 |
|
|
port( A : in std_logic := 'U';
|
| 2254 |
|
|
B : in std_logic := 'U';
|
| 2255 |
|
|
C : in std_logic := 'U';
|
| 2256 |
|
|
Y : out std_logic
|
| 2257 |
|
|
);
|
| 2258 |
|
|
end component;
|
| 2259 |
|
|
|
| 2260 |
|
|
component XOR2
|
| 2261 |
|
|
port( A : in std_logic := 'U';
|
| 2262 |
|
|
B : in std_logic := 'U';
|
| 2263 |
|
|
Y : out std_logic
|
| 2264 |
|
|
);
|
| 2265 |
|
|
end component;
|
| 2266 |
|
|
|
| 2267 |
|
|
component DFN1E1C0
|
| 2268 |
|
|
port( D : in std_logic := 'U';
|
| 2269 |
|
|
CLK : in std_logic := 'U';
|
| 2270 |
|
|
CLR : in std_logic := 'U';
|
| 2271 |
|
|
E : in std_logic := 'U';
|
| 2272 |
|
|
Q : out std_logic
|
| 2273 |
|
|
);
|
| 2274 |
|
|
end component;
|
| 2275 |
|
|
|
| 2276 |
|
|
component NOR2B
|
| 2277 |
|
|
port( A : in std_logic := 'U';
|
| 2278 |
|
|
B : in std_logic := 'U';
|
| 2279 |
|
|
Y : out std_logic
|
| 2280 |
|
|
);
|
| 2281 |
|
|
end component;
|
| 2282 |
|
|
|
| 2283 |
|
|
component OR2B
|
| 2284 |
|
|
port( A : in std_logic := 'U';
|
| 2285 |
|
|
B : in std_logic := 'U';
|
| 2286 |
|
|
Y : out std_logic
|
| 2287 |
|
|
);
|
| 2288 |
|
|
end component;
|
| 2289 |
|
|
|
| 2290 |
|
|
component OA1
|
| 2291 |
|
|
port( A : in std_logic := 'U';
|
| 2292 |
|
|
B : in std_logic := 'U';
|
| 2293 |
|
|
C : in std_logic := 'U';
|
| 2294 |
|
|
Y : out std_logic
|
| 2295 |
|
|
);
|
| 2296 |
|
|
end component;
|
| 2297 |
|
|
|
| 2298 |
|
|
component AO1
|
| 2299 |
|
|
port( A : in std_logic := 'U';
|
| 2300 |
|
|
B : in std_logic := 'U';
|
| 2301 |
|
|
C : in std_logic := 'U';
|
| 2302 |
|
|
Y : out std_logic
|
| 2303 |
|
|
);
|
| 2304 |
|
|
end component;
|
| 2305 |
|
|
|
| 2306 |
|
|
component NOR3A
|
| 2307 |
|
|
port( A : in std_logic := 'U';
|
| 2308 |
|
|
B : in std_logic := 'U';
|
| 2309 |
|
|
C : in std_logic := 'U';
|
| 2310 |
|
|
Y : out std_logic
|
| 2311 |
|
|
);
|
| 2312 |
|
|
end component;
|
| 2313 |
|
|
|
| 2314 |
|
|
component DFN1C0
|
| 2315 |
|
|
port( D : in std_logic := 'U';
|
| 2316 |
|
|
CLK : in std_logic := 'U';
|
| 2317 |
|
|
CLR : in std_logic := 'U';
|
| 2318 |
|
|
Q : out std_logic
|
| 2319 |
|
|
);
|
| 2320 |
|
|
end component;
|
| 2321 |
|
|
|
| 2322 |
|
|
component VCC
|
| 2323 |
|
|
port( Y : out std_logic
|
| 2324 |
|
|
);
|
| 2325 |
|
|
end component;
|
| 2326 |
|
|
|
| 2327 |
|
|
component MX2
|
| 2328 |
|
|
port( A : in std_logic := 'U';
|
| 2329 |
|
|
B : in std_logic := 'U';
|
| 2330 |
|
|
S : in std_logic := 'U';
|
| 2331 |
|
|
Y : out std_logic
|
| 2332 |
|
|
);
|
| 2333 |
|
|
end component;
|
| 2334 |
|
|
|
| 2335 |
|
|
component OR2
|
| 2336 |
|
|
port( A : in std_logic := 'U';
|
| 2337 |
|
|
B : in std_logic := 'U';
|
| 2338 |
|
|
Y : out std_logic
|
| 2339 |
|
|
);
|
| 2340 |
|
|
end component;
|
| 2341 |
|
|
|
| 2342 |
|
|
component XA1
|
| 2343 |
|
|
port( A : in std_logic := 'U';
|
| 2344 |
|
|
B : in std_logic := 'U';
|
| 2345 |
|
|
C : in std_logic := 'U';
|
| 2346 |
|
|
Y : out std_logic
|
| 2347 |
|
|
);
|
| 2348 |
|
|
end component;
|
| 2349 |
|
|
|
| 2350 |
|
|
component NOR2A
|
| 2351 |
|
|
port( A : in std_logic := 'U';
|
| 2352 |
|
|
B : in std_logic := 'U';
|
| 2353 |
|
|
Y : out std_logic
|
| 2354 |
|
|
);
|
| 2355 |
|
|
end component;
|
| 2356 |
|
|
|
| 2357 |
|
|
component OA1A
|
| 2358 |
|
|
port( A : in std_logic := 'U';
|
| 2359 |
|
|
B : in std_logic := 'U';
|
| 2360 |
|
|
C : in std_logic := 'U';
|
| 2361 |
|
|
Y : out std_logic
|
| 2362 |
|
|
);
|
| 2363 |
|
|
end component;
|
| 2364 |
|
|
|
| 2365 |
|
|
component DFN1E0C0
|
| 2366 |
|
|
port( D : in std_logic := 'U';
|
| 2367 |
|
|
CLK : in std_logic := 'U';
|
| 2368 |
|
|
CLR : in std_logic := 'U';
|
| 2369 |
|
|
E : in std_logic := 'U';
|
| 2370 |
|
|
Q : out std_logic
|
| 2371 |
|
|
);
|
| 2372 |
|
|
end component;
|
| 2373 |
|
|
|
| 2374 |
|
|
component MIN3X
|
| 2375 |
|
|
port( A : in std_logic := 'U';
|
| 2376 |
|
|
B : in std_logic := 'U';
|
| 2377 |
|
|
C : in std_logic := 'U';
|
| 2378 |
|
|
Y : out std_logic
|
| 2379 |
|
|
);
|
| 2380 |
|
|
end component;
|
| 2381 |
|
|
|
| 2382 |
|
|
component GND
|
| 2383 |
|
|
port( Y : out std_logic
|
| 2384 |
|
|
);
|
| 2385 |
|
|
end component;
|
| 2386 |
|
|
|
| 2387 |
|
|
component COREAHBLITE_DEFAULTSLAVESM_0
|
| 2388 |
|
|
port( HRESETn_c : in std_logic := 'U';
|
| 2389 |
|
|
HCLK_c : in std_logic := 'U';
|
| 2390 |
|
|
N_382 : in std_logic := 'U';
|
| 2391 |
|
|
N_383 : in std_logic := 'U';
|
| 2392 |
|
|
N_390 : in std_logic := 'U';
|
| 2393 |
|
|
N_389 : in std_logic := 'U';
|
| 2394 |
|
|
N_393 : in std_logic := 'U';
|
| 2395 |
|
|
N_391 : out std_logic;
|
| 2396 |
|
|
N_394 : out std_logic;
|
| 2397 |
|
|
N_392 : out std_logic;
|
| 2398 |
|
|
N_399 : out std_logic;
|
| 2399 |
|
|
defSlaveSMCurrentState : out std_logic
|
| 2400 |
|
|
);
|
| 2401 |
|
|
end component;
|
| 2402 |
|
|
|
| 2403 |
|
|
signal d_masterRegAddrSel_0_0_a2_3_4,
|
| 2404 |
|
|
\SDATASELInt_RNISKATF_0[1]_net_1\,
|
| 2405 |
|
|
d_masterRegAddrSel_0_0_a2_3_3, \N_397\,
|
| 2406 |
|
|
d_masterRegAddrSel_0_0_a2_3_2, \N_330\,
|
| 2407 |
|
|
d_masterRegAddrSel_0_0_a2_3_1, \N_340\,
|
| 2408 |
|
|
masterRegAddrSel_net_1, d_masterRegAddrSel_0_0_a2_1,
|
| 2409 |
|
|
d_masterRegAddrSel_0_0_a2_0, regHTRANS_net_1, \N_327\,
|
| 2410 |
|
|
\HRDATA_4_6_0\, \HRDATA_4_5_0\, \HRDATA_4_2_0\,
|
| 2411 |
|
|
\HRDATA_4_0_0\, \HRDATA_4_7_0\, \HRDATA_4_3_0\,
|
| 2412 |
|
|
\HRDATA_4_4_0\, \HRDATA_4_1_0\, HREADY_m2_e_0_3,
|
| 2413 |
|
|
HREADY_m2_e_0_1, N_255, \N_391\, HREADY_m2_e_0_0,
|
| 2414 |
|
|
\SDATASELInt[5]_net_1\, \SDATASELInt[3]_net_1\,
|
| 2415 |
|
|
\xhdl1222[0]\, \SDATASELInt[1]_net_1\, N_399, \N_392\,
|
| 2416 |
|
|
masterAddrClockEnable, N_279,
|
| 2417 |
|
|
\PREVDATASLAVEREADY_iv_i_0_i_o4_1\, \N_403\,
|
| 2418 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_1_tz,
|
| 2419 |
|
|
\PREVDATASLAVEREADY_iv_i_0_i_o4_0\, SADDRSEL_N_5_mux,
|
| 2420 |
|
|
\regHADDR[29]_net_1\, \regHADDR[30]_net_1\,
|
| 2421 |
|
|
SADDRSEL_N_3_mux, N_361,
|
| 2422 |
|
|
\PREVDATASLAVEREADY_iv_i_0_i_o4_104\, N_251, \N_394\,
|
| 2423 |
|
|
N_259_i, \SDATASELInt[2]_net_1\, \SDATASELInt[7]_net_1\,
|
| 2424 |
|
|
N_258_i, N_384, N_257_i, \SDATASELInt[6]_net_1\,
|
| 2425 |
|
|
\SDATASELInt[9]_net_1\, N_386, \SDATASELInt[10]_net_1\,
|
| 2426 |
|
|
\SDATASELInt[8]_net_1\, \SDATASELInt[11]_net_1\,
|
| 2427 |
|
|
\SDATASELInt[4]_net_1\, \N_389\, \N_390\, \N_265\,
|
| 2428 |
|
|
\SADDRSEL[14]\, \N_395\, N_408, \SADDRSEL[13]\, N_396,
|
| 2429 |
|
|
N_404, \SADDRSEL[12]\, \SADDRSEL[8]\, \SADDRSEL[5]\,
|
| 2430 |
|
|
\SADDRSEL[4]\, \SADDRSEL[1]\, \xhdl1221[0]\,
|
| 2431 |
|
|
d_masterRegAddrSel, \regHTRANS_RNO\, \regHADDR[28]_net_1\,
|
| 2432 |
|
|
\regHADDR[31]_net_1\, N_261_i, N_383, N_376,
|
| 2433 |
|
|
\SDATASELInt[12]_net_1\, \SDATASELInt[13]_net_1\,
|
| 2434 |
|
|
\SDATASELInt[14]_net_1\, \SDATASELInt[15]_net_1\, N_382,
|
| 2435 |
|
|
\SADDRSEL[2]\, N_405, N_329, N_328,
|
| 2436 |
|
|
\SDATASELInt_RNIKCEDK[0]_net_1\, N_334, \SADDRSEL[15]\,
|
| 2437 |
|
|
\SADDRSEL[11]\, \SADDRSEL[10]\, \SADDRSEL[9]\,
|
| 2438 |
|
|
\SADDRSEL[7]\, \SADDRSEL[6]\, \SADDRSEL[3]\, \GND\, \VCC\
|
| 2439 |
|
|
: std_logic;
|
| 2440 |
|
|
|
| 2441 |
|
|
for all : COREAHBLITE_DEFAULTSLAVESM_0
|
| 2442 |
|
|
Use entity work.COREAHBLITE_DEFAULTSLAVESM_0(DEF_ARCH);
|
| 2443 |
|
|
begin
|
| 2444 |
|
|
|
| 2445 |
|
|
regHADDR_29 <= \regHADDR[31]_net_1\;
|
| 2446 |
|
|
xhdl1221_0 <= \xhdl1221[0]\;
|
| 2447 |
|
|
SDATASELInt_4 <= \SDATASELInt[5]_net_1\;
|
| 2448 |
|
|
SDATASELInt_2 <= \SDATASELInt[3]_net_1\;
|
| 2449 |
|
|
SDATASELInt_0 <= \SDATASELInt[1]_net_1\;
|
| 2450 |
|
|
xhdl1222_0 <= \xhdl1222[0]\;
|
| 2451 |
|
|
N_395 <= \N_395\;
|
| 2452 |
|
|
N_265 <= \N_265\;
|
| 2453 |
|
|
N_390 <= \N_390\;
|
| 2454 |
|
|
N_389 <= \N_389\;
|
| 2455 |
|
|
N_394 <= \N_394\;
|
| 2456 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_0 <=
|
| 2457 |
|
|
\PREVDATASLAVEREADY_iv_i_0_i_o4_0\;
|
| 2458 |
|
|
N_403 <= \N_403\;
|
| 2459 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_1 <=
|
| 2460 |
|
|
\PREVDATASLAVEREADY_iv_i_0_i_o4_1\;
|
| 2461 |
|
|
N_392 <= \N_392\;
|
| 2462 |
|
|
N_391 <= \N_391\;
|
| 2463 |
|
|
N_327 <= \N_327\;
|
| 2464 |
|
|
regHTRANS <= regHTRANS_net_1;
|
| 2465 |
|
|
masterRegAddrSel <= masterRegAddrSel_net_1;
|
| 2466 |
|
|
N_340 <= \N_340\;
|
| 2467 |
|
|
N_330 <= \N_330\;
|
| 2468 |
|
|
N_397 <= \N_397\;
|
| 2469 |
|
|
|
| 2470 |
|
|
\SDATASELInt_RNO[2]\ : NOR3B
|
| 2471 |
|
|
port map(A => \N_395\, B => N_405, C => \N_330\, Y =>
|
| 2472 |
|
|
\SADDRSEL[2]\);
|
| 2473 |
|
|
|
| 2474 |
|
|
\SDATASELInt_RNI5IBF_0[10]\ : NOR2
|
| 2475 |
|
|
port map(A => \SDATASELInt[10]_net_1\, B =>
|
| 2476 |
|
|
\SDATASELInt[8]_net_1\, Y => N_384);
|
| 2477 |
|
|
|
| 2478 |
|
|
\SDATASELInt_RNIM05H4[12]\ : NOR3C
|
| 2479 |
|
|
port map(A => \N_392\, B => \N_265\, C => N_393, Y => N_361);
|
| 2480 |
|
|
|
| 2481 |
|
|
\SDATASELInt_RNIL6TG[2]\ : XOR2
|
| 2482 |
|
|
port map(A => \SDATASELInt[7]_net_1\, B =>
|
| 2483 |
|
|
\SDATASELInt[2]_net_1\, Y => N_258_i);
|
| 2484 |
|
|
|
| 2485 |
|
|
HRDATA_4_5_0 : NOR3C
|
| 2486 |
|
|
port map(A => PRDATA_0_sqmuxa_0_a2_12, B =>
|
| 2487 |
|
|
PRDATA_0_sqmuxa_0_a2_13, C =>
|
| 2488 |
|
|
CoreAPB_0_APBmslave0_PRDATA(5), Y => \HRDATA_4_5_0\);
|
| 2489 |
|
|
|
| 2490 |
|
|
\regHADDR[30]\ : DFN1E1C0
|
| 2491 |
|
|
port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_28, CLK =>
|
| 2492 |
|
|
HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q
|
| 2493 |
|
|
=> \regHADDR[30]_net_1\);
|
| 2494 |
|
|
|
| 2495 |
|
|
\regHADDR_RNI8HAK1[29]\ : NOR2B
|
| 2496 |
|
|
port map(A => N_328, B => N_329, Y => N_408);
|
| 2497 |
|
|
|
| 2498 |
|
|
HRDATA_4_3_0 : NOR3C
|
| 2499 |
|
|
port map(A => PRDATA_0_sqmuxa_0_a2_12, B =>
|
| 2500 |
|
|
PRDATA_0_sqmuxa_0_a2_13, C =>
|
| 2501 |
|
|
CoreAPB_0_APBmslave0_PRDATA(3), Y => \HRDATA_4_3_0\);
|
| 2502 |
|
|
|
| 2503 |
|
|
\SDATASELInt_RNO[5]\ : NOR3B
|
| 2504 |
|
|
port map(A => N_396, B => N_404, C => \N_330\, Y =>
|
| 2505 |
|
|
\SADDRSEL[5]\);
|
| 2506 |
|
|
|
| 2507 |
|
|
\SDATASELInt_RNIKIGE4[3]\ : NOR2B
|
| 2508 |
|
|
port map(A => HREADY_m2_e_0_3, B => \N_392\, Y => \N_340\);
|
| 2509 |
|
|
|
| 2510 |
|
|
\regHADDR_RNI389M1[28]\ : NOR2B
|
| 2511 |
|
|
port map(A => N_254, B => \N_327\, Y => N_396);
|
| 2512 |
|
|
|
| 2513 |
|
|
d_masterRegAddrSel_0_0_o4 : OR2B
|
| 2514 |
|
|
port map(A => masterAddrInProg_i_1_0, B =>
|
| 2515 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY, Y => N_279);
|
| 2516 |
|
|
|
| 2517 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_104 : OA1
|
| 2518 |
|
|
port map(A => N_365_1, B => N_364_1, C => \N_394\, Y =>
|
| 2519 |
|
|
\PREVDATASLAVEREADY_iv_i_0_i_o4_104\);
|
| 2520 |
|
|
|
| 2521 |
|
|
\SDATASELInt_RNI2FBF_0[11]\ : NOR2
|
| 2522 |
|
|
port map(A => \SDATASELInt[11]_net_1\, B =>
|
| 2523 |
|
|
\SDATASELInt[4]_net_1\, Y => N_386);
|
| 2524 |
|
|
|
| 2525 |
|
|
SADDRSEL_m1_0_a2 : NOR2
|
| 2526 |
|
|
port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_27, B =>
|
| 2527 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_28, Y => SADDRSEL_N_3_mux);
|
| 2528 |
|
|
|
| 2529 |
|
|
\SDATASELInt_RNO[14]\ : NOR3C
|
| 2530 |
|
|
port map(A => \N_330\, B => \N_395\, C => N_408, Y =>
|
| 2531 |
|
|
\SADDRSEL[14]\);
|
| 2532 |
|
|
|
| 2533 |
|
|
\SDATASELInt_RNISQ0N8[0]\ : NOR3C
|
| 2534 |
|
|
port map(A => N_399, B => \xhdl1222[0]\, C =>
|
| 2535 |
|
|
\HRDATA_4_6_0\, Y => AHBMASTER_FIC_0_AHBmaster_HRDATA(6));
|
| 2536 |
|
|
|
| 2537 |
|
|
\SDATASELInt_RNII6HSK[1]\ : AO1
|
| 2538 |
|
|
port map(A => N_398, B => N_251, C => \N_340\, Y => N_163);
|
| 2539 |
|
|
|
| 2540 |
|
|
masterRegAddrSel_RNIJQ0M : NOR3A
|
| 2541 |
|
|
port map(A => AHBMASTER_FIC_0_AHBmaster_HTRANS_0, B =>
|
| 2542 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_26, C =>
|
| 2543 |
|
|
masterRegAddrSel_net_1, Y =>
|
| 2544 |
|
|
d_masterRegAddrSel_0_0_a2_3_1);
|
| 2545 |
|
|
|
| 2546 |
|
|
\masterRegAddrSel\ : DFN1C0
|
| 2547 |
|
|
port map(D => d_masterRegAddrSel, CLK => HCLK_c, CLR =>
|
| 2548 |
|
|
HRESETn_c, Q => masterRegAddrSel_net_1);
|
| 2549 |
|
|
|
| 2550 |
|
|
\SDATASELInt_RNITR0N8[0]\ : NOR3C
|
| 2551 |
|
|
port map(A => N_399, B => \xhdl1222[0]\, C =>
|
| 2552 |
|
|
\HRDATA_4_7_0\, Y => AHBMASTER_FIC_0_AHBmaster_HRDATA(7));
|
| 2553 |
|
|
|
| 2554 |
|
|
\regHTRANS\ : DFN1C0
|
| 2555 |
|
|
port map(D => \regHTRANS_RNO\, CLK => HCLK_c, CLR =>
|
| 2556 |
|
|
HRESETn_c, Q => regHTRANS_net_1);
|
| 2557 |
|
|
|
| 2558 |
|
|
VCC_i : VCC
|
| 2559 |
|
|
port map(Y => \VCC\);
|
| 2560 |
|
|
|
| 2561 |
|
|
\SDATASELInt_RNO[9]\ : NOR3C
|
| 2562 |
|
|
port map(A => \N_330\, B => N_396, C => \N_397\, Y =>
|
| 2563 |
|
|
\SADDRSEL[9]\);
|
| 2564 |
|
|
|
| 2565 |
|
|
\regHADDR_RNISF4Q[29]\ : MX2
|
| 2566 |
|
|
port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_27, B =>
|
| 2567 |
|
|
\regHADDR[29]_net_1\, S => masterRegAddrSel_net_1, Y =>
|
| 2568 |
|
|
N_328);
|
| 2569 |
|
|
|
| 2570 |
|
|
\SDATASELInt_RNIJRPD[12]\ : XOR2
|
| 2571 |
|
|
port map(A => \SDATASELInt[12]_net_1\, B =>
|
| 2572 |
|
|
\SDATASELInt[13]_net_1\, Y => N_261_i);
|
| 2573 |
|
|
|
| 2574 |
|
|
masterRegAddrSel_RNIUUVO3 : NOR3B
|
| 2575 |
|
|
port map(A => \N_397\, B => \N_395\, C => \N_330\, Y =>
|
| 2576 |
|
|
\xhdl1221[0]\);
|
| 2577 |
|
|
|
| 2578 |
|
|
\regHADDR[29]\ : DFN1E1C0
|
| 2579 |
|
|
port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_27, CLK =>
|
| 2580 |
|
|
HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q
|
| 2581 |
|
|
=> \regHADDR[29]_net_1\);
|
| 2582 |
|
|
|
| 2583 |
|
|
\regHADDR[24]\ : DFN1E1C0
|
| 2584 |
|
|
port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_22, CLK =>
|
| 2585 |
|
|
HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q
|
| 2586 |
|
|
=> regHADDR_22);
|
| 2587 |
|
|
|
| 2588 |
|
|
regHTRANS_RNO : OR2
|
| 2589 |
|
|
port map(A => regHTRANS_net_1, B => masterAddrClockEnable,
|
| 2590 |
|
|
Y => \regHTRANS_RNO\);
|
| 2591 |
|
|
|
| 2592 |
|
|
masterRegAddrSel_RNI24877 : NOR3B
|
| 2593 |
|
|
port map(A => \N_397\, B => d_masterRegAddrSel_0_0_a2_3_2,
|
| 2594 |
|
|
C => \N_330\, Y => d_masterRegAddrSel_0_0_a2_3_3);
|
| 2595 |
|
|
|
| 2596 |
|
|
\SDATASELInt_RNITR801[6]\ : XA1
|
| 2597 |
|
|
port map(A => \SDATASELInt[6]_net_1\, B =>
|
| 2598 |
|
|
\SDATASELInt[9]_net_1\, C => N_386, Y => N_380);
|
| 2599 |
|
|
|
| 2600 |
|
|
\SDATASELInt_RNIQO0N8[0]\ : NOR3C
|
| 2601 |
|
|
port map(A => N_399, B => \xhdl1222[0]\, C =>
|
| 2602 |
|
|
\HRDATA_4_4_0\, Y => AHBMASTER_FIC_0_AHBmaster_HRDATA(4));
|
| 2603 |
|
|
|
| 2604 |
|
|
\SDATASELInt_RNI5IBF[10]\ : XOR2
|
| 2605 |
|
|
port map(A => \SDATASELInt[10]_net_1\, B =>
|
| 2606 |
|
|
\SDATASELInt[8]_net_1\, Y => N_259_i);
|
| 2607 |
|
|
|
| 2608 |
|
|
\regHADDR_RNI4AMD[29]\ : NOR2
|
| 2609 |
|
|
port map(A => \regHADDR[29]_net_1\, B =>
|
| 2610 |
|
|
\regHADDR[30]_net_1\, Y => SADDRSEL_N_5_mux);
|
| 2611 |
|
|
|
| 2612 |
|
|
\regHADDR[28]\ : DFN1E1C0
|
| 2613 |
|
|
port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_26, CLK =>
|
| 2614 |
|
|
HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q
|
| 2615 |
|
|
=> \regHADDR[28]_net_1\);
|
| 2616 |
|
|
|
| 2617 |
|
|
\SDATASELInt_RNITTUD2[3]\ : NOR3C
|
| 2618 |
|
|
port map(A => HREADY_m2_e_0_1, B => N_255, C => \N_391\, Y
|
| 2619 |
|
|
=> HREADY_m2_e_0_3);
|
| 2620 |
|
|
|
| 2621 |
|
|
\SDATASELInt_RNIGFP7C[12]\ : OR2
|
| 2622 |
|
|
port map(A => N_361, B =>
|
| 2623 |
|
|
\PREVDATASLAVEREADY_iv_i_0_i_o4_104\, Y =>
|
| 2624 |
|
|
\PREVDATASLAVEREADY_iv_i_0_i_o4_0\);
|
| 2625 |
|
|
|
| 2626 |
|
|
\SDATASELInt_RNIARJR[14]\ : XA1
|
| 2627 |
|
|
port map(A => \SDATASELInt[15]_net_1\, B =>
|
| 2628 |
|
|
\SDATASELInt[14]_net_1\, C => N_382, Y => N_376);
|
| 2629 |
|
|
|
| 2630 |
|
|
\regHADDR[31]\ : DFN1E1C0
|
| 2631 |
|
|
port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_26, CLK =>
|
| 2632 |
|
|
HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q
|
| 2633 |
|
|
=> \regHADDR[31]_net_1\);
|
| 2634 |
|
|
|
| 2635 |
|
|
\SDATASELInt_RNO[8]\ : NOR3C
|
| 2636 |
|
|
port map(A => \N_330\, B => \N_395\, C => \N_397\, Y =>
|
| 2637 |
|
|
\SADDRSEL[8]\);
|
| 2638 |
|
|
|
| 2639 |
|
|
masterRegAddrSel_RNI7DH45 : NOR2A
|
| 2640 |
|
|
port map(A => d_masterRegAddrSel_0_0_a2_3_1, B => \N_340\,
|
| 2641 |
|
|
Y => d_masterRegAddrSel_0_0_a2_3_2);
|
| 2642 |
|
|
|
| 2643 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_a2_17 : NOR2B
|
| 2644 |
|
|
port map(A => \N_391\, B => \N_392\, Y => \N_403\);
|
| 2645 |
|
|
|
| 2646 |
|
|
masterRegAddrSel_RNI0O8LN : OA1A
|
| 2647 |
|
|
port map(A => N_398, B => \SDATASELInt_RNISKATF_0[1]_net_1\,
|
| 2648 |
|
|
C => d_masterRegAddrSel_0_0_a2_3_3, Y =>
|
| 2649 |
|
|
d_masterRegAddrSel_0_0_a2_3_4);
|
| 2650 |
|
|
|
| 2651 |
|
|
\regHADDR_RNIE36Q[31]\ : MX2
|
| 2652 |
|
|
port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_29, B =>
|
| 2653 |
|
|
\regHADDR[31]_net_1\, S => masterRegAddrSel_net_1, Y =>
|
| 2654 |
|
|
\N_330\);
|
| 2655 |
|
|
|
| 2656 |
|
|
\SDATASELInt[4]\ : DFN1E0C0
|
| 2657 |
|
|
port map(D => \SADDRSEL[4]\, CLK => HCLK_c, CLR =>
|
| 2658 |
|
|
HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q =>
|
| 2659 |
|
|
\SDATASELInt[4]_net_1\);
|
| 2660 |
|
|
|
| 2661 |
|
|
\regHADDR[2]\ : DFN1E1C0
|
| 2662 |
|
|
port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_0, CLK =>
|
| 2663 |
|
|
HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q
|
| 2664 |
|
|
=> regHADDR_0);
|
| 2665 |
|
|
|
| 2666 |
|
|
\SDATASELInt[15]\ : DFN1E0C0
|
| 2667 |
|
|
port map(D => \SADDRSEL[15]\, CLK => HCLK_c, CLR =>
|
| 2668 |
|
|
HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q =>
|
| 2669 |
|
|
\SDATASELInt[15]_net_1\);
|
| 2670 |
|
|
|
| 2671 |
|
|
masterRegAddrSel_RNO_1 : NOR3B
|
| 2672 |
|
|
port map(A => masterRegAddrSel_net_1, B => regHTRANS_net_1,
|
| 2673 |
|
|
C => \N_327\, Y => d_masterRegAddrSel_0_0_a2_0);
|
| 2674 |
|
|
|
| 2675 |
|
|
HRDATA_4_7_0 : NOR3C
|
| 2676 |
|
|
port map(A => PRDATA_0_sqmuxa_0_a2_12, B =>
|
| 2677 |
|
|
PRDATA_0_sqmuxa_0_a2_13, C =>
|
| 2678 |
|
|
CoreAPB_0_APBmslave0_PRDATA(7), Y => \HRDATA_4_7_0\);
|
| 2679 |
|
|
|
| 2680 |
|
|
HRDATA_4_0_0 : NOR3C
|
| 2681 |
|
|
port map(A => PRDATA_0_sqmuxa_0_a2_12, B =>
|
| 2682 |
|
|
PRDATA_0_sqmuxa_0_a2_13, C =>
|
| 2683 |
|
|
CoreAPB_0_APBmslave0_PRDATA(0), Y => \HRDATA_4_0_0\);
|
| 2684 |
|
|
|
| 2685 |
|
|
\SDATASELInt_RNO[6]\ : NOR3B
|
| 2686 |
|
|
port map(A => \N_395\, B => N_408, C => \N_330\, Y =>
|
| 2687 |
|
|
\SADDRSEL[6]\);
|
| 2688 |
|
|
|
| 2689 |
|
|
\SDATASELInt[14]\ : DFN1E0C0
|
| 2690 |
|
|
port map(D => \SADDRSEL[14]\, CLK => HCLK_c, CLR =>
|
| 2691 |
|
|
HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q =>
|
| 2692 |
|
|
\SDATASELInt[14]_net_1\);
|
| 2693 |
|
|
|
| 2694 |
|
|
\SDATASELInt[2]\ : DFN1E0C0
|
| 2695 |
|
|
port map(D => \SADDRSEL[2]\, CLK => HCLK_c, CLR =>
|
| 2696 |
|
|
HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q =>
|
| 2697 |
|
|
\SDATASELInt[2]_net_1\);
|
| 2698 |
|
|
|
| 2699 |
|
|
\regHADDR[25]\ : DFN1E1C0
|
| 2700 |
|
|
port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_23, CLK =>
|
| 2701 |
|
|
HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q
|
| 2702 |
|
|
=> regHADDR_23);
|
| 2703 |
|
|
|
| 2704 |
|
|
\SDATASELInt_RNI14Q11[3]\ : NOR3A
|
| 2705 |
|
|
port map(A => HREADY_m2_e_0_0, B => \SDATASELInt[5]_net_1\,
|
| 2706 |
|
|
C => \SDATASELInt[3]_net_1\, Y => HREADY_m2_e_0_1);
|
| 2707 |
|
|
|
| 2708 |
|
|
\SDATASELInt_RNO[3]\ : NOR3B
|
| 2709 |
|
|
port map(A => N_396, B => N_405, C => \N_330\, Y =>
|
| 2710 |
|
|
\SADDRSEL[3]\);
|
| 2711 |
|
|
|
| 2712 |
|
|
\SDATASELInt_RNIBLBP[1]\ : MIN3X
|
| 2713 |
|
|
port map(A => \SDATASELInt[3]_net_1\, B =>
|
| 2714 |
|
|
\SDATASELInt[5]_net_1\, C => \SDATASELInt[1]_net_1\, Y
|
| 2715 |
|
|
=> PREVDATASLAVEREADY_iv_i_0_i_o4_1_tz);
|
| 2716 |
|
|
|
| 2717 |
|
|
\SDATASELInt_RNO[11]\ : NOR3C
|
| 2718 |
|
|
port map(A => \N_330\, B => N_396, C => N_405, Y =>
|
| 2719 |
|
|
\SADDRSEL[11]\);
|
| 2720 |
|
|
|
| 2721 |
|
|
\SDATASELInt_RNIQO801_0[2]\ : NOR3A
|
| 2722 |
|
|
port map(A => N_259_i, B => \SDATASELInt[2]_net_1\, C =>
|
| 2723 |
|
|
\SDATASELInt[7]_net_1\, Y => N_377);
|
| 2724 |
|
|
|
| 2725 |
|
|
HRDATA_4_2_0 : NOR3C
|
| 2726 |
|
|
port map(A => PRDATA_0_sqmuxa_0_a2_12, B =>
|
| 2727 |
|
|
PRDATA_0_sqmuxa_0_a2_13, C =>
|
| 2728 |
|
|
CoreAPB_0_APBmslave0_PRDATA(2), Y => \HRDATA_4_2_0\);
|
| 2729 |
|
|
|
| 2730 |
|
|
\SDATASELInt_RNIC5HL3[1]\ : NOR2B
|
| 2731 |
|
|
port map(A => \N_403\, B =>
|
| 2732 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_1_tz, Y =>
|
| 2733 |
|
|
\PREVDATASLAVEREADY_iv_i_0_i_o4_1\);
|
| 2734 |
|
|
|
| 2735 |
|
|
\SDATASELInt_RNINL0N8[0]\ : NOR3C
|
| 2736 |
|
|
port map(A => N_399, B => \xhdl1222[0]\, C =>
|
| 2737 |
|
|
\HRDATA_4_1_0\, Y => AHBMASTER_FIC_0_AHBmaster_HRDATA(1));
|
| 2738 |
|
|
|
| 2739 |
|
|
GND_i : GND
|
| 2740 |
|
|
port map(Y => \GND\);
|
| 2741 |
|
|
|
| 2742 |
|
|
\SDATASELInt_RNIQO801[2]\ : NOR3A
|
| 2743 |
|
|
port map(A => N_384, B => \SDATASELInt[2]_net_1\, C =>
|
| 2744 |
|
|
\SDATASELInt[7]_net_1\, Y => \N_390\);
|
| 2745 |
|
|
|
| 2746 |
|
|
\SDATASELInt_RNIDUSG[1]\ : NOR2A
|
| 2747 |
|
|
port map(A => \xhdl1222[0]\, B => \SDATASELInt[1]_net_1\, Y
|
| 2748 |
|
|
=> HREADY_m2_e_0_0);
|
| 2749 |
|
|
|
| 2750 |
|
|
\regHADDR_RNI8HAK1_1[29]\ : NOR2A
|
| 2751 |
|
|
port map(A => N_328, B => N_329, Y => N_405);
|
| 2752 |
|
|
|
| 2753 |
|
|
\SDATASELInt[13]\ : DFN1E0C0
|
| 2754 |
|
|
port map(D => \SADDRSEL[13]\, CLK => HCLK_c, CLR =>
|
| 2755 |
|
|
HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q =>
|
| 2756 |
|
|
\SDATASELInt[13]_net_1\);
|
| 2757 |
|
|
|
| 2758 |
|
|
HREADY_M_iv_i_0_i_o4 : OR2B
|
| 2759 |
|
|
port map(A => masterDataInProg_0, B =>
|
| 2760 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY, Y => N_255);
|
| 2761 |
|
|
|
| 2762 |
|
|
\regHWRITE\ : DFN1E1C0
|
| 2763 |
|
|
port map(D => AHBMASTER_FIC_0_AHBmaster_HWRITE, CLK =>
|
| 2764 |
|
|
HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q
|
| 2765 |
|
|
=> regHWRITE);
|
| 2766 |
|
|
|
| 2767 |
|
|
\SDATASELInt_RNINVPD[14]\ : NOR2
|
| 2768 |
|
|
port map(A => \SDATASELInt[14]_net_1\, B =>
|
| 2769 |
|
|
\SDATASELInt[15]_net_1\, Y => N_383);
|
| 2770 |
|
|
|
| 2771 |
|
|
\SDATASELInt[9]\ : DFN1E0C0
|
| 2772 |
|
|
port map(D => \SADDRSEL[9]\, CLK => HCLK_c, CLR =>
|
| 2773 |
|
|
HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q =>
|
| 2774 |
|
|
\SDATASELInt[9]_net_1\);
|
| 2775 |
|
|
|
| 2776 |
|
|
\SDATASELInt[1]\ : DFN1E0C0
|
| 2777 |
|
|
port map(D => \SADDRSEL[1]\, CLK => HCLK_c, CLR =>
|
| 2778 |
|
|
HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q =>
|
| 2779 |
|
|
\SDATASELInt[1]_net_1\);
|
| 2780 |
|
|
|
| 2781 |
|
|
\SDATASELInt[12]\ : DFN1E0C0
|
| 2782 |
|
|
port map(D => \SADDRSEL[12]\, CLK => HCLK_c, CLR =>
|
| 2783 |
|
|
HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q =>
|
| 2784 |
|
|
\SDATASELInt[12]_net_1\);
|
| 2785 |
|
|
|
| 2786 |
|
|
\SDATASELInt[0]\ : DFN1E0C0
|
| 2787 |
|
|
port map(D => \xhdl1221[0]\, CLK => HCLK_c, CLR =>
|
| 2788 |
|
|
HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q =>
|
| 2789 |
|
|
\xhdl1222[0]\);
|
| 2790 |
|
|
|
| 2791 |
|
|
\SDATASELInt[5]\ : DFN1E0C0
|
| 2792 |
|
|
port map(D => \SADDRSEL[5]\, CLK => HCLK_c, CLR =>
|
| 2793 |
|
|
HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q =>
|
| 2794 |
|
|
\SDATASELInt[5]_net_1\);
|
| 2795 |
|
|
|
| 2796 |
|
|
\SDATASELInt_RNISKATF[1]\ : OR2
|
| 2797 |
|
|
port map(A => \PREVDATASLAVEREADY_iv_i_0_i_o4_1\, B =>
|
| 2798 |
|
|
\PREVDATASLAVEREADY_iv_i_0_i_o4_0\, Y => N_251);
|
| 2799 |
|
|
|
| 2800 |
|
|
\SDATASELInt_RNIPN0N8[0]\ : NOR3C
|
| 2801 |
|
|
port map(A => N_399, B => \xhdl1222[0]\, C =>
|
| 2802 |
|
|
\HRDATA_4_3_0\, Y => AHBMASTER_FIC_0_AHBmaster_HRDATA(3));
|
| 2803 |
|
|
|
| 2804 |
|
|
HRDATA_4_6_0 : NOR3C
|
| 2805 |
|
|
port map(A => PRDATA_0_sqmuxa_0_a2_12, B =>
|
| 2806 |
|
|
PRDATA_0_sqmuxa_0_a2_13, C =>
|
| 2807 |
|
|
CoreAPB_0_APBmslave0_PRDATA(6), Y => \HRDATA_4_6_0\);
|
| 2808 |
|
|
|
| 2809 |
|
|
\SDATASELInt_RNO[12]\ : NOR3C
|
| 2810 |
|
|
port map(A => \N_330\, B => \N_395\, C => N_404, Y =>
|
| 2811 |
|
|
\SADDRSEL[12]\);
|
| 2812 |
|
|
|
| 2813 |
|
|
\regHADDR[3]\ : DFN1E1C0
|
| 2814 |
|
|
port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_1, CLK =>
|
| 2815 |
|
|
HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q
|
| 2816 |
|
|
=> regHADDR_1);
|
| 2817 |
|
|
|
| 2818 |
|
|
masterRegAddrSel_RNIFIE8T : NOR2B
|
| 2819 |
|
|
port map(A => d_masterRegAddrSel_0_0_a2_3_4, B => N_279, Y
|
| 2820 |
|
|
=> masterAddrClockEnable);
|
| 2821 |
|
|
|
| 2822 |
|
|
\SDATASELInt_RNIJRPD_0[12]\ : NOR2
|
| 2823 |
|
|
port map(A => \SDATASELInt[12]_net_1\, B =>
|
| 2824 |
|
|
\SDATASELInt[13]_net_1\, Y => N_382);
|
| 2825 |
|
|
|
| 2826 |
|
|
\SDATASELInt[3]\ : DFN1E0C0
|
| 2827 |
|
|
port map(D => \SADDRSEL[3]\, CLK => HCLK_c, CLR =>
|
| 2828 |
|
|
HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q =>
|
| 2829 |
|
|
\SDATASELInt[3]_net_1\);
|
| 2830 |
|
|
|
| 2831 |
|
|
masterRegAddrSel_RNO_0 : NOR3B
|
| 2832 |
|
|
port map(A => \N_397\, B => d_masterRegAddrSel_0_0_a2_0, C
|
| 2833 |
|
|
=> \N_330\, Y => d_masterRegAddrSel_0_0_a2_1);
|
| 2834 |
|
|
|
| 2835 |
|
|
masterRegAddrSel_RNIDJG81 : MX2
|
| 2836 |
|
|
port map(A => SADDRSEL_N_3_mux, B => SADDRSEL_N_5_mux, S
|
| 2837 |
|
|
=> masterRegAddrSel_net_1, Y => \N_397\);
|
| 2838 |
|
|
|
| 2839 |
|
|
\SDATASELInt_RNO[15]\ : NOR3C
|
| 2840 |
|
|
port map(A => \N_330\, B => N_396, C => N_408, Y =>
|
| 2841 |
|
|
\SADDRSEL[15]\);
|
| 2842 |
|
|
|
| 2843 |
|
|
\SDATASELInt_RNISKATF_0[1]\ : NOR2
|
| 2844 |
|
|
port map(A => \PREVDATASLAVEREADY_iv_i_0_i_o4_1\, B =>
|
| 2845 |
|
|
\PREVDATASLAVEREADY_iv_i_0_i_o4_0\, Y =>
|
| 2846 |
|
|
\SDATASELInt_RNISKATF_0[1]_net_1\);
|
| 2847 |
|
|
|
| 2848 |
|
|
\SDATASELInt_RNIKM7N1[12]\ : AO1
|
| 2849 |
|
|
port map(A => N_261_i, B => N_383, C => N_376, Y => \N_265\);
|
| 2850 |
|
|
|
| 2851 |
|
|
\regHADDR_RNI8HAK1_0[29]\ : NOR2A
|
| 2852 |
|
|
port map(A => N_329, B => N_328, Y => N_404);
|
| 2853 |
|
|
|
| 2854 |
|
|
\SDATASELInt_RNO[13]\ : NOR3C
|
| 2855 |
|
|
port map(A => \N_330\, B => N_396, C => N_404, Y =>
|
| 2856 |
|
|
\SADDRSEL[13]\);
|
| 2857 |
|
|
|
| 2858 |
|
|
\SDATASELInt[7]\ : DFN1E0C0
|
| 2859 |
|
|
port map(D => \SADDRSEL[7]\, CLK => HCLK_c, CLR =>
|
| 2860 |
|
|
HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q =>
|
| 2861 |
|
|
\SDATASELInt[7]_net_1\);
|
| 2862 |
|
|
|
| 2863 |
|
|
\SDATASELInt_RNII3P5G[0]\ : NOR2A
|
| 2864 |
|
|
port map(A => N_251, B => \xhdl1222[0]\, Y => N_339_c);
|
| 2865 |
|
|
|
| 2866 |
|
|
\SDATASELInt_RNO[10]\ : NOR3C
|
| 2867 |
|
|
port map(A => \N_330\, B => \N_395\, C => N_405, Y =>
|
| 2868 |
|
|
\SADDRSEL[10]\);
|
| 2869 |
|
|
|
| 2870 |
|
|
\regHADDR_RNIC16Q[30]\ : MX2
|
| 2871 |
|
|
port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_28, B =>
|
| 2872 |
|
|
\regHADDR[30]_net_1\, S => masterRegAddrSel_net_1, Y =>
|
| 2873 |
|
|
N_329);
|
| 2874 |
|
|
|
| 2875 |
|
|
HRDATA_4_1_0 : NOR3C
|
| 2876 |
|
|
port map(A => PRDATA_0_sqmuxa_0_a2_12, B =>
|
| 2877 |
|
|
PRDATA_0_sqmuxa_0_a2_13, C =>
|
| 2878 |
|
|
CoreAPB_0_APBmslave0_PRDATA(1), Y => \HRDATA_4_1_0\);
|
| 2879 |
|
|
|
| 2880 |
|
|
\SDATASELInt_RNIKCEDK[0]\ : AO1
|
| 2881 |
|
|
port map(A => N_398, B => N_251, C => N_334, Y =>
|
| 2882 |
|
|
\SDATASELInt_RNIKCEDK[0]_net_1\);
|
| 2883 |
|
|
|
| 2884 |
|
|
\SDATASELInt_RNIOM0N8[0]\ : NOR3C
|
| 2885 |
|
|
port map(A => N_399, B => \xhdl1222[0]\, C =>
|
| 2886 |
|
|
\HRDATA_4_2_0\, Y => AHBMASTER_FIC_0_AHBmaster_HRDATA(2));
|
| 2887 |
|
|
|
| 2888 |
|
|
\SDATASELInt_RNIRP0N8[0]\ : NOR3C
|
| 2889 |
|
|
port map(A => N_399, B => \xhdl1222[0]\, C =>
|
| 2890 |
|
|
\HRDATA_4_5_0\, Y => AHBMASTER_FIC_0_AHBmaster_HRDATA(5));
|
| 2891 |
|
|
|
| 2892 |
|
|
\SDATASELInt_RNIMODV3[0]\ : NOR3B
|
| 2893 |
|
|
port map(A => N_399, B => \xhdl1222[0]\, C =>
|
| 2894 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY, Y => N_334);
|
| 2895 |
|
|
|
| 2896 |
|
|
\SDATASELInt_RNI2FBF[11]\ : XOR2
|
| 2897 |
|
|
port map(A => \SDATASELInt[11]_net_1\, B =>
|
| 2898 |
|
|
\SDATASELInt[4]_net_1\, Y => N_257_i);
|
| 2899 |
|
|
|
| 2900 |
|
|
\SDATASELInt[6]\ : DFN1E0C0
|
| 2901 |
|
|
port map(D => \SADDRSEL[6]\, CLK => HCLK_c, CLR =>
|
| 2902 |
|
|
HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q =>
|
| 2903 |
|
|
\SDATASELInt[6]_net_1\);
|
| 2904 |
|
|
|
| 2905 |
|
|
masterRegAddrSel_RNO : AO1
|
| 2906 |
|
|
port map(A => d_masterRegAddrSel_0_0_a2_1, B => N_279, C
|
| 2907 |
|
|
=> masterAddrClockEnable, Y => d_masterRegAddrSel);
|
| 2908 |
|
|
|
| 2909 |
|
|
HRDATA_4_4_0 : NOR3C
|
| 2910 |
|
|
port map(A => PRDATA_0_sqmuxa_0_a2_12, B =>
|
| 2911 |
|
|
PRDATA_0_sqmuxa_0_a2_13, C =>
|
| 2912 |
|
|
CoreAPB_0_APBmslave0_PRDATA(4), Y => \HRDATA_4_4_0\);
|
| 2913 |
|
|
|
| 2914 |
|
|
\regHADDR[27]\ : DFN1E1C0
|
| 2915 |
|
|
port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_25, CLK =>
|
| 2916 |
|
|
HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q
|
| 2917 |
|
|
=> regHADDR_25);
|
| 2918 |
|
|
|
| 2919 |
|
|
\regHADDR_RNI389M1_0[28]\ : NOR2A
|
| 2920 |
|
|
port map(A => N_254, B => \N_327\, Y => \N_395\);
|
| 2921 |
|
|
|
| 2922 |
|
|
\SDATASELInt_RNIMK0N8[0]\ : NOR3C
|
| 2923 |
|
|
port map(A => N_399, B => \xhdl1222[0]\, C =>
|
| 2924 |
|
|
\HRDATA_4_0_0\, Y => AHBMASTER_FIC_0_AHBmaster_HRDATA(0));
|
| 2925 |
|
|
|
| 2926 |
|
|
\SDATASELInt_RNO[4]\ : NOR3B
|
| 2927 |
|
|
port map(A => \N_395\, B => N_404, C => \N_330\, Y =>
|
| 2928 |
|
|
\SADDRSEL[4]\);
|
| 2929 |
|
|
|
| 2930 |
|
|
\SDATASELInt_RNIQO801_1[2]\ : NOR2B
|
| 2931 |
|
|
port map(A => N_258_i, B => N_384, Y => N_378);
|
| 2932 |
|
|
|
| 2933 |
|
|
\SDATASELInt[11]\ : DFN1E0C0
|
| 2934 |
|
|
port map(D => \SADDRSEL[11]\, CLK => HCLK_c, CLR =>
|
| 2935 |
|
|
HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q =>
|
| 2936 |
|
|
\SDATASELInt[11]_net_1\);
|
| 2937 |
|
|
|
| 2938 |
|
|
\SDATASELInt[8]\ : DFN1E0C0
|
| 2939 |
|
|
port map(D => \SADDRSEL[8]\, CLK => HCLK_c, CLR =>
|
| 2940 |
|
|
HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q =>
|
| 2941 |
|
|
\SDATASELInt[8]_net_1\);
|
| 2942 |
|
|
|
| 2943 |
|
|
\SDATASELInt_RNO[7]\ : NOR3B
|
| 2944 |
|
|
port map(A => N_396, B => N_408, C => \N_330\, Y =>
|
| 2945 |
|
|
\SADDRSEL[7]\);
|
| 2946 |
|
|
|
| 2947 |
|
|
\SDATASELInt_RNO[1]\ : NOR3B
|
| 2948 |
|
|
port map(A => \N_397\, B => N_396, C => \N_330\, Y =>
|
| 2949 |
|
|
\SADDRSEL[1]\);
|
| 2950 |
|
|
|
| 2951 |
|
|
\SDATASELInt_RNITR801_1[6]\ : NOR3A
|
| 2952 |
|
|
port map(A => N_257_i, B => \SDATASELInt[6]_net_1\, C =>
|
| 2953 |
|
|
\SDATASELInt[9]_net_1\, Y => N_379);
|
| 2954 |
|
|
|
| 2955 |
|
|
\regHADDR[4]\ : DFN1E1C0
|
| 2956 |
|
|
port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_2, CLK =>
|
| 2957 |
|
|
HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q
|
| 2958 |
|
|
=> regHADDR_2);
|
| 2959 |
|
|
|
| 2960 |
|
|
\regHADDR[26]\ : DFN1E1C0
|
| 2961 |
|
|
port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_24, CLK =>
|
| 2962 |
|
|
HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q
|
| 2963 |
|
|
=> regHADDR_24);
|
| 2964 |
|
|
|
| 2965 |
|
|
\SDATASELInt[10]\ : DFN1E0C0
|
| 2966 |
|
|
port map(D => \SADDRSEL[10]\, CLK => HCLK_c, CLR =>
|
| 2967 |
|
|
HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q =>
|
| 2968 |
|
|
\SDATASELInt[10]_net_1\);
|
| 2969 |
|
|
|
| 2970 |
|
|
\SDATASELInt_RNITR801_0[6]\ : NOR3A
|
| 2971 |
|
|
port map(A => N_386, B => \SDATASELInt[6]_net_1\, C =>
|
| 2972 |
|
|
\SDATASELInt[9]_net_1\, Y => \N_389\);
|
| 2973 |
|
|
|
| 2974 |
|
|
\regHADDR_RNIQD4Q[28]\ : MX2
|
| 2975 |
|
|
port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_26, B =>
|
| 2976 |
|
|
\regHADDR[28]_net_1\, S => masterRegAddrSel_net_1, Y =>
|
| 2977 |
|
|
\N_327\);
|
| 2978 |
|
|
|
| 2979 |
|
|
default_slave_sm : COREAHBLITE_DEFAULTSLAVESM_0
|
| 2980 |
|
|
port map(HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, N_382
|
| 2981 |
|
|
=> N_382, N_383 => N_383, N_390 => \N_390\, N_389 =>
|
| 2982 |
|
|
\N_389\, N_393 => N_393, N_391 => \N_391\, N_394 =>
|
| 2983 |
|
|
\N_394\, N_392 => \N_392\, N_399 => N_399,
|
| 2984 |
|
|
defSlaveSMCurrentState => defSlaveSMCurrentState);
|
| 2985 |
|
|
|
| 2986 |
|
|
|
| 2987 |
|
|
end DEF_ARCH;
|
| 2988 |
|
|
|
| 2989 |
|
|
library ieee;
|
| 2990 |
|
|
use ieee.std_logic_1164.all;
|
| 2991 |
|
|
library proasic3;
|
| 2992 |
|
|
use proasic3.all;
|
| 2993 |
|
|
|
| 2994 |
|
|
entity COREAHBLITE_MATRIX4X16 is
|
| 2995 |
|
|
|
| 2996 |
|
|
port( CoreAHBLite_0_AHBmslave0_HWDATA : out std_logic_vector(7 downto 0);
|
| 2997 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA : in std_logic_vector(7 downto 0);
|
| 2998 |
|
|
arbRegSMCurrentState_i_0_3 : out std_logic;
|
| 2999 |
|
|
arbRegSMCurrentState_i_0_0 : out std_logic;
|
| 3000 |
|
|
arbRegSMCurrentState_RNICAHF7_0 : out std_logic;
|
| 3001 |
|
|
AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : in std_logic;
|
| 3002 |
|
|
CoreAPB_0_APBmslave0_PRDATA : in std_logic_vector(7 downto 0);
|
| 3003 |
|
|
xhdl1222_0 : out std_logic;
|
| 3004 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA : out std_logic_vector(7 downto 0);
|
| 3005 |
|
|
masterAddrInProg_i_1_0 : out std_logic;
|
| 3006 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_26 : in std_logic;
|
| 3007 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_27 : in std_logic;
|
| 3008 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_28 : in std_logic;
|
| 3009 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_29 : in std_logic;
|
| 3010 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_0 : in std_logic;
|
| 3011 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_1 : in std_logic;
|
| 3012 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_2 : in std_logic;
|
| 3013 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_22 : in std_logic;
|
| 3014 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_23 : in std_logic;
|
| 3015 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_24 : in std_logic;
|
| 3016 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_25 : in std_logic;
|
| 3017 |
|
|
un4_m5_0_a3_1 : in std_logic;
|
| 3018 |
|
|
un1_m1_e_0_0 : in std_logic;
|
| 3019 |
|
|
N_364 : out std_logic;
|
| 3020 |
|
|
N_365 : out std_logic;
|
| 3021 |
|
|
HTRANS_0_a3_i_a2_4_0 : out std_logic;
|
| 3022 |
|
|
HTRANS_0_a3_i_a2_3_0 : out std_logic;
|
| 3023 |
|
|
N_323 : out std_logic;
|
| 3024 |
|
|
N_326 : out std_logic;
|
| 3025 |
|
|
N_18 : out std_logic;
|
| 3026 |
|
|
N_135 : out std_logic;
|
| 3027 |
|
|
N_20 : out std_logic;
|
| 3028 |
|
|
N_22 : out std_logic;
|
| 3029 |
|
|
N_120 : out std_logic;
|
| 3030 |
|
|
N_124 : out std_logic;
|
| 3031 |
|
|
N_128 : out std_logic;
|
| 3032 |
|
|
un4_m5_0_a3_2 : in std_logic;
|
| 3033 |
|
|
HADDR_24_0_a3_i_out : out std_logic;
|
| 3034 |
|
|
N_363 : out std_logic;
|
| 3035 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx : out std_logic;
|
| 3036 |
|
|
un1_N_11_mux_i_5_a1_1 : in std_logic;
|
| 3037 |
|
|
N_367 : out std_logic;
|
| 3038 |
|
|
N_263 : out std_logic;
|
| 3039 |
|
|
N_171 : out std_logic;
|
| 3040 |
|
|
N_398 : in std_logic;
|
| 3041 |
|
|
N_397 : out std_logic;
|
| 3042 |
|
|
N_330 : out std_logic;
|
| 3043 |
|
|
N_340 : out std_logic;
|
| 3044 |
|
|
N_327 : out std_logic;
|
| 3045 |
|
|
PRDATA_0_sqmuxa_0_a2_12 : in std_logic;
|
| 3046 |
|
|
PRDATA_0_sqmuxa_0_a2_13 : in std_logic;
|
| 3047 |
|
|
N_391 : out std_logic;
|
| 3048 |
|
|
N_392 : out std_logic;
|
| 3049 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_1 : out std_logic;
|
| 3050 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_0 : out std_logic;
|
| 3051 |
|
|
N_339_c : out std_logic;
|
| 3052 |
|
|
N_265 : out std_logic;
|
| 3053 |
|
|
N_395 : out std_logic;
|
| 3054 |
|
|
N_254 : out std_logic;
|
| 3055 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY : in std_logic;
|
| 3056 |
|
|
N_163 : out std_logic;
|
| 3057 |
|
|
HCLK_c : in std_logic;
|
| 3058 |
|
|
HRESETn_c : in std_logic;
|
| 3059 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWRITE : in std_logic;
|
| 3060 |
|
|
defSlaveSMCurrentState : out std_logic
|
| 3061 |
|
|
);
|
| 3062 |
|
|
|
| 3063 |
|
|
end COREAHBLITE_MATRIX4X16;
|
| 3064 |
|
|
|
| 3065 |
|
|
architecture DEF_ARCH of COREAHBLITE_MATRIX4X16 is
|
| 3066 |
|
|
|
| 3067 |
|
|
component COREAHBLITE_SLAVESTAGE_16
|
| 3068 |
|
|
port( xhdl1221_0 : in std_logic := 'U';
|
| 3069 |
|
|
arbRegSMCurrentState_RNICAHF7_0 : out std_logic;
|
| 3070 |
|
|
arbRegSMCurrentState_i_0_3 : out std_logic;
|
| 3071 |
|
|
arbRegSMCurrentState_i_0_0 : out std_logic;
|
| 3072 |
|
|
masterAddrInProg_i_1_0 : out std_logic;
|
| 3073 |
|
|
regHADDR_29 : in std_logic := 'U';
|
| 3074 |
|
|
regHADDR_22 : in std_logic := 'U';
|
| 3075 |
|
|
regHADDR_23 : in std_logic := 'U';
|
| 3076 |
|
|
regHADDR_24 : in std_logic := 'U';
|
| 3077 |
|
|
regHADDR_25 : in std_logic := 'U';
|
| 3078 |
|
|
regHADDR_2 : in std_logic := 'U';
|
| 3079 |
|
|
regHADDR_1 : in std_logic := 'U';
|
| 3080 |
|
|
regHADDR_0 : in std_logic := 'U';
|
| 3081 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_29 : in std_logic := 'U';
|
| 3082 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_22 : in std_logic := 'U';
|
| 3083 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_23 : in std_logic := 'U';
|
| 3084 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_24 : in std_logic := 'U';
|
| 3085 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_25 : in std_logic := 'U';
|
| 3086 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_2 : in std_logic := 'U';
|
| 3087 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_1 : in std_logic := 'U';
|
| 3088 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_0 : in std_logic := 'U';
|
| 3089 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA : in std_logic_vector(7 downto 0) := (others => 'U');
|
| 3090 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA : out std_logic_vector(7 downto 0);
|
| 3091 |
|
|
AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : in std_logic := 'U';
|
| 3092 |
|
|
masterDataInProg_0 : out std_logic;
|
| 3093 |
|
|
SDATASELInt_2 : in std_logic := 'U';
|
| 3094 |
|
|
SDATASELInt_4 : in std_logic := 'U';
|
| 3095 |
|
|
SDATASELInt_0 : in std_logic := 'U';
|
| 3096 |
|
|
N_327 : in std_logic := 'U';
|
| 3097 |
|
|
N_397 : in std_logic := 'U';
|
| 3098 |
|
|
N_330 : in std_logic := 'U';
|
| 3099 |
|
|
N_171 : out std_logic;
|
| 3100 |
|
|
N_263 : out std_logic;
|
| 3101 |
|
|
N_367 : out std_logic;
|
| 3102 |
|
|
N_403 : in std_logic := 'U';
|
| 3103 |
|
|
un1_N_11_mux_i_5_a1_1 : in std_logic := 'U';
|
| 3104 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx : out std_logic;
|
| 3105 |
|
|
N_363 : out std_logic;
|
| 3106 |
|
|
HADDR_24_0_a3_i_out : out std_logic;
|
| 3107 |
|
|
un4_m5_0_a3_2 : in std_logic := 'U';
|
| 3108 |
|
|
N_128 : out std_logic;
|
| 3109 |
|
|
N_124 : out std_logic;
|
| 3110 |
|
|
N_120 : out std_logic;
|
| 3111 |
|
|
N_22 : out std_logic;
|
| 3112 |
|
|
N_20 : out std_logic;
|
| 3113 |
|
|
N_135 : out std_logic;
|
| 3114 |
|
|
N_18 : out std_logic;
|
| 3115 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY : in std_logic := 'U';
|
| 3116 |
|
|
HRESETn_c : in std_logic := 'U';
|
| 3117 |
|
|
HCLK_c : in std_logic := 'U';
|
| 3118 |
|
|
regHWRITE : in std_logic := 'U';
|
| 3119 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWRITE : in std_logic := 'U';
|
| 3120 |
|
|
N_326 : out std_logic;
|
| 3121 |
|
|
N_323 : out std_logic;
|
| 3122 |
|
|
regHTRANS : in std_logic := 'U';
|
| 3123 |
|
|
N_389 : in std_logic := 'U';
|
| 3124 |
|
|
N_377 : in std_logic := 'U';
|
| 3125 |
|
|
N_378 : in std_logic := 'U';
|
| 3126 |
|
|
N_390 : in std_logic := 'U';
|
| 3127 |
|
|
N_379 : in std_logic := 'U';
|
| 3128 |
|
|
N_380 : in std_logic := 'U';
|
| 3129 |
|
|
HTRANS_0_a3_i_a2_3_0 : out std_logic;
|
| 3130 |
|
|
HTRANS_0_a3_i_a2_4_0 : out std_logic;
|
| 3131 |
|
|
N_392 : in std_logic := 'U';
|
| 3132 |
|
|
N_365_1 : out std_logic;
|
| 3133 |
|
|
N_365 : out std_logic;
|
| 3134 |
|
|
N_394 : in std_logic := 'U';
|
| 3135 |
|
|
N_364_1 : out std_logic;
|
| 3136 |
|
|
N_364 : out std_logic;
|
| 3137 |
|
|
N_391 : in std_logic := 'U';
|
| 3138 |
|
|
un1_m1_e_0_0 : in std_logic := 'U';
|
| 3139 |
|
|
N_393 : out std_logic;
|
| 3140 |
|
|
N_398 : in std_logic := 'U';
|
| 3141 |
|
|
masterRegAddrSel : in std_logic := 'U';
|
| 3142 |
|
|
un4_m5_0_a3_1 : in std_logic := 'U';
|
| 3143 |
|
|
N_254 : out std_logic
|
| 3144 |
|
|
);
|
| 3145 |
|
|
end component;
|
| 3146 |
|
|
|
| 3147 |
|
|
component VCC
|
| 3148 |
|
|
port( Y : out std_logic
|
| 3149 |
|
|
);
|
| 3150 |
|
|
end component;
|
| 3151 |
|
|
|
| 3152 |
|
|
component COREAHBLITE_MASTERSTAGE_1_1_0_1_0
|
| 3153 |
|
|
port( AHBMASTER_FIC_0_AHBmaster_HADDR_26 : in std_logic := 'U';
|
| 3154 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_27 : in std_logic := 'U';
|
| 3155 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_28 : in std_logic := 'U';
|
| 3156 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_29 : in std_logic := 'U';
|
| 3157 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_0 : in std_logic := 'U';
|
| 3158 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_1 : in std_logic := 'U';
|
| 3159 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_2 : in std_logic := 'U';
|
| 3160 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_22 : in std_logic := 'U';
|
| 3161 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_23 : in std_logic := 'U';
|
| 3162 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_24 : in std_logic := 'U';
|
| 3163 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_25 : in std_logic := 'U';
|
| 3164 |
|
|
regHADDR_29 : out std_logic;
|
| 3165 |
|
|
regHADDR_0 : out std_logic;
|
| 3166 |
|
|
regHADDR_1 : out std_logic;
|
| 3167 |
|
|
regHADDR_2 : out std_logic;
|
| 3168 |
|
|
regHADDR_22 : out std_logic;
|
| 3169 |
|
|
regHADDR_23 : out std_logic;
|
| 3170 |
|
|
regHADDR_24 : out std_logic;
|
| 3171 |
|
|
regHADDR_25 : out std_logic;
|
| 3172 |
|
|
masterDataInProg_0 : in std_logic := 'U';
|
| 3173 |
|
|
masterAddrInProg_i_1_0 : in std_logic := 'U';
|
| 3174 |
|
|
xhdl1221_0 : out std_logic;
|
| 3175 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA : out std_logic_vector(7 downto 0);
|
| 3176 |
|
|
SDATASELInt_4 : out std_logic;
|
| 3177 |
|
|
SDATASELInt_2 : out std_logic;
|
| 3178 |
|
|
SDATASELInt_0 : out std_logic;
|
| 3179 |
|
|
xhdl1222_0 : out std_logic;
|
| 3180 |
|
|
CoreAPB_0_APBmslave0_PRDATA : in std_logic_vector(7 downto 0) := (others => 'U');
|
| 3181 |
|
|
AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : in std_logic := 'U';
|
| 3182 |
|
|
defSlaveSMCurrentState : out std_logic;
|
| 3183 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWRITE : in std_logic := 'U';
|
| 3184 |
|
|
regHWRITE : out std_logic;
|
| 3185 |
|
|
HRESETn_c : in std_logic := 'U';
|
| 3186 |
|
|
HCLK_c : in std_logic := 'U';
|
| 3187 |
|
|
N_163 : out std_logic;
|
| 3188 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY : in std_logic := 'U';
|
| 3189 |
|
|
N_254 : in std_logic := 'U';
|
| 3190 |
|
|
N_395 : out std_logic;
|
| 3191 |
|
|
N_393 : in std_logic := 'U';
|
| 3192 |
|
|
N_265 : out std_logic;
|
| 3193 |
|
|
N_390 : out std_logic;
|
| 3194 |
|
|
N_389 : out std_logic;
|
| 3195 |
|
|
N_380 : out std_logic;
|
| 3196 |
|
|
N_379 : out std_logic;
|
| 3197 |
|
|
N_378 : out std_logic;
|
| 3198 |
|
|
N_377 : out std_logic;
|
| 3199 |
|
|
N_339_c : out std_logic;
|
| 3200 |
|
|
N_394 : out std_logic;
|
| 3201 |
|
|
N_364_1 : in std_logic := 'U';
|
| 3202 |
|
|
N_365_1 : in std_logic := 'U';
|
| 3203 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_0 : out std_logic;
|
| 3204 |
|
|
N_403 : out std_logic;
|
| 3205 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_1 : out std_logic;
|
| 3206 |
|
|
N_392 : out std_logic;
|
| 3207 |
|
|
N_391 : out std_logic;
|
| 3208 |
|
|
PRDATA_0_sqmuxa_0_a2_13 : in std_logic := 'U';
|
| 3209 |
|
|
PRDATA_0_sqmuxa_0_a2_12 : in std_logic := 'U';
|
| 3210 |
|
|
N_327 : out std_logic;
|
| 3211 |
|
|
regHTRANS : out std_logic;
|
| 3212 |
|
|
masterRegAddrSel : out std_logic;
|
| 3213 |
|
|
N_340 : out std_logic;
|
| 3214 |
|
|
N_330 : out std_logic;
|
| 3215 |
|
|
N_397 : out std_logic;
|
| 3216 |
|
|
N_398 : in std_logic := 'U'
|
| 3217 |
|
|
);
|
| 3218 |
|
|
end component;
|
| 3219 |
|
|
|
| 3220 |
|
|
component GND
|
| 3221 |
|
|
port( Y : out std_logic
|
| 3222 |
|
|
);
|
| 3223 |
|
|
end component;
|
| 3224 |
|
|
|
| 3225 |
|
|
signal \regHADDR[31]\, \regHADDR[2]\, \regHADDR[3]\,
|
| 3226 |
|
|
\regHADDR[4]\, \regHADDR[24]\, \regHADDR[25]\,
|
| 3227 |
|
|
\regHADDR[26]\, \regHADDR[27]\, \masterDataInProg[0]\,
|
| 3228 |
|
|
\masterAddrInProg_i_1[0]\, \xhdl1221[0]\,
|
| 3229 |
|
|
\SDATASELInt[5]\, \SDATASELInt[3]\, \SDATASELInt[1]\,
|
| 3230 |
|
|
regHWRITE, \N_254\, N_393, N_390, N_389, N_380, N_379,
|
| 3231 |
|
|
N_378, N_377, N_394, N_364_1, N_365_1, N_403, \N_392\,
|
| 3232 |
|
|
\N_391\, \N_327\, regHTRANS, masterRegAddrSel, \N_330\,
|
| 3233 |
|
|
\N_397\, \GND\, \VCC\ : std_logic;
|
| 3234 |
|
|
|
| 3235 |
|
|
for all : COREAHBLITE_SLAVESTAGE_16
|
| 3236 |
|
|
Use entity work.COREAHBLITE_SLAVESTAGE_16(DEF_ARCH);
|
| 3237 |
|
|
for all : COREAHBLITE_MASTERSTAGE_1_1_0_1_0
|
| 3238 |
|
|
Use entity work.COREAHBLITE_MASTERSTAGE_1_1_0_1_0(DEF_ARCH);
|
| 3239 |
|
|
begin
|
| 3240 |
|
|
|
| 3241 |
|
|
masterAddrInProg_i_1_0 <= \masterAddrInProg_i_1[0]\;
|
| 3242 |
|
|
N_397 <= \N_397\;
|
| 3243 |
|
|
N_330 <= \N_330\;
|
| 3244 |
|
|
N_327 <= \N_327\;
|
| 3245 |
|
|
N_391 <= \N_391\;
|
| 3246 |
|
|
N_392 <= \N_392\;
|
| 3247 |
|
|
N_254 <= \N_254\;
|
| 3248 |
|
|
|
| 3249 |
|
|
slavestage_0 : COREAHBLITE_SLAVESTAGE_16
|
| 3250 |
|
|
port map(xhdl1221_0 => \xhdl1221[0]\,
|
| 3251 |
|
|
arbRegSMCurrentState_RNICAHF7_0 =>
|
| 3252 |
|
|
arbRegSMCurrentState_RNICAHF7_0,
|
| 3253 |
|
|
arbRegSMCurrentState_i_0_3 => arbRegSMCurrentState_i_0_3,
|
| 3254 |
|
|
arbRegSMCurrentState_i_0_0 => arbRegSMCurrentState_i_0_0,
|
| 3255 |
|
|
masterAddrInProg_i_1_0 => \masterAddrInProg_i_1[0]\,
|
| 3256 |
|
|
regHADDR_29 => \regHADDR[31]\, regHADDR_22 =>
|
| 3257 |
|
|
\regHADDR[24]\, regHADDR_23 => \regHADDR[25]\,
|
| 3258 |
|
|
regHADDR_24 => \regHADDR[26]\, regHADDR_25 =>
|
| 3259 |
|
|
\regHADDR[27]\, regHADDR_2 => \regHADDR[4]\, regHADDR_1
|
| 3260 |
|
|
=> \regHADDR[3]\, regHADDR_0 => \regHADDR[2]\,
|
| 3261 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_29 =>
|
| 3262 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_29,
|
| 3263 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_22 =>
|
| 3264 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_22,
|
| 3265 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_23 =>
|
| 3266 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_23,
|
| 3267 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_24 =>
|
| 3268 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_24,
|
| 3269 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_25 =>
|
| 3270 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_25,
|
| 3271 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_2 =>
|
| 3272 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_2,
|
| 3273 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_1 =>
|
| 3274 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_1,
|
| 3275 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_0 =>
|
| 3276 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_0,
|
| 3277 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(7) =>
|
| 3278 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(7),
|
| 3279 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(6) =>
|
| 3280 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(6),
|
| 3281 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(5) =>
|
| 3282 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(5),
|
| 3283 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(4) =>
|
| 3284 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(4),
|
| 3285 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(3) =>
|
| 3286 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(3),
|
| 3287 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(2) =>
|
| 3288 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(2),
|
| 3289 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(1) =>
|
| 3290 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(1),
|
| 3291 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(0) =>
|
| 3292 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(0),
|
| 3293 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(7) =>
|
| 3294 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(7),
|
| 3295 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(6) =>
|
| 3296 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(6),
|
| 3297 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(5) =>
|
| 3298 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(5),
|
| 3299 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(4) =>
|
| 3300 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(4),
|
| 3301 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(3) =>
|
| 3302 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(3),
|
| 3303 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(2) =>
|
| 3304 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(2),
|
| 3305 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(1) =>
|
| 3306 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(1),
|
| 3307 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(0) =>
|
| 3308 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(0),
|
| 3309 |
|
|
AHBMASTER_FIC_0_AHBmaster_HTRANS_0 =>
|
| 3310 |
|
|
AHBMASTER_FIC_0_AHBmaster_HTRANS_0, masterDataInProg_0
|
| 3311 |
|
|
=> \masterDataInProg[0]\, SDATASELInt_2 =>
|
| 3312 |
|
|
\SDATASELInt[3]\, SDATASELInt_4 => \SDATASELInt[5]\,
|
| 3313 |
|
|
SDATASELInt_0 => \SDATASELInt[1]\, N_327 => \N_327\,
|
| 3314 |
|
|
N_397 => \N_397\, N_330 => \N_330\, N_171 => N_171, N_263
|
| 3315 |
|
|
=> N_263, N_367 => N_367, N_403 => N_403,
|
| 3316 |
|
|
un1_N_11_mux_i_5_a1_1 => un1_N_11_mux_i_5_a1_1,
|
| 3317 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx =>
|
| 3318 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx, N_363 => N_363,
|
| 3319 |
|
|
HADDR_24_0_a3_i_out => HADDR_24_0_a3_i_out, un4_m5_0_a3_2
|
| 3320 |
|
|
=> un4_m5_0_a3_2, N_128 => N_128, N_124 => N_124, N_120
|
| 3321 |
|
|
=> N_120, N_22 => N_22, N_20 => N_20, N_135 => N_135,
|
| 3322 |
|
|
N_18 => N_18, CoreAHBLite_0_AHBmslave0_HREADY =>
|
| 3323 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY, HRESETn_c => HRESETn_c,
|
| 3324 |
|
|
HCLK_c => HCLK_c, regHWRITE => regHWRITE,
|
| 3325 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWRITE =>
|
| 3326 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWRITE, N_326 => N_326, N_323
|
| 3327 |
|
|
=> N_323, regHTRANS => regHTRANS, N_389 => N_389, N_377
|
| 3328 |
|
|
=> N_377, N_378 => N_378, N_390 => N_390, N_379 => N_379,
|
| 3329 |
|
|
N_380 => N_380, HTRANS_0_a3_i_a2_3_0 =>
|
| 3330 |
|
|
HTRANS_0_a3_i_a2_3_0, HTRANS_0_a3_i_a2_4_0 =>
|
| 3331 |
|
|
HTRANS_0_a3_i_a2_4_0, N_392 => \N_392\, N_365_1 =>
|
| 3332 |
|
|
N_365_1, N_365 => N_365, N_394 => N_394, N_364_1 =>
|
| 3333 |
|
|
N_364_1, N_364 => N_364, N_391 => \N_391\, un1_m1_e_0_0
|
| 3334 |
|
|
=> un1_m1_e_0_0, N_393 => N_393, N_398 => N_398,
|
| 3335 |
|
|
masterRegAddrSel => masterRegAddrSel, un4_m5_0_a3_1 =>
|
| 3336 |
|
|
un4_m5_0_a3_1, N_254 => \N_254\);
|
| 3337 |
|
|
|
| 3338 |
|
|
VCC_i : VCC
|
| 3339 |
|
|
port map(Y => \VCC\);
|
| 3340 |
|
|
|
| 3341 |
|
|
masterstage_0 : COREAHBLITE_MASTERSTAGE_1_1_0_1_0
|
| 3342 |
|
|
port map(AHBMASTER_FIC_0_AHBmaster_HADDR_26 =>
|
| 3343 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_26,
|
| 3344 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_27 =>
|
| 3345 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_27,
|
| 3346 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_28 =>
|
| 3347 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_28,
|
| 3348 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_29 =>
|
| 3349 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_29,
|
| 3350 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_0 =>
|
| 3351 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_0,
|
| 3352 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_1 =>
|
| 3353 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_1,
|
| 3354 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_2 =>
|
| 3355 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_2,
|
| 3356 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_22 =>
|
| 3357 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_22,
|
| 3358 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_23 =>
|
| 3359 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_23,
|
| 3360 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_24 =>
|
| 3361 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_24,
|
| 3362 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_25 =>
|
| 3363 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_25, regHADDR_29 =>
|
| 3364 |
|
|
\regHADDR[31]\, regHADDR_0 => \regHADDR[2]\, regHADDR_1
|
| 3365 |
|
|
=> \regHADDR[3]\, regHADDR_2 => \regHADDR[4]\,
|
| 3366 |
|
|
regHADDR_22 => \regHADDR[24]\, regHADDR_23 =>
|
| 3367 |
|
|
\regHADDR[25]\, regHADDR_24 => \regHADDR[26]\,
|
| 3368 |
|
|
regHADDR_25 => \regHADDR[27]\, masterDataInProg_0 =>
|
| 3369 |
|
|
\masterDataInProg[0]\, masterAddrInProg_i_1_0 =>
|
| 3370 |
|
|
\masterAddrInProg_i_1[0]\, xhdl1221_0 => \xhdl1221[0]\,
|
| 3371 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(7) =>
|
| 3372 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(7),
|
| 3373 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(6) =>
|
| 3374 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(6),
|
| 3375 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(5) =>
|
| 3376 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(5),
|
| 3377 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(4) =>
|
| 3378 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(4),
|
| 3379 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(3) =>
|
| 3380 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(3),
|
| 3381 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(2) =>
|
| 3382 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(2),
|
| 3383 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(1) =>
|
| 3384 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(1),
|
| 3385 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(0) =>
|
| 3386 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(0), SDATASELInt_4 =>
|
| 3387 |
|
|
\SDATASELInt[5]\, SDATASELInt_2 => \SDATASELInt[3]\,
|
| 3388 |
|
|
SDATASELInt_0 => \SDATASELInt[1]\, xhdl1222_0 =>
|
| 3389 |
|
|
xhdl1222_0, CoreAPB_0_APBmslave0_PRDATA(7) =>
|
| 3390 |
|
|
CoreAPB_0_APBmslave0_PRDATA(7),
|
| 3391 |
|
|
CoreAPB_0_APBmslave0_PRDATA(6) =>
|
| 3392 |
|
|
CoreAPB_0_APBmslave0_PRDATA(6),
|
| 3393 |
|
|
CoreAPB_0_APBmslave0_PRDATA(5) =>
|
| 3394 |
|
|
CoreAPB_0_APBmslave0_PRDATA(5),
|
| 3395 |
|
|
CoreAPB_0_APBmslave0_PRDATA(4) =>
|
| 3396 |
|
|
CoreAPB_0_APBmslave0_PRDATA(4),
|
| 3397 |
|
|
CoreAPB_0_APBmslave0_PRDATA(3) =>
|
| 3398 |
|
|
CoreAPB_0_APBmslave0_PRDATA(3),
|
| 3399 |
|
|
CoreAPB_0_APBmslave0_PRDATA(2) =>
|
| 3400 |
|
|
CoreAPB_0_APBmslave0_PRDATA(2),
|
| 3401 |
|
|
CoreAPB_0_APBmslave0_PRDATA(1) =>
|
| 3402 |
|
|
CoreAPB_0_APBmslave0_PRDATA(1),
|
| 3403 |
|
|
CoreAPB_0_APBmslave0_PRDATA(0) =>
|
| 3404 |
|
|
CoreAPB_0_APBmslave0_PRDATA(0),
|
| 3405 |
|
|
AHBMASTER_FIC_0_AHBmaster_HTRANS_0 =>
|
| 3406 |
|
|
AHBMASTER_FIC_0_AHBmaster_HTRANS_0,
|
| 3407 |
|
|
defSlaveSMCurrentState => defSlaveSMCurrentState,
|
| 3408 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWRITE =>
|
| 3409 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWRITE, regHWRITE => regHWRITE,
|
| 3410 |
|
|
HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, N_163 => N_163,
|
| 3411 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY =>
|
| 3412 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY, N_254 => \N_254\, N_395
|
| 3413 |
|
|
=> N_395, N_393 => N_393, N_265 => N_265, N_390 => N_390,
|
| 3414 |
|
|
N_389 => N_389, N_380 => N_380, N_379 => N_379, N_378 =>
|
| 3415 |
|
|
N_378, N_377 => N_377, N_339_c => N_339_c, N_394 => N_394,
|
| 3416 |
|
|
N_364_1 => N_364_1, N_365_1 => N_365_1,
|
| 3417 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_0 =>
|
| 3418 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_0, N_403 => N_403,
|
| 3419 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_1 =>
|
| 3420 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_1, N_392 => \N_392\, N_391
|
| 3421 |
|
|
=> \N_391\, PRDATA_0_sqmuxa_0_a2_13 =>
|
| 3422 |
|
|
PRDATA_0_sqmuxa_0_a2_13, PRDATA_0_sqmuxa_0_a2_12 =>
|
| 3423 |
|
|
PRDATA_0_sqmuxa_0_a2_12, N_327 => \N_327\, regHTRANS =>
|
| 3424 |
|
|
regHTRANS, masterRegAddrSel => masterRegAddrSel, N_340
|
| 3425 |
|
|
=> N_340, N_330 => \N_330\, N_397 => \N_397\, N_398 =>
|
| 3426 |
|
|
N_398);
|
| 3427 |
|
|
|
| 3428 |
|
|
GND_i : GND
|
| 3429 |
|
|
port map(Y => \GND\);
|
| 3430 |
|
|
|
| 3431 |
|
|
|
| 3432 |
|
|
end DEF_ARCH;
|
| 3433 |
|
|
|
| 3434 |
|
|
library ieee;
|
| 3435 |
|
|
use ieee.std_logic_1164.all;
|
| 3436 |
|
|
library proasic3;
|
| 3437 |
|
|
use proasic3.all;
|
| 3438 |
|
|
|
| 3439 |
|
|
entity top_CoreAHBLite_0_CoreAHBLite is
|
| 3440 |
|
|
|
| 3441 |
|
|
port( AHBMASTER_FIC_0_AHBmaster_HADDR_26 : in std_logic;
|
| 3442 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_27 : in std_logic;
|
| 3443 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_28 : in std_logic;
|
| 3444 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_29 : in std_logic;
|
| 3445 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_0 : in std_logic;
|
| 3446 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_1 : in std_logic;
|
| 3447 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_2 : in std_logic;
|
| 3448 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_22 : in std_logic;
|
| 3449 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_23 : in std_logic;
|
| 3450 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_24 : in std_logic;
|
| 3451 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_25 : in std_logic;
|
| 3452 |
|
|
masterAddrInProg_i_1_0 : out std_logic;
|
| 3453 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA : out std_logic_vector(7 downto 0);
|
| 3454 |
|
|
xhdl1222_0 : out std_logic;
|
| 3455 |
|
|
CoreAPB_0_APBmslave0_PRDATA : in std_logic_vector(7 downto 0);
|
| 3456 |
|
|
AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : in std_logic;
|
| 3457 |
|
|
arbRegSMCurrentState_RNICAHF7_0 : out std_logic;
|
| 3458 |
|
|
arbRegSMCurrentState_i_0_3 : out std_logic;
|
| 3459 |
|
|
arbRegSMCurrentState_i_0_0 : out std_logic;
|
| 3460 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA : in std_logic_vector(7 downto 0);
|
| 3461 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA : out std_logic_vector(7 downto 0);
|
| 3462 |
|
|
defSlaveSMCurrentState : out std_logic;
|
| 3463 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWRITE : in std_logic;
|
| 3464 |
|
|
HRESETn_c : in std_logic;
|
| 3465 |
|
|
HCLK_c : in std_logic;
|
| 3466 |
|
|
N_163 : out std_logic;
|
| 3467 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY : in std_logic;
|
| 3468 |
|
|
N_254 : out std_logic;
|
| 3469 |
|
|
N_395 : out std_logic;
|
| 3470 |
|
|
N_265 : out std_logic;
|
| 3471 |
|
|
N_339_c : out std_logic;
|
| 3472 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_0 : out std_logic;
|
| 3473 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_1 : out std_logic;
|
| 3474 |
|
|
N_392 : out std_logic;
|
| 3475 |
|
|
N_391 : out std_logic;
|
| 3476 |
|
|
PRDATA_0_sqmuxa_0_a2_13 : in std_logic;
|
| 3477 |
|
|
PRDATA_0_sqmuxa_0_a2_12 : in std_logic;
|
| 3478 |
|
|
N_327 : out std_logic;
|
| 3479 |
|
|
N_340 : out std_logic;
|
| 3480 |
|
|
N_330 : out std_logic;
|
| 3481 |
|
|
N_397 : out std_logic;
|
| 3482 |
|
|
N_398 : in std_logic;
|
| 3483 |
|
|
N_171 : out std_logic;
|
| 3484 |
|
|
N_263 : out std_logic;
|
| 3485 |
|
|
N_367 : out std_logic;
|
| 3486 |
|
|
un1_N_11_mux_i_5_a1_1 : in std_logic;
|
| 3487 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx : out std_logic;
|
| 3488 |
|
|
N_363 : out std_logic;
|
| 3489 |
|
|
HADDR_24_0_a3_i_out : out std_logic;
|
| 3490 |
|
|
un4_m5_0_a3_2 : in std_logic;
|
| 3491 |
|
|
N_128 : out std_logic;
|
| 3492 |
|
|
N_124 : out std_logic;
|
| 3493 |
|
|
N_120 : out std_logic;
|
| 3494 |
|
|
N_22 : out std_logic;
|
| 3495 |
|
|
N_20 : out std_logic;
|
| 3496 |
|
|
N_135 : out std_logic;
|
| 3497 |
|
|
N_18 : out std_logic;
|
| 3498 |
|
|
N_326 : out std_logic;
|
| 3499 |
|
|
N_323 : out std_logic;
|
| 3500 |
|
|
HTRANS_0_a3_i_a2_3_0 : out std_logic;
|
| 3501 |
|
|
HTRANS_0_a3_i_a2_4_0 : out std_logic;
|
| 3502 |
|
|
N_365 : out std_logic;
|
| 3503 |
|
|
N_364 : out std_logic;
|
| 3504 |
|
|
un1_m1_e_0_0 : in std_logic;
|
| 3505 |
|
|
un4_m5_0_a3_1 : in std_logic
|
| 3506 |
|
|
);
|
| 3507 |
|
|
|
| 3508 |
|
|
end top_CoreAHBLite_0_CoreAHBLite;
|
| 3509 |
|
|
|
| 3510 |
|
|
architecture DEF_ARCH of top_CoreAHBLite_0_CoreAHBLite is
|
| 3511 |
|
|
|
| 3512 |
|
|
component COREAHBLITE_MATRIX4X16
|
| 3513 |
|
|
port( CoreAHBLite_0_AHBmslave0_HWDATA : out std_logic_vector(7 downto 0);
|
| 3514 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA : in std_logic_vector(7 downto 0) := (others => 'U');
|
| 3515 |
|
|
arbRegSMCurrentState_i_0_3 : out std_logic;
|
| 3516 |
|
|
arbRegSMCurrentState_i_0_0 : out std_logic;
|
| 3517 |
|
|
arbRegSMCurrentState_RNICAHF7_0 : out std_logic;
|
| 3518 |
|
|
AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : in std_logic := 'U';
|
| 3519 |
|
|
CoreAPB_0_APBmslave0_PRDATA : in std_logic_vector(7 downto 0) := (others => 'U');
|
| 3520 |
|
|
xhdl1222_0 : out std_logic;
|
| 3521 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA : out std_logic_vector(7 downto 0);
|
| 3522 |
|
|
masterAddrInProg_i_1_0 : out std_logic;
|
| 3523 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_26 : in std_logic := 'U';
|
| 3524 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_27 : in std_logic := 'U';
|
| 3525 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_28 : in std_logic := 'U';
|
| 3526 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_29 : in std_logic := 'U';
|
| 3527 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_0 : in std_logic := 'U';
|
| 3528 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_1 : in std_logic := 'U';
|
| 3529 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_2 : in std_logic := 'U';
|
| 3530 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_22 : in std_logic := 'U';
|
| 3531 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_23 : in std_logic := 'U';
|
| 3532 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_24 : in std_logic := 'U';
|
| 3533 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_25 : in std_logic := 'U';
|
| 3534 |
|
|
un4_m5_0_a3_1 : in std_logic := 'U';
|
| 3535 |
|
|
un1_m1_e_0_0 : in std_logic := 'U';
|
| 3536 |
|
|
N_364 : out std_logic;
|
| 3537 |
|
|
N_365 : out std_logic;
|
| 3538 |
|
|
HTRANS_0_a3_i_a2_4_0 : out std_logic;
|
| 3539 |
|
|
HTRANS_0_a3_i_a2_3_0 : out std_logic;
|
| 3540 |
|
|
N_323 : out std_logic;
|
| 3541 |
|
|
N_326 : out std_logic;
|
| 3542 |
|
|
N_18 : out std_logic;
|
| 3543 |
|
|
N_135 : out std_logic;
|
| 3544 |
|
|
N_20 : out std_logic;
|
| 3545 |
|
|
N_22 : out std_logic;
|
| 3546 |
|
|
N_120 : out std_logic;
|
| 3547 |
|
|
N_124 : out std_logic;
|
| 3548 |
|
|
N_128 : out std_logic;
|
| 3549 |
|
|
un4_m5_0_a3_2 : in std_logic := 'U';
|
| 3550 |
|
|
HADDR_24_0_a3_i_out : out std_logic;
|
| 3551 |
|
|
N_363 : out std_logic;
|
| 3552 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx : out std_logic;
|
| 3553 |
|
|
un1_N_11_mux_i_5_a1_1 : in std_logic := 'U';
|
| 3554 |
|
|
N_367 : out std_logic;
|
| 3555 |
|
|
N_263 : out std_logic;
|
| 3556 |
|
|
N_171 : out std_logic;
|
| 3557 |
|
|
N_398 : in std_logic := 'U';
|
| 3558 |
|
|
N_397 : out std_logic;
|
| 3559 |
|
|
N_330 : out std_logic;
|
| 3560 |
|
|
N_340 : out std_logic;
|
| 3561 |
|
|
N_327 : out std_logic;
|
| 3562 |
|
|
PRDATA_0_sqmuxa_0_a2_12 : in std_logic := 'U';
|
| 3563 |
|
|
PRDATA_0_sqmuxa_0_a2_13 : in std_logic := 'U';
|
| 3564 |
|
|
N_391 : out std_logic;
|
| 3565 |
|
|
N_392 : out std_logic;
|
| 3566 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_1 : out std_logic;
|
| 3567 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_0 : out std_logic;
|
| 3568 |
|
|
N_339_c : out std_logic;
|
| 3569 |
|
|
N_265 : out std_logic;
|
| 3570 |
|
|
N_395 : out std_logic;
|
| 3571 |
|
|
N_254 : out std_logic;
|
| 3572 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY : in std_logic := 'U';
|
| 3573 |
|
|
N_163 : out std_logic;
|
| 3574 |
|
|
HCLK_c : in std_logic := 'U';
|
| 3575 |
|
|
HRESETn_c : in std_logic := 'U';
|
| 3576 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWRITE : in std_logic := 'U';
|
| 3577 |
|
|
defSlaveSMCurrentState : out std_logic
|
| 3578 |
|
|
);
|
| 3579 |
|
|
end component;
|
| 3580 |
|
|
|
| 3581 |
|
|
component VCC
|
| 3582 |
|
|
port( Y : out std_logic
|
| 3583 |
|
|
);
|
| 3584 |
|
|
end component;
|
| 3585 |
|
|
|
| 3586 |
|
|
component GND
|
| 3587 |
|
|
port( Y : out std_logic
|
| 3588 |
|
|
);
|
| 3589 |
|
|
end component;
|
| 3590 |
|
|
|
| 3591 |
|
|
signal \GND\, \VCC\ : std_logic;
|
| 3592 |
|
|
|
| 3593 |
|
|
for all : COREAHBLITE_MATRIX4X16
|
| 3594 |
|
|
Use entity work.COREAHBLITE_MATRIX4X16(DEF_ARCH);
|
| 3595 |
|
|
begin
|
| 3596 |
|
|
|
| 3597 |
|
|
|
| 3598 |
|
|
matrix4x16 : COREAHBLITE_MATRIX4X16
|
| 3599 |
|
|
port map(CoreAHBLite_0_AHBmslave0_HWDATA(7) =>
|
| 3600 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(7),
|
| 3601 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(6) =>
|
| 3602 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(6),
|
| 3603 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(5) =>
|
| 3604 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(5),
|
| 3605 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(4) =>
|
| 3606 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(4),
|
| 3607 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(3) =>
|
| 3608 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(3),
|
| 3609 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(2) =>
|
| 3610 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(2),
|
| 3611 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(1) =>
|
| 3612 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(1),
|
| 3613 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(0) =>
|
| 3614 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(0),
|
| 3615 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(7) =>
|
| 3616 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(7),
|
| 3617 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(6) =>
|
| 3618 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(6),
|
| 3619 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(5) =>
|
| 3620 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(5),
|
| 3621 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(4) =>
|
| 3622 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(4),
|
| 3623 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(3) =>
|
| 3624 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(3),
|
| 3625 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(2) =>
|
| 3626 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(2),
|
| 3627 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(1) =>
|
| 3628 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(1),
|
| 3629 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(0) =>
|
| 3630 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(0),
|
| 3631 |
|
|
arbRegSMCurrentState_i_0_3 => arbRegSMCurrentState_i_0_3,
|
| 3632 |
|
|
arbRegSMCurrentState_i_0_0 => arbRegSMCurrentState_i_0_0,
|
| 3633 |
|
|
arbRegSMCurrentState_RNICAHF7_0 =>
|
| 3634 |
|
|
arbRegSMCurrentState_RNICAHF7_0,
|
| 3635 |
|
|
AHBMASTER_FIC_0_AHBmaster_HTRANS_0 =>
|
| 3636 |
|
|
AHBMASTER_FIC_0_AHBmaster_HTRANS_0,
|
| 3637 |
|
|
CoreAPB_0_APBmslave0_PRDATA(7) =>
|
| 3638 |
|
|
CoreAPB_0_APBmslave0_PRDATA(7),
|
| 3639 |
|
|
CoreAPB_0_APBmslave0_PRDATA(6) =>
|
| 3640 |
|
|
CoreAPB_0_APBmslave0_PRDATA(6),
|
| 3641 |
|
|
CoreAPB_0_APBmslave0_PRDATA(5) =>
|
| 3642 |
|
|
CoreAPB_0_APBmslave0_PRDATA(5),
|
| 3643 |
|
|
CoreAPB_0_APBmslave0_PRDATA(4) =>
|
| 3644 |
|
|
CoreAPB_0_APBmslave0_PRDATA(4),
|
| 3645 |
|
|
CoreAPB_0_APBmslave0_PRDATA(3) =>
|
| 3646 |
|
|
CoreAPB_0_APBmslave0_PRDATA(3),
|
| 3647 |
|
|
CoreAPB_0_APBmslave0_PRDATA(2) =>
|
| 3648 |
|
|
CoreAPB_0_APBmslave0_PRDATA(2),
|
| 3649 |
|
|
CoreAPB_0_APBmslave0_PRDATA(1) =>
|
| 3650 |
|
|
CoreAPB_0_APBmslave0_PRDATA(1),
|
| 3651 |
|
|
CoreAPB_0_APBmslave0_PRDATA(0) =>
|
| 3652 |
|
|
CoreAPB_0_APBmslave0_PRDATA(0), xhdl1222_0 => xhdl1222_0,
|
| 3653 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(7) =>
|
| 3654 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(7),
|
| 3655 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(6) =>
|
| 3656 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(6),
|
| 3657 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(5) =>
|
| 3658 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(5),
|
| 3659 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(4) =>
|
| 3660 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(4),
|
| 3661 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(3) =>
|
| 3662 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(3),
|
| 3663 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(2) =>
|
| 3664 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(2),
|
| 3665 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(1) =>
|
| 3666 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(1),
|
| 3667 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(0) =>
|
| 3668 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(0),
|
| 3669 |
|
|
masterAddrInProg_i_1_0 => masterAddrInProg_i_1_0,
|
| 3670 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_26 =>
|
| 3671 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_26,
|
| 3672 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_27 =>
|
| 3673 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_27,
|
| 3674 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_28 =>
|
| 3675 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_28,
|
| 3676 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_29 =>
|
| 3677 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_29,
|
| 3678 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_0 =>
|
| 3679 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_0,
|
| 3680 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_1 =>
|
| 3681 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_1,
|
| 3682 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_2 =>
|
| 3683 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_2,
|
| 3684 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_22 =>
|
| 3685 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_22,
|
| 3686 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_23 =>
|
| 3687 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_23,
|
| 3688 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_24 =>
|
| 3689 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_24,
|
| 3690 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_25 =>
|
| 3691 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_25, un4_m5_0_a3_1 =>
|
| 3692 |
|
|
un4_m5_0_a3_1, un1_m1_e_0_0 => un1_m1_e_0_0, N_364 =>
|
| 3693 |
|
|
N_364, N_365 => N_365, HTRANS_0_a3_i_a2_4_0 =>
|
| 3694 |
|
|
HTRANS_0_a3_i_a2_4_0, HTRANS_0_a3_i_a2_3_0 =>
|
| 3695 |
|
|
HTRANS_0_a3_i_a2_3_0, N_323 => N_323, N_326 => N_326,
|
| 3696 |
|
|
N_18 => N_18, N_135 => N_135, N_20 => N_20, N_22 => N_22,
|
| 3697 |
|
|
N_120 => N_120, N_124 => N_124, N_128 => N_128,
|
| 3698 |
|
|
un4_m5_0_a3_2 => un4_m5_0_a3_2, HADDR_24_0_a3_i_out =>
|
| 3699 |
|
|
HADDR_24_0_a3_i_out, N_363 => N_363,
|
| 3700 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx =>
|
| 3701 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx, un1_N_11_mux_i_5_a1_1 =>
|
| 3702 |
|
|
un1_N_11_mux_i_5_a1_1, N_367 => N_367, N_263 => N_263,
|
| 3703 |
|
|
N_171 => N_171, N_398 => N_398, N_397 => N_397, N_330 =>
|
| 3704 |
|
|
N_330, N_340 => N_340, N_327 => N_327,
|
| 3705 |
|
|
PRDATA_0_sqmuxa_0_a2_12 => PRDATA_0_sqmuxa_0_a2_12,
|
| 3706 |
|
|
PRDATA_0_sqmuxa_0_a2_13 => PRDATA_0_sqmuxa_0_a2_13, N_391
|
| 3707 |
|
|
=> N_391, N_392 => N_392,
|
| 3708 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_1 =>
|
| 3709 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_1,
|
| 3710 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_0 =>
|
| 3711 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_0, N_339_c => N_339_c,
|
| 3712 |
|
|
N_265 => N_265, N_395 => N_395, N_254 => N_254,
|
| 3713 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY =>
|
| 3714 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY, N_163 => N_163, HCLK_c
|
| 3715 |
|
|
=> HCLK_c, HRESETn_c => HRESETn_c,
|
| 3716 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWRITE =>
|
| 3717 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWRITE, defSlaveSMCurrentState
|
| 3718 |
|
|
=> defSlaveSMCurrentState);
|
| 3719 |
|
|
|
| 3720 |
|
|
VCC_i : VCC
|
| 3721 |
|
|
port map(Y => \VCC\);
|
| 3722 |
|
|
|
| 3723 |
|
|
GND_i : GND
|
| 3724 |
|
|
port map(Y => \GND\);
|
| 3725 |
|
|
|
| 3726 |
|
|
|
| 3727 |
|
|
end DEF_ARCH;
|
| 3728 |
|
|
|
| 3729 |
|
|
library ieee;
|
| 3730 |
|
|
use ieee.std_logic_1164.all;
|
| 3731 |
|
|
library proasic3;
|
| 3732 |
|
|
use proasic3.all;
|
| 3733 |
|
|
|
| 3734 |
|
|
entity top_CoreUARTapb_0_Tx_async is
|
| 3735 |
|
|
|
| 3736 |
|
|
port( tx_hold_reg : in std_logic_vector(7 downto 0);
|
| 3737 |
|
|
HRESETn_c : in std_logic;
|
| 3738 |
|
|
HCLK_c : in std_logic;
|
| 3739 |
|
|
TX_c : out std_logic;
|
| 3740 |
|
|
TXRDY : out std_logic;
|
| 3741 |
|
|
xmit_pulse : in std_logic;
|
| 3742 |
|
|
un1_csn : in std_logic
|
| 3743 |
|
|
);
|
| 3744 |
|
|
|
| 3745 |
|
|
end top_CoreUARTapb_0_Tx_async;
|
| 3746 |
|
|
|
| 3747 |
|
|
architecture DEF_ARCH of top_CoreUARTapb_0_Tx_async is
|
| 3748 |
|
|
|
| 3749 |
|
|
component DFN1E0P0
|
| 3750 |
|
|
port( D : in std_logic := 'U';
|
| 3751 |
|
|
CLK : in std_logic := 'U';
|
| 3752 |
|
|
PRE : in std_logic := 'U';
|
| 3753 |
|
|
E : in std_logic := 'U';
|
| 3754 |
|
|
Q : out std_logic
|
| 3755 |
|
|
);
|
| 3756 |
|
|
end component;
|
| 3757 |
|
|
|
| 3758 |
|
|
component NOR2B
|
| 3759 |
|
|
port( A : in std_logic := 'U';
|
| 3760 |
|
|
B : in std_logic := 'U';
|
| 3761 |
|
|
Y : out std_logic
|
| 3762 |
|
|
);
|
| 3763 |
|
|
end component;
|
| 3764 |
|
|
|
| 3765 |
|
|
component DFN1C0
|
| 3766 |
|
|
port( D : in std_logic := 'U';
|
| 3767 |
|
|
CLK : in std_logic := 'U';
|
| 3768 |
|
|
CLR : in std_logic := 'U';
|
| 3769 |
|
|
Q : out std_logic
|
| 3770 |
|
|
);
|
| 3771 |
|
|
end component;
|
| 3772 |
|
|
|
| 3773 |
|
|
component MX2
|
| 3774 |
|
|
port( A : in std_logic := 'U';
|
| 3775 |
|
|
B : in std_logic := 'U';
|
| 3776 |
|
|
S : in std_logic := 'U';
|
| 3777 |
|
|
Y : out std_logic
|
| 3778 |
|
|
);
|
| 3779 |
|
|
end component;
|
| 3780 |
|
|
|
| 3781 |
|
|
component DFN1E1C0
|
| 3782 |
|
|
port( D : in std_logic := 'U';
|
| 3783 |
|
|
CLK : in std_logic := 'U';
|
| 3784 |
|
|
CLR : in std_logic := 'U';
|
| 3785 |
|
|
E : in std_logic := 'U';
|
| 3786 |
|
|
Q : out std_logic
|
| 3787 |
|
|
);
|
| 3788 |
|
|
end component;
|
| 3789 |
|
|
|
| 3790 |
|
|
component XA1
|
| 3791 |
|
|
port( A : in std_logic := 'U';
|
| 3792 |
|
|
B : in std_logic := 'U';
|
| 3793 |
|
|
C : in std_logic := 'U';
|
| 3794 |
|
|
Y : out std_logic
|
| 3795 |
|
|
);
|
| 3796 |
|
|
end component;
|
| 3797 |
|
|
|
| 3798 |
|
|
component VCC
|
| 3799 |
|
|
port( Y : out std_logic
|
| 3800 |
|
|
);
|
| 3801 |
|
|
end component;
|
| 3802 |
|
|
|
| 3803 |
|
|
component MX2C
|
| 3804 |
|
|
port( A : in std_logic := 'U';
|
| 3805 |
|
|
B : in std_logic := 'U';
|
| 3806 |
|
|
S : in std_logic := 'U';
|
| 3807 |
|
|
Y : out std_logic
|
| 3808 |
|
|
);
|
| 3809 |
|
|
end component;
|
| 3810 |
|
|
|
| 3811 |
|
|
component NOR2A
|
| 3812 |
|
|
port( A : in std_logic := 'U';
|
| 3813 |
|
|
B : in std_logic := 'U';
|
| 3814 |
|
|
Y : out std_logic
|
| 3815 |
|
|
);
|
| 3816 |
|
|
end component;
|
| 3817 |
|
|
|
| 3818 |
|
|
component DFN1P0
|
| 3819 |
|
|
port( D : in std_logic := 'U';
|
| 3820 |
|
|
CLK : in std_logic := 'U';
|
| 3821 |
|
|
PRE : in std_logic := 'U';
|
| 3822 |
|
|
Q : out std_logic
|
| 3823 |
|
|
);
|
| 3824 |
|
|
end component;
|
| 3825 |
|
|
|
| 3826 |
|
|
component OR2A
|
| 3827 |
|
|
port( A : in std_logic := 'U';
|
| 3828 |
|
|
B : in std_logic := 'U';
|
| 3829 |
|
|
Y : out std_logic
|
| 3830 |
|
|
);
|
| 3831 |
|
|
end component;
|
| 3832 |
|
|
|
| 3833 |
|
|
component AO1C
|
| 3834 |
|
|
port( A : in std_logic := 'U';
|
| 3835 |
|
|
B : in std_logic := 'U';
|
| 3836 |
|
|
C : in std_logic := 'U';
|
| 3837 |
|
|
Y : out std_logic
|
| 3838 |
|
|
);
|
| 3839 |
|
|
end component;
|
| 3840 |
|
|
|
| 3841 |
|
|
component GND
|
| 3842 |
|
|
port( Y : out std_logic
|
| 3843 |
|
|
);
|
| 3844 |
|
|
end component;
|
| 3845 |
|
|
|
| 3846 |
|
|
component AXOI5
|
| 3847 |
|
|
port( A : in std_logic := 'U';
|
| 3848 |
|
|
B : in std_logic := 'U';
|
| 3849 |
|
|
C : in std_logic := 'U';
|
| 3850 |
|
|
Y : out std_logic
|
| 3851 |
|
|
);
|
| 3852 |
|
|
end component;
|
| 3853 |
|
|
|
| 3854 |
|
|
component NOR3A
|
| 3855 |
|
|
port( A : in std_logic := 'U';
|
| 3856 |
|
|
B : in std_logic := 'U';
|
| 3857 |
|
|
C : in std_logic := 'U';
|
| 3858 |
|
|
Y : out std_logic
|
| 3859 |
|
|
);
|
| 3860 |
|
|
end component;
|
| 3861 |
|
|
|
| 3862 |
|
|
component NOR3B
|
| 3863 |
|
|
port( A : in std_logic := 'U';
|
| 3864 |
|
|
B : in std_logic := 'U';
|
| 3865 |
|
|
C : in std_logic := 'U';
|
| 3866 |
|
|
Y : out std_logic
|
| 3867 |
|
|
);
|
| 3868 |
|
|
end component;
|
| 3869 |
|
|
|
| 3870 |
|
|
component MX2B
|
| 3871 |
|
|
port( A : in std_logic := 'U';
|
| 3872 |
|
|
B : in std_logic := 'U';
|
| 3873 |
|
|
S : in std_logic := 'U';
|
| 3874 |
|
|
Y : out std_logic
|
| 3875 |
|
|
);
|
| 3876 |
|
|
end component;
|
| 3877 |
|
|
|
| 3878 |
|
|
component INV
|
| 3879 |
|
|
port( A : in std_logic := 'U';
|
| 3880 |
|
|
Y : out std_logic
|
| 3881 |
|
|
);
|
| 3882 |
|
|
end component;
|
| 3883 |
|
|
|
| 3884 |
|
|
component NOR2
|
| 3885 |
|
|
port( A : in std_logic := 'U';
|
| 3886 |
|
|
B : in std_logic := 'U';
|
| 3887 |
|
|
Y : out std_logic
|
| 3888 |
|
|
);
|
| 3889 |
|
|
end component;
|
| 3890 |
|
|
|
| 3891 |
|
|
signal un1_csn_i, m35_0, \xmit_state_i_0[4]\,
|
| 3892 |
|
|
\xmit_state[3]_net_1\, \xmit_state_ns[0]\,
|
| 3893 |
|
|
\xmit_state[2]_net_1\, N_33, N_132, \xmit_state[5]_net_1\,
|
| 3894 |
|
|
N_4_0, \xmit_bit_sel[0]_net_1\, \xmit_bit_sel[1]_net_1\,
|
| 3895 |
|
|
N_5_0, \xmit_bit_sel[2]_net_1\, N_7_0,
|
| 3896 |
|
|
\xmit_bit_sel[3]_net_1\, N_11_0, N_14_0, N_20_0,
|
| 3897 |
|
|
\xmit_state[0]_net_1\, N_21_0, N_24_0, \xmit_state_ns[5]\,
|
| 3898 |
|
|
N_26_0, N_27_0, \xmit_state_RNO[2]_net_1\, \TXRDY\, N_41,
|
| 3899 |
|
|
N_44, N_56, N_47, N_53, N_50, \tx_byte[3]_net_1\,
|
| 3900 |
|
|
\tx_byte[7]_net_1\, \tx_byte[1]_net_1\,
|
| 3901 |
|
|
\tx_byte[5]_net_1\, i0_i, i1_i, \tx_byte[2]_net_1\,
|
| 3902 |
|
|
\tx_byte[6]_net_1\, \tx_byte[0]_net_1\,
|
| 3903 |
|
|
\tx_byte[4]_net_1\, xmit_bit_sel_e0, N_64_mux,
|
| 3904 |
|
|
\xmit_state_ns[1]\, txrdy_int_1_sqmuxa, \GND\, \VCC\
|
| 3905 |
|
|
: std_logic;
|
| 3906 |
|
|
|
| 3907 |
|
|
begin
|
| 3908 |
|
|
|
| 3909 |
|
|
TXRDY <= \TXRDY\;
|
| 3910 |
|
|
|
| 3911 |
|
|
txrdy_int : DFN1E0P0
|
| 3912 |
|
|
port map(D => un1_csn_i, CLK => HCLK_c, PRE => HRESETn_c, E
|
| 3913 |
|
|
=> txrdy_int_1_sqmuxa, Q => \TXRDY\);
|
| 3914 |
|
|
|
| 3915 |
|
|
\xmit_bit_sel_RNI5GED1[2]\ : NOR2B
|
| 3916 |
|
|
port map(A => N_4_0, B => \xmit_bit_sel[2]_net_1\, Y =>
|
| 3917 |
|
|
N_5_0);
|
| 3918 |
|
|
|
| 3919 |
|
|
\xmit_bit_sel_RNIDK9U[0]\ : NOR2B
|
| 3920 |
|
|
port map(A => \xmit_bit_sel[0]_net_1\, B =>
|
| 3921 |
|
|
\xmit_bit_sel[1]_net_1\, Y => N_4_0);
|
| 3922 |
|
|
|
| 3923 |
|
|
\xmit_state[3]\ : DFN1C0
|
| 3924 |
|
|
port map(D => N_64_mux, CLK => HCLK_c, CLR => HRESETn_c, Q
|
| 3925 |
|
|
=> \xmit_state[3]_net_1\);
|
| 3926 |
|
|
|
| 3927 |
|
|
tx_xhdl2_RNO_3 : MX2
|
| 3928 |
|
|
port map(A => N_53, B => N_50, S => \xmit_bit_sel[1]_net_1\,
|
| 3929 |
|
|
Y => N_47);
|
| 3930 |
|
|
|
| 3931 |
|
|
\tx_byte[0]\ : DFN1E1C0
|
| 3932 |
|
|
port map(D => tx_hold_reg(0), CLK => HCLK_c, CLR =>
|
| 3933 |
|
|
HRESETn_c, E => N_26_0, Q => \tx_byte[0]_net_1\);
|
| 3934 |
|
|
|
| 3935 |
|
|
\xmit_state[0]\ : DFN1C0
|
| 3936 |
|
|
port map(D => \xmit_state_ns[5]\, CLK => HCLK_c, CLR =>
|
| 3937 |
|
|
HRESETn_c, Q => \xmit_state[0]_net_1\);
|
| 3938 |
|
|
|
| 3939 |
|
|
\tx_byte[4]\ : DFN1E1C0
|
| 3940 |
|
|
port map(D => tx_hold_reg(4), CLK => HCLK_c, CLR =>
|
| 3941 |
|
|
HRESETn_c, E => N_26_0, Q => \tx_byte[4]_net_1\);
|
| 3942 |
|
|
|
| 3943 |
|
|
\xmit_bit_sel_RNO[1]\ : XA1
|
| 3944 |
|
|
port map(A => \xmit_bit_sel[1]_net_1\, B =>
|
| 3945 |
|
|
\xmit_bit_sel[0]_net_1\, C => \xmit_state[2]_net_1\, Y
|
| 3946 |
|
|
=> N_14_0);
|
| 3947 |
|
|
|
| 3948 |
|
|
VCC_i : VCC
|
| 3949 |
|
|
port map(Y => \VCC\);
|
| 3950 |
|
|
|
| 3951 |
|
|
\xmit_state_RNO_1[5]\ : MX2C
|
| 3952 |
|
|
port map(A => \TXRDY\, B => xmit_pulse, S =>
|
| 3953 |
|
|
\xmit_state[0]_net_1\, Y => N_33);
|
| 3954 |
|
|
|
| 3955 |
|
|
\tx_byte[5]\ : DFN1E1C0
|
| 3956 |
|
|
port map(D => tx_hold_reg(5), CLK => HCLK_c, CLR =>
|
| 3957 |
|
|
HRESETn_c, E => N_26_0, Q => \tx_byte[5]_net_1\);
|
| 3958 |
|
|
|
| 3959 |
|
|
\xmit_state_RNO_0[5]\ : NOR2A
|
| 3960 |
|
|
port map(A => \xmit_state_i_0[4]\, B =>
|
| 3961 |
|
|
\xmit_state[3]_net_1\, Y => m35_0);
|
| 3962 |
|
|
|
| 3963 |
|
|
\xmit_state[5]\ : DFN1P0
|
| 3964 |
|
|
port map(D => \xmit_state_ns[0]\, CLK => HCLK_c, PRE =>
|
| 3965 |
|
|
HRESETn_c, Q => \xmit_state[5]_net_1\);
|
| 3966 |
|
|
|
| 3967 |
|
|
\xmit_bit_sel_RNIUCJS1[3]\ : NOR2A
|
| 3968 |
|
|
port map(A => N_5_0, B => \xmit_bit_sel[3]_net_1\, Y =>
|
| 3969 |
|
|
N_21_0);
|
| 3970 |
|
|
|
| 3971 |
|
|
tx_xhdl2_RNO : MX2C
|
| 3972 |
|
|
port map(A => \xmit_state[3]_net_1\, B => N_44, S =>
|
| 3973 |
|
|
\xmit_state[2]_net_1\, Y => N_41);
|
| 3974 |
|
|
|
| 3975 |
|
|
\xmit_state_RNO[4]\ : OR2A
|
| 3976 |
|
|
port map(A => \xmit_state[5]_net_1\, B => \TXRDY\, Y =>
|
| 3977 |
|
|
\xmit_state_ns[1]\);
|
| 3978 |
|
|
|
| 3979 |
|
|
\xmit_state[2]\ : DFN1C0
|
| 3980 |
|
|
port map(D => \xmit_state_RNO[2]_net_1\, CLK => HCLK_c, CLR
|
| 3981 |
|
|
=> HRESETn_c, Q => \xmit_state[2]_net_1\);
|
| 3982 |
|
|
|
| 3983 |
|
|
\xmit_bit_sel[3]\ : DFN1E1C0
|
| 3984 |
|
|
port map(D => N_7_0, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 3985 |
|
|
xmit_pulse, Q => \xmit_bit_sel[3]_net_1\);
|
| 3986 |
|
|
|
| 3987 |
|
|
\xmit_state_RNO_0[0]\ : NOR2A
|
| 3988 |
|
|
port map(A => \xmit_state[0]_net_1\, B => xmit_pulse, Y =>
|
| 3989 |
|
|
N_20_0);
|
| 3990 |
|
|
|
| 3991 |
|
|
tx_xhdl2_RNO_1 : MX2
|
| 3992 |
|
|
port map(A => N_56, B => N_47, S => \xmit_bit_sel[0]_net_1\,
|
| 3993 |
|
|
Y => N_44);
|
| 3994 |
|
|
|
| 3995 |
|
|
tx_xhdl2 : DFN1E0P0
|
| 3996 |
|
|
port map(D => N_41, CLK => HCLK_c, PRE => HRESETn_c, E =>
|
| 3997 |
|
|
N_132, Q => TX_c);
|
| 3998 |
|
|
|
| 3999 |
|
|
\xmit_bit_sel[2]\ : DFN1E1C0
|
| 4000 |
|
|
port map(D => N_11_0, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 4001 |
|
|
=> xmit_pulse, Q => \xmit_bit_sel[2]_net_1\);
|
| 4002 |
|
|
|
| 4003 |
|
|
\tx_byte[3]\ : DFN1E1C0
|
| 4004 |
|
|
port map(D => tx_hold_reg(3), CLK => HCLK_c, CLR =>
|
| 4005 |
|
|
HRESETn_c, E => N_26_0, Q => \tx_byte[3]_net_1\);
|
| 4006 |
|
|
|
| 4007 |
|
|
\xmit_state_RNO_1[0]\ : MX2
|
| 4008 |
|
|
port map(A => \xmit_state[0]_net_1\, B => N_21_0, S =>
|
| 4009 |
|
|
xmit_pulse, Y => N_24_0);
|
| 4010 |
|
|
|
| 4011 |
|
|
\tx_byte[7]\ : DFN1E1C0
|
| 4012 |
|
|
port map(D => tx_hold_reg(7), CLK => HCLK_c, CLR =>
|
| 4013 |
|
|
HRESETn_c, E => N_26_0, Q => \tx_byte[7]_net_1\);
|
| 4014 |
|
|
|
| 4015 |
|
|
\xmit_state_RNIEME51[3]\ : NOR2B
|
| 4016 |
|
|
port map(A => \xmit_state[3]_net_1\, B => xmit_pulse, Y =>
|
| 4017 |
|
|
N_26_0);
|
| 4018 |
|
|
|
| 4019 |
|
|
\xmit_state_RNO[3]\ : AO1C
|
| 4020 |
|
|
port map(A => xmit_pulse, B => \xmit_state[3]_net_1\, C =>
|
| 4021 |
|
|
\xmit_state_i_0[4]\, Y => N_64_mux);
|
| 4022 |
|
|
|
| 4023 |
|
|
GND_i : GND
|
| 4024 |
|
|
port map(Y => \GND\);
|
| 4025 |
|
|
|
| 4026 |
|
|
\xmit_bit_sel_RNO[2]\ : XA1
|
| 4027 |
|
|
port map(A => \xmit_bit_sel[2]_net_1\, B => N_4_0, C =>
|
| 4028 |
|
|
\xmit_state[2]_net_1\, Y => N_11_0);
|
| 4029 |
|
|
|
| 4030 |
|
|
\xmit_state_RNO[0]\ : MX2
|
| 4031 |
|
|
port map(A => N_20_0, B => N_24_0, S =>
|
| 4032 |
|
|
\xmit_state[2]_net_1\, Y => \xmit_state_ns[5]\);
|
| 4033 |
|
|
|
| 4034 |
|
|
\xmit_bit_sel_RNO[0]\ : AXOI5
|
| 4035 |
|
|
port map(A => \xmit_state[2]_net_1\, B => xmit_pulse, C =>
|
| 4036 |
|
|
\xmit_bit_sel[0]_net_1\, Y => xmit_bit_sel_e0);
|
| 4037 |
|
|
|
| 4038 |
|
|
tx_xhdl2_RNO_0 : NOR3A
|
| 4039 |
|
|
port map(A => \xmit_state_i_0[4]\, B =>
|
| 4040 |
|
|
\xmit_state[5]_net_1\, C => xmit_pulse, Y => N_132);
|
| 4041 |
|
|
|
| 4042 |
|
|
tx_xhdl2_RNO_4 : MX2C
|
| 4043 |
|
|
port map(A => \tx_byte[0]_net_1\, B => \tx_byte[4]_net_1\,
|
| 4044 |
|
|
S => \xmit_bit_sel[2]_net_1\, Y => i0_i);
|
| 4045 |
|
|
|
| 4046 |
|
|
tx_xhdl2_RNO_2 : MX2
|
| 4047 |
|
|
port map(A => i0_i, B => i1_i, S => \xmit_bit_sel[1]_net_1\,
|
| 4048 |
|
|
Y => N_56);
|
| 4049 |
|
|
|
| 4050 |
|
|
\xmit_state_RNO[5]\ : NOR3A
|
| 4051 |
|
|
port map(A => m35_0, B => \xmit_state[2]_net_1\, C => N_33,
|
| 4052 |
|
|
Y => \xmit_state_ns[0]\);
|
| 4053 |
|
|
|
| 4054 |
|
|
tx_xhdl2_RNO_5 : MX2C
|
| 4055 |
|
|
port map(A => \tx_byte[2]_net_1\, B => \tx_byte[6]_net_1\,
|
| 4056 |
|
|
S => \xmit_bit_sel[2]_net_1\, Y => i1_i);
|
| 4057 |
|
|
|
| 4058 |
|
|
\tx_byte[6]\ : DFN1E1C0
|
| 4059 |
|
|
port map(D => tx_hold_reg(6), CLK => HCLK_c, CLR =>
|
| 4060 |
|
|
HRESETn_c, E => N_26_0, Q => \tx_byte[6]_net_1\);
|
| 4061 |
|
|
|
| 4062 |
|
|
\xmit_bit_sel[1]\ : DFN1E1C0
|
| 4063 |
|
|
port map(D => N_14_0, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 4064 |
|
|
=> xmit_pulse, Q => \xmit_bit_sel[1]_net_1\);
|
| 4065 |
|
|
|
| 4066 |
|
|
\xmit_state_RNO_0[2]\ : NOR3B
|
| 4067 |
|
|
port map(A => xmit_pulse, B => N_21_0, C =>
|
| 4068 |
|
|
\xmit_state[3]_net_1\, Y => N_27_0);
|
| 4069 |
|
|
|
| 4070 |
|
|
\xmit_bit_sel[0]\ : DFN1C0
|
| 4071 |
|
|
port map(D => xmit_bit_sel_e0, CLK => HCLK_c, CLR =>
|
| 4072 |
|
|
HRESETn_c, Q => \xmit_bit_sel[0]_net_1\);
|
| 4073 |
|
|
|
| 4074 |
|
|
\xmit_state_RNO[2]\ : MX2B
|
| 4075 |
|
|
port map(A => N_26_0, B => N_27_0, S =>
|
| 4076 |
|
|
\xmit_state[2]_net_1\, Y => \xmit_state_RNO[2]_net_1\);
|
| 4077 |
|
|
|
| 4078 |
|
|
\tx_byte[2]\ : DFN1E1C0
|
| 4079 |
|
|
port map(D => tx_hold_reg(2), CLK => HCLK_c, CLR =>
|
| 4080 |
|
|
HRESETn_c, E => N_26_0, Q => \tx_byte[2]_net_1\);
|
| 4081 |
|
|
|
| 4082 |
|
|
txrdy_int_RNO : INV
|
| 4083 |
|
|
port map(A => un1_csn, Y => un1_csn_i);
|
| 4084 |
|
|
|
| 4085 |
|
|
tx_xhdl2_RNO_7 : MX2C
|
| 4086 |
|
|
port map(A => \tx_byte[3]_net_1\, B => \tx_byte[7]_net_1\,
|
| 4087 |
|
|
S => \xmit_bit_sel[2]_net_1\, Y => N_50);
|
| 4088 |
|
|
|
| 4089 |
|
|
\tx_byte[1]\ : DFN1E1C0
|
| 4090 |
|
|
port map(D => tx_hold_reg(1), CLK => HCLK_c, CLR =>
|
| 4091 |
|
|
HRESETn_c, E => N_26_0, Q => \tx_byte[1]_net_1\);
|
| 4092 |
|
|
|
| 4093 |
|
|
\xmit_state[4]\ : DFN1P0
|
| 4094 |
|
|
port map(D => \xmit_state_ns[1]\, CLK => HCLK_c, PRE =>
|
| 4095 |
|
|
HRESETn_c, Q => \xmit_state_i_0[4]\);
|
| 4096 |
|
|
|
| 4097 |
|
|
\xmit_bit_sel_RNO[3]\ : XA1
|
| 4098 |
|
|
port map(A => \xmit_bit_sel[3]_net_1\, B => N_5_0, C =>
|
| 4099 |
|
|
\xmit_state[2]_net_1\, Y => N_7_0);
|
| 4100 |
|
|
|
| 4101 |
|
|
txrdy_int_RNO_0 : NOR2
|
| 4102 |
|
|
port map(A => N_26_0, B => un1_csn, Y => txrdy_int_1_sqmuxa);
|
| 4103 |
|
|
|
| 4104 |
|
|
tx_xhdl2_RNO_6 : MX2C
|
| 4105 |
|
|
port map(A => \tx_byte[1]_net_1\, B => \tx_byte[5]_net_1\,
|
| 4106 |
|
|
S => \xmit_bit_sel[2]_net_1\, Y => N_53);
|
| 4107 |
|
|
|
| 4108 |
|
|
|
| 4109 |
|
|
end DEF_ARCH;
|
| 4110 |
|
|
|
| 4111 |
|
|
library ieee;
|
| 4112 |
|
|
use ieee.std_logic_1164.all;
|
| 4113 |
|
|
library proasic3;
|
| 4114 |
|
|
use proasic3.all;
|
| 4115 |
|
|
|
| 4116 |
|
|
entity top_CoreUARTapb_0_Clock_gen is
|
| 4117 |
|
|
|
| 4118 |
|
|
port( HRESETn_c : in std_logic;
|
| 4119 |
|
|
HCLK_c : in std_logic;
|
| 4120 |
|
|
baud_clock : out std_logic;
|
| 4121 |
|
|
xmit_pulse : out std_logic
|
| 4122 |
|
|
);
|
| 4123 |
|
|
|
| 4124 |
|
|
end top_CoreUARTapb_0_Clock_gen;
|
| 4125 |
|
|
|
| 4126 |
|
|
architecture DEF_ARCH of top_CoreUARTapb_0_Clock_gen is
|
| 4127 |
|
|
|
| 4128 |
|
|
component OR3
|
| 4129 |
|
|
port( A : in std_logic := 'U';
|
| 4130 |
|
|
B : in std_logic := 'U';
|
| 4131 |
|
|
C : in std_logic := 'U';
|
| 4132 |
|
|
Y : out std_logic
|
| 4133 |
|
|
);
|
| 4134 |
|
|
end component;
|
| 4135 |
|
|
|
| 4136 |
|
|
component NOR2B
|
| 4137 |
|
|
port( A : in std_logic := 'U';
|
| 4138 |
|
|
B : in std_logic := 'U';
|
| 4139 |
|
|
Y : out std_logic
|
| 4140 |
|
|
);
|
| 4141 |
|
|
end component;
|
| 4142 |
|
|
|
| 4143 |
|
|
component DFN1C0
|
| 4144 |
|
|
port( D : in std_logic := 'U';
|
| 4145 |
|
|
CLK : in std_logic := 'U';
|
| 4146 |
|
|
CLR : in std_logic := 'U';
|
| 4147 |
|
|
Q : out std_logic
|
| 4148 |
|
|
);
|
| 4149 |
|
|
end component;
|
| 4150 |
|
|
|
| 4151 |
|
|
component AX1C
|
| 4152 |
|
|
port( A : in std_logic := 'U';
|
| 4153 |
|
|
B : in std_logic := 'U';
|
| 4154 |
|
|
C : in std_logic := 'U';
|
| 4155 |
|
|
Y : out std_logic
|
| 4156 |
|
|
);
|
| 4157 |
|
|
end component;
|
| 4158 |
|
|
|
| 4159 |
|
|
component XNOR2
|
| 4160 |
|
|
port( A : in std_logic := 'U';
|
| 4161 |
|
|
B : in std_logic := 'U';
|
| 4162 |
|
|
Y : out std_logic
|
| 4163 |
|
|
);
|
| 4164 |
|
|
end component;
|
| 4165 |
|
|
|
| 4166 |
|
|
component NOR2A
|
| 4167 |
|
|
port( A : in std_logic := 'U';
|
| 4168 |
|
|
B : in std_logic := 'U';
|
| 4169 |
|
|
Y : out std_logic
|
| 4170 |
|
|
);
|
| 4171 |
|
|
end component;
|
| 4172 |
|
|
|
| 4173 |
|
|
component DFN1E1C0
|
| 4174 |
|
|
port( D : in std_logic := 'U';
|
| 4175 |
|
|
CLK : in std_logic := 'U';
|
| 4176 |
|
|
CLR : in std_logic := 'U';
|
| 4177 |
|
|
E : in std_logic := 'U';
|
| 4178 |
|
|
Q : out std_logic
|
| 4179 |
|
|
);
|
| 4180 |
|
|
end component;
|
| 4181 |
|
|
|
| 4182 |
|
|
component NOR3A
|
| 4183 |
|
|
port( A : in std_logic := 'U';
|
| 4184 |
|
|
B : in std_logic := 'U';
|
| 4185 |
|
|
C : in std_logic := 'U';
|
| 4186 |
|
|
Y : out std_logic
|
| 4187 |
|
|
);
|
| 4188 |
|
|
end component;
|
| 4189 |
|
|
|
| 4190 |
|
|
component NOR2
|
| 4191 |
|
|
port( A : in std_logic := 'U';
|
| 4192 |
|
|
B : in std_logic := 'U';
|
| 4193 |
|
|
Y : out std_logic
|
| 4194 |
|
|
);
|
| 4195 |
|
|
end component;
|
| 4196 |
|
|
|
| 4197 |
|
|
component OR2
|
| 4198 |
|
|
port( A : in std_logic := 'U';
|
| 4199 |
|
|
B : in std_logic := 'U';
|
| 4200 |
|
|
Y : out std_logic
|
| 4201 |
|
|
);
|
| 4202 |
|
|
end component;
|
| 4203 |
|
|
|
| 4204 |
|
|
component XOR2
|
| 4205 |
|
|
port( A : in std_logic := 'U';
|
| 4206 |
|
|
B : in std_logic := 'U';
|
| 4207 |
|
|
Y : out std_logic
|
| 4208 |
|
|
);
|
| 4209 |
|
|
end component;
|
| 4210 |
|
|
|
| 4211 |
|
|
component VCC
|
| 4212 |
|
|
port( Y : out std_logic
|
| 4213 |
|
|
);
|
| 4214 |
|
|
end component;
|
| 4215 |
|
|
|
| 4216 |
|
|
component NOR3
|
| 4217 |
|
|
port( A : in std_logic := 'U';
|
| 4218 |
|
|
B : in std_logic := 'U';
|
| 4219 |
|
|
C : in std_logic := 'U';
|
| 4220 |
|
|
Y : out std_logic
|
| 4221 |
|
|
);
|
| 4222 |
|
|
end component;
|
| 4223 |
|
|
|
| 4224 |
|
|
component NOR3C
|
| 4225 |
|
|
port( A : in std_logic := 'U';
|
| 4226 |
|
|
B : in std_logic := 'U';
|
| 4227 |
|
|
C : in std_logic := 'U';
|
| 4228 |
|
|
Y : out std_logic
|
| 4229 |
|
|
);
|
| 4230 |
|
|
end component;
|
| 4231 |
|
|
|
| 4232 |
|
|
component GND
|
| 4233 |
|
|
port( Y : out std_logic
|
| 4234 |
|
|
);
|
| 4235 |
|
|
end component;
|
| 4236 |
|
|
|
| 4237 |
|
|
component OR2A
|
| 4238 |
|
|
port( A : in std_logic := 'U';
|
| 4239 |
|
|
B : in std_logic := 'U';
|
| 4240 |
|
|
Y : out std_logic
|
| 4241 |
|
|
);
|
| 4242 |
|
|
end component;
|
| 4243 |
|
|
|
| 4244 |
|
|
signal N_12, \baud_cntr[1]_net_1\, \baud_cntr[0]_net_1\,
|
| 4245 |
|
|
N_10, \baud_cntr[3]_net_1\, \DWACT_FDEC_E[0]\, N_5,
|
| 4246 |
|
|
\baud_cntr[8]_net_1\, \DWACT_FDEC_E[4]\, N_2,
|
| 4247 |
|
|
\DWACT_FDEC_E[7]\, \DWACT_FDEC_E[6]\, un2_baud_cntr_9,
|
| 4248 |
|
|
un2_baud_cntr_6, \baud_cntr[9]_net_1\, un2_baud_cntr_8,
|
| 4249 |
|
|
un2_baud_cntr_4, \baud_cntr[4]_net_1\, un2_baud_cntr_7,
|
| 4250 |
|
|
un2_baud_cntr_2, \baud_cntr[5]_net_1\,
|
| 4251 |
|
|
\baud_cntr[2]_net_1\, \baud_cntr[11]_net_1\,
|
| 4252 |
|
|
\baud_cntr[12]_net_1\, \baud_cntr[6]_net_1\,
|
| 4253 |
|
|
\baud_cntr[7]_net_1\, \baud_cntr[10]_net_1\,
|
| 4254 |
|
|
un2_baud_cntr, un8_baud_clock_int, \xmit_cntr[2]_net_1\,
|
| 4255 |
|
|
\xmit_cntr[3]_net_1\, xmit_cntr_c1, \baud_clock\,
|
| 4256 |
|
|
\xmit_clock\, xmit_cntr_n1, \xmit_cntr[0]_net_1\,
|
| 4257 |
|
|
\xmit_cntr[1]_net_1\, xmit_cntr_n2, xmit_cntr_n3,
|
| 4258 |
|
|
xmit_cntr_e0, \baud_cntr_4[12]\, \baud_cntr_3[12]\,
|
| 4259 |
|
|
\baud_cntr_4[11]\, \baud_cntr_3[11]\, \baud_cntr_4[10]\,
|
| 4260 |
|
|
\baud_cntr_3[10]\, \baud_cntr_4[9]\, \baud_cntr_3[9]\,
|
| 4261 |
|
|
\baud_cntr_4[8]\, \baud_cntr_3[8]\, \baud_cntr_4[7]\,
|
| 4262 |
|
|
\baud_cntr_3[7]\, \baud_cntr_4[6]\, \baud_cntr_3[6]\,
|
| 4263 |
|
|
\baud_cntr_4[5]\, \baud_cntr_3[5]\, \baud_cntr_4[4]\,
|
| 4264 |
|
|
\baud_cntr_3[4]\, \baud_cntr_4[3]\, \baud_cntr_3[3]\,
|
| 4265 |
|
|
\baud_cntr_4[2]\, \baud_cntr_3[2]\, \baud_cntr_4[1]\,
|
| 4266 |
|
|
\baud_cntr_3[1]\, \baud_cntr_4[0]\, N_3,
|
| 4267 |
|
|
\DWACT_FDEC_E[2]\, \DWACT_FDEC_E[5]\, N_4,
|
| 4268 |
|
|
\DWACT_FDEC_E[3]\, N_6, N_7, N_8, \DWACT_FDEC_E[1]\, N_9,
|
| 4269 |
|
|
N_11, \GND\, \VCC\ : std_logic;
|
| 4270 |
|
|
|
| 4271 |
|
|
begin
|
| 4272 |
|
|
|
| 4273 |
|
|
baud_clock <= \baud_clock\;
|
| 4274 |
|
|
|
| 4275 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_19\ : OR3
|
| 4276 |
|
|
port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C
|
| 4277 |
|
|
=> \baud_cntr[6]_net_1\, Y => N_7);
|
| 4278 |
|
|
|
| 4279 |
|
|
xmit_clock_RNIMD3T : NOR2B
|
| 4280 |
|
|
port map(A => \baud_clock\, B => \xmit_clock\, Y =>
|
| 4281 |
|
|
xmit_pulse);
|
| 4282 |
|
|
|
| 4283 |
|
|
\baud_cntr[7]\ : DFN1C0
|
| 4284 |
|
|
port map(D => \baud_cntr_4[7]\, CLK => HCLK_c, CLR =>
|
| 4285 |
|
|
HRESETn_c, Q => \baud_cntr[7]_net_1\);
|
| 4286 |
|
|
|
| 4287 |
|
|
\xmit_cntr_RNO[3]\ : AX1C
|
| 4288 |
|
|
port map(A => \xmit_cntr[2]_net_1\, B => xmit_cntr_c1, C
|
| 4289 |
|
|
=> \xmit_cntr[3]_net_1\, Y => xmit_cntr_n3);
|
| 4290 |
|
|
|
| 4291 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_5\ : XNOR2
|
| 4292 |
|
|
port map(A => \baud_cntr[0]_net_1\, B =>
|
| 4293 |
|
|
\baud_cntr[1]_net_1\, Y => \baud_cntr_3[1]\);
|
| 4294 |
|
|
|
| 4295 |
|
|
\baud_cntr[0]\ : DFN1C0
|
| 4296 |
|
|
port map(D => \baud_cntr_4[0]\, CLK => HCLK_c, CLR =>
|
| 4297 |
|
|
HRESETn_c, Q => \baud_cntr[0]_net_1\);
|
| 4298 |
|
|
|
| 4299 |
|
|
\baud_cntr_RNO[7]\ : NOR2A
|
| 4300 |
|
|
port map(A => \baud_cntr_3[7]\, B => un2_baud_cntr, Y =>
|
| 4301 |
|
|
\baud_cntr_4[7]\);
|
| 4302 |
|
|
|
| 4303 |
|
|
\baud_cntr[9]\ : DFN1C0
|
| 4304 |
|
|
port map(D => \baud_cntr_4[9]\, CLK => HCLK_c, CLR =>
|
| 4305 |
|
|
HRESETn_c, Q => \baud_cntr[9]_net_1\);
|
| 4306 |
|
|
|
| 4307 |
|
|
\xmit_cntr[3]\ : DFN1E1C0
|
| 4308 |
|
|
port map(D => xmit_cntr_n3, CLK => HCLK_c, CLR => HRESETn_c,
|
| 4309 |
|
|
E => \baud_clock\, Q => \xmit_cntr[3]_net_1\);
|
| 4310 |
|
|
|
| 4311 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_13\ : OR3
|
| 4312 |
|
|
port map(A => \DWACT_FDEC_E[0]\, B => \baud_cntr[3]_net_1\,
|
| 4313 |
|
|
C => \baud_cntr[4]_net_1\, Y => N_9);
|
| 4314 |
|
|
|
| 4315 |
|
|
\baud_cntr_RNINP0G1[2]\ : NOR3A
|
| 4316 |
|
|
port map(A => un2_baud_cntr_2, B => \baud_cntr[5]_net_1\, C
|
| 4317 |
|
|
=> \baud_cntr[2]_net_1\, Y => un2_baud_cntr_7);
|
| 4318 |
|
|
|
| 4319 |
|
|
\baud_cntr_RNI434N[10]\ : NOR2
|
| 4320 |
|
|
port map(A => \baud_cntr[7]_net_1\, B =>
|
| 4321 |
|
|
\baud_cntr[10]_net_1\, Y => un2_baud_cntr_2);
|
| 4322 |
|
|
|
| 4323 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_33\ : OR3
|
| 4324 |
|
|
port map(A => \baud_cntr[9]_net_1\, B =>
|
| 4325 |
|
|
\baud_cntr[10]_net_1\, C => \baud_cntr[11]_net_1\, Y =>
|
| 4326 |
|
|
\DWACT_FDEC_E[7]\);
|
| 4327 |
|
|
|
| 4328 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_24\ : OR3
|
| 4329 |
|
|
port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C
|
| 4330 |
|
|
=> \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\);
|
| 4331 |
|
|
|
| 4332 |
|
|
\baud_cntr_RNO[1]\ : NOR2A
|
| 4333 |
|
|
port map(A => \baud_cntr_3[1]\, B => un2_baud_cntr, Y =>
|
| 4334 |
|
|
\baud_cntr_4[1]\);
|
| 4335 |
|
|
|
| 4336 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_25\ : OR2
|
| 4337 |
|
|
port map(A => \baud_cntr[8]_net_1\, B => \DWACT_FDEC_E[4]\,
|
| 4338 |
|
|
Y => N_5);
|
| 4339 |
|
|
|
| 4340 |
|
|
\xmit_cntr_RNO[2]\ : XOR2
|
| 4341 |
|
|
port map(A => xmit_cntr_c1, B => \xmit_cntr[2]_net_1\, Y
|
| 4342 |
|
|
=> xmit_cntr_n2);
|
| 4343 |
|
|
|
| 4344 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_26\ : XNOR2
|
| 4345 |
|
|
port map(A => N_5, B => \baud_cntr[9]_net_1\, Y =>
|
| 4346 |
|
|
\baud_cntr_3[9]\);
|
| 4347 |
|
|
|
| 4348 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_12\ : XNOR2
|
| 4349 |
|
|
port map(A => N_10, B => \baud_cntr[4]_net_1\, Y =>
|
| 4350 |
|
|
\baud_cntr_3[4]\);
|
| 4351 |
|
|
|
| 4352 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_32\ : XNOR2
|
| 4353 |
|
|
port map(A => N_3, B => \baud_cntr[11]_net_1\, Y =>
|
| 4354 |
|
|
\baud_cntr_3[11]\);
|
| 4355 |
|
|
|
| 4356 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_21\ : OR2
|
| 4357 |
|
|
port map(A => \baud_cntr[6]_net_1\, B =>
|
| 4358 |
|
|
\baud_cntr[7]_net_1\, Y => \DWACT_FDEC_E[3]\);
|
| 4359 |
|
|
|
| 4360 |
|
|
VCC_i : VCC
|
| 4361 |
|
|
port map(Y => \VCC\);
|
| 4362 |
|
|
|
| 4363 |
|
|
\baud_cntr_RNO[12]\ : NOR2A
|
| 4364 |
|
|
port map(A => \baud_cntr_3[12]\, B => un2_baud_cntr, Y =>
|
| 4365 |
|
|
\baud_cntr_4[12]\);
|
| 4366 |
|
|
|
| 4367 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_27\ : OR3
|
| 4368 |
|
|
port map(A => \DWACT_FDEC_E[4]\, B => \baud_cntr[8]_net_1\,
|
| 4369 |
|
|
C => \baud_cntr[9]_net_1\, Y => N_4);
|
| 4370 |
|
|
|
| 4371 |
|
|
\baud_cntr_RNIAMP11[12]\ : NOR3
|
| 4372 |
|
|
port map(A => \baud_cntr[11]_net_1\, B =>
|
| 4373 |
|
|
\baud_cntr[12]_net_1\, C => \baud_cntr[3]_net_1\, Y =>
|
| 4374 |
|
|
un2_baud_cntr_6);
|
| 4375 |
|
|
|
| 4376 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_29\ : OR3
|
| 4377 |
|
|
port map(A => \baud_cntr[6]_net_1\, B =>
|
| 4378 |
|
|
\baud_cntr[7]_net_1\, C => \baud_cntr[8]_net_1\, Y =>
|
| 4379 |
|
|
\DWACT_FDEC_E[5]\);
|
| 4380 |
|
|
|
| 4381 |
|
|
\baud_cntr_RNO[9]\ : NOR2A
|
| 4382 |
|
|
port map(A => \baud_cntr_3[9]\, B => un2_baud_cntr, Y =>
|
| 4383 |
|
|
\baud_cntr_4[9]\);
|
| 4384 |
|
|
|
| 4385 |
|
|
\baud_cntr_RNI1RGS4[1]\ : NOR3C
|
| 4386 |
|
|
port map(A => un2_baud_cntr_8, B => un2_baud_cntr_7, C =>
|
| 4387 |
|
|
un2_baud_cntr_9, Y => un2_baud_cntr);
|
| 4388 |
|
|
|
| 4389 |
|
|
xmit_clock_RNO : NOR3C
|
| 4390 |
|
|
port map(A => \xmit_cntr[2]_net_1\, B =>
|
| 4391 |
|
|
\xmit_cntr[3]_net_1\, C => xmit_cntr_c1, Y =>
|
| 4392 |
|
|
un8_baud_clock_int);
|
| 4393 |
|
|
|
| 4394 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_23\ : XNOR2
|
| 4395 |
|
|
port map(A => N_6, B => \baud_cntr[8]_net_1\, Y =>
|
| 4396 |
|
|
\baud_cntr_3[8]\);
|
| 4397 |
|
|
|
| 4398 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_8\ : OR3
|
| 4399 |
|
|
port map(A => \baud_cntr[0]_net_1\, B =>
|
| 4400 |
|
|
\baud_cntr[1]_net_1\, C => \baud_cntr[2]_net_1\, Y =>
|
| 4401 |
|
|
N_11);
|
| 4402 |
|
|
|
| 4403 |
|
|
\xmit_cntr_RNO[1]\ : XOR2
|
| 4404 |
|
|
port map(A => \xmit_cntr[0]_net_1\, B =>
|
| 4405 |
|
|
\xmit_cntr[1]_net_1\, Y => xmit_cntr_n1);
|
| 4406 |
|
|
|
| 4407 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_22\ : OR3
|
| 4408 |
|
|
port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C
|
| 4409 |
|
|
=> \DWACT_FDEC_E[3]\, Y => N_6);
|
| 4410 |
|
|
|
| 4411 |
|
|
\baud_cntr[5]\ : DFN1C0
|
| 4412 |
|
|
port map(D => \baud_cntr_4[5]\, CLK => HCLK_c, CLR =>
|
| 4413 |
|
|
HRESETn_c, Q => \baud_cntr[5]_net_1\);
|
| 4414 |
|
|
|
| 4415 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_10\ : OR3
|
| 4416 |
|
|
port map(A => \baud_cntr[0]_net_1\, B =>
|
| 4417 |
|
|
\baud_cntr[1]_net_1\, C => \baud_cntr[2]_net_1\, Y =>
|
| 4418 |
|
|
\DWACT_FDEC_E[0]\);
|
| 4419 |
|
|
|
| 4420 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_30\ : OR3
|
| 4421 |
|
|
port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C
|
| 4422 |
|
|
=> \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\);
|
| 4423 |
|
|
|
| 4424 |
|
|
\baud_cntr[3]\ : DFN1C0
|
| 4425 |
|
|
port map(D => \baud_cntr_4[3]\, CLK => HCLK_c, CLR =>
|
| 4426 |
|
|
HRESETn_c, Q => \baud_cntr[3]_net_1\);
|
| 4427 |
|
|
|
| 4428 |
|
|
\baud_cntr_RNO[5]\ : NOR2A
|
| 4429 |
|
|
port map(A => \baud_cntr_3[5]\, B => un2_baud_cntr, Y =>
|
| 4430 |
|
|
\baud_cntr_4[5]\);
|
| 4431 |
|
|
|
| 4432 |
|
|
\baud_cntr[2]\ : DFN1C0
|
| 4433 |
|
|
port map(D => \baud_cntr_4[2]\, CLK => HCLK_c, CLR =>
|
| 4434 |
|
|
HRESETn_c, Q => \baud_cntr[2]_net_1\);
|
| 4435 |
|
|
|
| 4436 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_18\ : OR3
|
| 4437 |
|
|
port map(A => \baud_cntr[3]_net_1\, B =>
|
| 4438 |
|
|
\baud_cntr[4]_net_1\, C => \baud_cntr[5]_net_1\, Y =>
|
| 4439 |
|
|
\DWACT_FDEC_E[2]\);
|
| 4440 |
|
|
|
| 4441 |
|
|
GND_i : GND
|
| 4442 |
|
|
port map(Y => \GND\);
|
| 4443 |
|
|
|
| 4444 |
|
|
\baud_cntr_RNO[10]\ : NOR2A
|
| 4445 |
|
|
port map(A => \baud_cntr_3[10]\, B => un2_baud_cntr, Y =>
|
| 4446 |
|
|
\baud_cntr_4[10]\);
|
| 4447 |
|
|
|
| 4448 |
|
|
\baud_cntr[10]\ : DFN1C0
|
| 4449 |
|
|
port map(D => \baud_cntr_4[10]\, CLK => HCLK_c, CLR =>
|
| 4450 |
|
|
HRESETn_c, Q => \baud_cntr[10]_net_1\);
|
| 4451 |
|
|
|
| 4452 |
|
|
\xmit_cntr_RNO[0]\ : XOR2
|
| 4453 |
|
|
port map(A => \xmit_cntr[0]_net_1\, B => \baud_clock\, Y
|
| 4454 |
|
|
=> xmit_cntr_e0);
|
| 4455 |
|
|
|
| 4456 |
|
|
\baud_cntr[11]\ : DFN1C0
|
| 4457 |
|
|
port map(D => \baud_cntr_4[11]\, CLK => HCLK_c, CLR =>
|
| 4458 |
|
|
HRESETn_c, Q => \baud_cntr[11]_net_1\);
|
| 4459 |
|
|
|
| 4460 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_20\ : XNOR2
|
| 4461 |
|
|
port map(A => N_7, B => \baud_cntr[7]_net_1\, Y =>
|
| 4462 |
|
|
\baud_cntr_3[7]\);
|
| 4463 |
|
|
|
| 4464 |
|
|
\baud_cntr_RNIBIPH1[1]\ : NOR3A
|
| 4465 |
|
|
port map(A => un2_baud_cntr_4, B => \baud_cntr[4]_net_1\, C
|
| 4466 |
|
|
=> \baud_cntr[1]_net_1\, Y => un2_baud_cntr_8);
|
| 4467 |
|
|
|
| 4468 |
|
|
\baud_cntr[6]\ : DFN1C0
|
| 4469 |
|
|
port map(D => \baud_cntr_4[6]\, CLK => HCLK_c, CLR =>
|
| 4470 |
|
|
HRESETn_c, Q => \baud_cntr[6]_net_1\);
|
| 4471 |
|
|
|
| 4472 |
|
|
\baud_cntr_RNIVEMQ1[9]\ : NOR3A
|
| 4473 |
|
|
port map(A => un2_baud_cntr_6, B => \baud_cntr[0]_net_1\, C
|
| 4474 |
|
|
=> \baud_cntr[9]_net_1\, Y => un2_baud_cntr_9);
|
| 4475 |
|
|
|
| 4476 |
|
|
\baud_cntr[4]\ : DFN1C0
|
| 4477 |
|
|
port map(D => \baud_cntr_4[4]\, CLK => HCLK_c, CLR =>
|
| 4478 |
|
|
HRESETn_c, Q => \baud_cntr[4]_net_1\);
|
| 4479 |
|
|
|
| 4480 |
|
|
\baud_cntr_RNIQTSO[6]\ : NOR2
|
| 4481 |
|
|
port map(A => \baud_cntr[6]_net_1\, B =>
|
| 4482 |
|
|
\baud_cntr[8]_net_1\, Y => un2_baud_cntr_4);
|
| 4483 |
|
|
|
| 4484 |
|
|
\xmit_cntr[2]\ : DFN1E1C0
|
| 4485 |
|
|
port map(D => xmit_cntr_n2, CLK => HCLK_c, CLR => HRESETn_c,
|
| 4486 |
|
|
E => \baud_clock\, Q => \xmit_cntr[2]_net_1\);
|
| 4487 |
|
|
|
| 4488 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_9\ : XNOR2
|
| 4489 |
|
|
port map(A => N_11, B => \baud_cntr[3]_net_1\, Y =>
|
| 4490 |
|
|
\baud_cntr_3[3]\);
|
| 4491 |
|
|
|
| 4492 |
|
|
\baud_cntr_RNO[11]\ : NOR2A
|
| 4493 |
|
|
port map(A => \baud_cntr_3[11]\, B => un2_baud_cntr, Y =>
|
| 4494 |
|
|
\baud_cntr_4[11]\);
|
| 4495 |
|
|
|
| 4496 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_7\ : XNOR2
|
| 4497 |
|
|
port map(A => N_12, B => \baud_cntr[2]_net_1\, Y =>
|
| 4498 |
|
|
\baud_cntr_3[2]\);
|
| 4499 |
|
|
|
| 4500 |
|
|
\baud_cntr_RNO[6]\ : NOR2A
|
| 4501 |
|
|
port map(A => \baud_cntr_3[6]\, B => un2_baud_cntr, Y =>
|
| 4502 |
|
|
\baud_cntr_4[6]\);
|
| 4503 |
|
|
|
| 4504 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_28\ : XNOR2
|
| 4505 |
|
|
port map(A => N_4, B => \baud_cntr[10]_net_1\, Y =>
|
| 4506 |
|
|
\baud_cntr_3[10]\);
|
| 4507 |
|
|
|
| 4508 |
|
|
\baud_cntr_RNO[0]\ : OR2A
|
| 4509 |
|
|
port map(A => \baud_cntr[0]_net_1\, B => un2_baud_cntr, Y
|
| 4510 |
|
|
=> \baud_cntr_4[0]\);
|
| 4511 |
|
|
|
| 4512 |
|
|
\xmit_cntr_RNIPE04[1]\ : NOR2B
|
| 4513 |
|
|
port map(A => \xmit_cntr[1]_net_1\, B =>
|
| 4514 |
|
|
\xmit_cntr[0]_net_1\, Y => xmit_cntr_c1);
|
| 4515 |
|
|
|
| 4516 |
|
|
\baud_cntr_RNO[3]\ : NOR2A
|
| 4517 |
|
|
port map(A => \baud_cntr_3[3]\, B => un2_baud_cntr, Y =>
|
| 4518 |
|
|
\baud_cntr_4[3]\);
|
| 4519 |
|
|
|
| 4520 |
|
|
\baud_cntr[1]\ : DFN1C0
|
| 4521 |
|
|
port map(D => \baud_cntr_4[1]\, CLK => HCLK_c, CLR =>
|
| 4522 |
|
|
HRESETn_c, Q => \baud_cntr[1]_net_1\);
|
| 4523 |
|
|
|
| 4524 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_6\ : OR2
|
| 4525 |
|
|
port map(A => \baud_cntr[1]_net_1\, B =>
|
| 4526 |
|
|
\baud_cntr[0]_net_1\, Y => N_12);
|
| 4527 |
|
|
|
| 4528 |
|
|
xmit_clock : DFN1E1C0
|
| 4529 |
|
|
port map(D => un8_baud_clock_int, CLK => HCLK_c, CLR =>
|
| 4530 |
|
|
HRESETn_c, E => \baud_clock\, Q => \xmit_clock\);
|
| 4531 |
|
|
|
| 4532 |
|
|
\baud_cntr_RNO[4]\ : NOR2A
|
| 4533 |
|
|
port map(A => \baud_cntr_3[4]\, B => un2_baud_cntr, Y =>
|
| 4534 |
|
|
\baud_cntr_4[4]\);
|
| 4535 |
|
|
|
| 4536 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_14\ : XNOR2
|
| 4537 |
|
|
port map(A => N_9, B => \baud_cntr[5]_net_1\, Y =>
|
| 4538 |
|
|
\baud_cntr_3[5]\);
|
| 4539 |
|
|
|
| 4540 |
|
|
baud_clock_int : DFN1C0
|
| 4541 |
|
|
port map(D => un2_baud_cntr, CLK => HCLK_c, CLR =>
|
| 4542 |
|
|
HRESETn_c, Q => \baud_clock\);
|
| 4543 |
|
|
|
| 4544 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_34\ : OR2
|
| 4545 |
|
|
port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y
|
| 4546 |
|
|
=> N_2);
|
| 4547 |
|
|
|
| 4548 |
|
|
\xmit_cntr[1]\ : DFN1E1C0
|
| 4549 |
|
|
port map(D => xmit_cntr_n1, CLK => HCLK_c, CLR => HRESETn_c,
|
| 4550 |
|
|
E => \baud_clock\, Q => \xmit_cntr[1]_net_1\);
|
| 4551 |
|
|
|
| 4552 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_15\ : OR2
|
| 4553 |
|
|
port map(A => \baud_cntr[3]_net_1\, B =>
|
| 4554 |
|
|
\baud_cntr[4]_net_1\, Y => \DWACT_FDEC_E[1]\);
|
| 4555 |
|
|
|
| 4556 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_35\ : XNOR2
|
| 4557 |
|
|
port map(A => N_2, B => \baud_cntr[12]_net_1\, Y =>
|
| 4558 |
|
|
\baud_cntr_3[12]\);
|
| 4559 |
|
|
|
| 4560 |
|
|
\baud_cntr[12]\ : DFN1C0
|
| 4561 |
|
|
port map(D => \baud_cntr_4[12]\, CLK => HCLK_c, CLR =>
|
| 4562 |
|
|
HRESETn_c, Q => \baud_cntr[12]_net_1\);
|
| 4563 |
|
|
|
| 4564 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_16\ : OR3
|
| 4565 |
|
|
port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C
|
| 4566 |
|
|
=> \baud_cntr[5]_net_1\, Y => N_8);
|
| 4567 |
|
|
|
| 4568 |
|
|
\xmit_cntr[0]\ : DFN1C0
|
| 4569 |
|
|
port map(D => xmit_cntr_e0, CLK => HCLK_c, CLR => HRESETn_c,
|
| 4570 |
|
|
Q => \xmit_cntr[0]_net_1\);
|
| 4571 |
|
|
|
| 4572 |
|
|
\baud_cntr_RNO[2]\ : NOR2A
|
| 4573 |
|
|
port map(A => \baud_cntr_3[2]\, B => un2_baud_cntr, Y =>
|
| 4574 |
|
|
\baud_cntr_4[2]\);
|
| 4575 |
|
|
|
| 4576 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_11\ : OR2
|
| 4577 |
|
|
port map(A => \baud_cntr[3]_net_1\, B => \DWACT_FDEC_E[0]\,
|
| 4578 |
|
|
Y => N_10);
|
| 4579 |
|
|
|
| 4580 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_31\ : OR3
|
| 4581 |
|
|
port map(A => \DWACT_FDEC_E[6]\, B => \baud_cntr[9]_net_1\,
|
| 4582 |
|
|
C => \baud_cntr[10]_net_1\, Y => N_3);
|
| 4583 |
|
|
|
| 4584 |
|
|
\UG10.make_baud_cntr2.baud_cntr_3_I_17\ : XNOR2
|
| 4585 |
|
|
port map(A => N_8, B => \baud_cntr[6]_net_1\, Y =>
|
| 4586 |
|
|
\baud_cntr_3[6]\);
|
| 4587 |
|
|
|
| 4588 |
|
|
\baud_cntr_RNO[8]\ : NOR2A
|
| 4589 |
|
|
port map(A => \baud_cntr_3[8]\, B => un2_baud_cntr, Y =>
|
| 4590 |
|
|
\baud_cntr_4[8]\);
|
| 4591 |
|
|
|
| 4592 |
|
|
\baud_cntr[8]\ : DFN1C0
|
| 4593 |
|
|
port map(D => \baud_cntr_4[8]\, CLK => HCLK_c, CLR =>
|
| 4594 |
|
|
HRESETn_c, Q => \baud_cntr[8]_net_1\);
|
| 4595 |
|
|
|
| 4596 |
|
|
|
| 4597 |
|
|
end DEF_ARCH;
|
| 4598 |
|
|
|
| 4599 |
|
|
library ieee;
|
| 4600 |
|
|
use ieee.std_logic_1164.all;
|
| 4601 |
|
|
library proasic3;
|
| 4602 |
|
|
use proasic3.all;
|
| 4603 |
|
|
|
| 4604 |
|
|
entity top_CoreUARTapb_0_Rx_async is
|
| 4605 |
|
|
|
| 4606 |
|
|
port( data_out : out std_logic_vector(7 downto 0);
|
| 4607 |
|
|
OVERFLOW : out std_logic;
|
| 4608 |
|
|
FRAMING_ERR : out std_logic;
|
| 4609 |
|
|
stop_strobe : out std_logic;
|
| 4610 |
|
|
un1_temp_xhdl10_i : in std_logic;
|
| 4611 |
|
|
HRESETn_c : in std_logic;
|
| 4612 |
|
|
HCLK_c : in std_logic;
|
| 4613 |
|
|
PARITY_ERR : out std_logic;
|
| 4614 |
|
|
CoreAPB_0_APBmslave0_PENABLE : in std_logic;
|
| 4615 |
|
|
un1_temp_xhdl10 : in std_logic;
|
| 4616 |
|
|
N_3_0 : in std_logic;
|
| 4617 |
|
|
m6_0 : in std_logic;
|
| 4618 |
|
|
N_84_mux : out std_logic;
|
| 4619 |
|
|
baud_clock : in std_logic;
|
| 4620 |
|
|
receive_full : out std_logic
|
| 4621 |
|
|
);
|
| 4622 |
|
|
|
| 4623 |
|
|
end top_CoreUARTapb_0_Rx_async;
|
| 4624 |
|
|
|
| 4625 |
|
|
architecture DEF_ARCH of top_CoreUARTapb_0_Rx_async is
|
| 4626 |
|
|
|
| 4627 |
|
|
component MX2
|
| 4628 |
|
|
port( A : in std_logic := 'U';
|
| 4629 |
|
|
B : in std_logic := 'U';
|
| 4630 |
|
|
S : in std_logic := 'U';
|
| 4631 |
|
|
Y : out std_logic
|
| 4632 |
|
|
);
|
| 4633 |
|
|
end component;
|
| 4634 |
|
|
|
| 4635 |
|
|
component DFN1E1C0
|
| 4636 |
|
|
port( D : in std_logic := 'U';
|
| 4637 |
|
|
CLK : in std_logic := 'U';
|
| 4638 |
|
|
CLR : in std_logic := 'U';
|
| 4639 |
|
|
E : in std_logic := 'U';
|
| 4640 |
|
|
Q : out std_logic
|
| 4641 |
|
|
);
|
| 4642 |
|
|
end component;
|
| 4643 |
|
|
|
| 4644 |
|
|
component NOR2A
|
| 4645 |
|
|
port( A : in std_logic := 'U';
|
| 4646 |
|
|
B : in std_logic := 'U';
|
| 4647 |
|
|
Y : out std_logic
|
| 4648 |
|
|
);
|
| 4649 |
|
|
end component;
|
| 4650 |
|
|
|
| 4651 |
|
|
component NOR2
|
| 4652 |
|
|
port( A : in std_logic := 'U';
|
| 4653 |
|
|
B : in std_logic := 'U';
|
| 4654 |
|
|
Y : out std_logic
|
| 4655 |
|
|
);
|
| 4656 |
|
|
end component;
|
| 4657 |
|
|
|
| 4658 |
|
|
component DFN1C0
|
| 4659 |
|
|
port( D : in std_logic := 'U';
|
| 4660 |
|
|
CLK : in std_logic := 'U';
|
| 4661 |
|
|
CLR : in std_logic := 'U';
|
| 4662 |
|
|
Q : out std_logic
|
| 4663 |
|
|
);
|
| 4664 |
|
|
end component;
|
| 4665 |
|
|
|
| 4666 |
|
|
component NOR2B
|
| 4667 |
|
|
port( A : in std_logic := 'U';
|
| 4668 |
|
|
B : in std_logic := 'U';
|
| 4669 |
|
|
Y : out std_logic
|
| 4670 |
|
|
);
|
| 4671 |
|
|
end component;
|
| 4672 |
|
|
|
| 4673 |
|
|
component DFN1E0C0
|
| 4674 |
|
|
port( D : in std_logic := 'U';
|
| 4675 |
|
|
CLK : in std_logic := 'U';
|
| 4676 |
|
|
CLR : in std_logic := 'U';
|
| 4677 |
|
|
E : in std_logic := 'U';
|
| 4678 |
|
|
Q : out std_logic
|
| 4679 |
|
|
);
|
| 4680 |
|
|
end component;
|
| 4681 |
|
|
|
| 4682 |
|
|
component OR3A
|
| 4683 |
|
|
port( A : in std_logic := 'U';
|
| 4684 |
|
|
B : in std_logic := 'U';
|
| 4685 |
|
|
C : in std_logic := 'U';
|
| 4686 |
|
|
Y : out std_logic
|
| 4687 |
|
|
);
|
| 4688 |
|
|
end component;
|
| 4689 |
|
|
|
| 4690 |
|
|
component OR2A
|
| 4691 |
|
|
port( A : in std_logic := 'U';
|
| 4692 |
|
|
B : in std_logic := 'U';
|
| 4693 |
|
|
Y : out std_logic
|
| 4694 |
|
|
);
|
| 4695 |
|
|
end component;
|
| 4696 |
|
|
|
| 4697 |
|
|
component AO1
|
| 4698 |
|
|
port( A : in std_logic := 'U';
|
| 4699 |
|
|
B : in std_logic := 'U';
|
| 4700 |
|
|
C : in std_logic := 'U';
|
| 4701 |
|
|
Y : out std_logic
|
| 4702 |
|
|
);
|
| 4703 |
|
|
end component;
|
| 4704 |
|
|
|
| 4705 |
|
|
component VCC
|
| 4706 |
|
|
port( Y : out std_logic
|
| 4707 |
|
|
);
|
| 4708 |
|
|
end component;
|
| 4709 |
|
|
|
| 4710 |
|
|
component NOR3B
|
| 4711 |
|
|
port( A : in std_logic := 'U';
|
| 4712 |
|
|
B : in std_logic := 'U';
|
| 4713 |
|
|
C : in std_logic := 'U';
|
| 4714 |
|
|
Y : out std_logic
|
| 4715 |
|
|
);
|
| 4716 |
|
|
end component;
|
| 4717 |
|
|
|
| 4718 |
|
|
component OA1A
|
| 4719 |
|
|
port( A : in std_logic := 'U';
|
| 4720 |
|
|
B : in std_logic := 'U';
|
| 4721 |
|
|
C : in std_logic := 'U';
|
| 4722 |
|
|
Y : out std_logic
|
| 4723 |
|
|
);
|
| 4724 |
|
|
end component;
|
| 4725 |
|
|
|
| 4726 |
|
|
component XA1B
|
| 4727 |
|
|
port( A : in std_logic := 'U';
|
| 4728 |
|
|
B : in std_logic := 'U';
|
| 4729 |
|
|
C : in std_logic := 'U';
|
| 4730 |
|
|
Y : out std_logic
|
| 4731 |
|
|
);
|
| 4732 |
|
|
end component;
|
| 4733 |
|
|
|
| 4734 |
|
|
component DFN1P0
|
| 4735 |
|
|
port( D : in std_logic := 'U';
|
| 4736 |
|
|
CLK : in std_logic := 'U';
|
| 4737 |
|
|
PRE : in std_logic := 'U';
|
| 4738 |
|
|
Q : out std_logic
|
| 4739 |
|
|
);
|
| 4740 |
|
|
end component;
|
| 4741 |
|
|
|
| 4742 |
|
|
component MX2A
|
| 4743 |
|
|
port( A : in std_logic := 'U';
|
| 4744 |
|
|
B : in std_logic := 'U';
|
| 4745 |
|
|
S : in std_logic := 'U';
|
| 4746 |
|
|
Y : out std_logic
|
| 4747 |
|
|
);
|
| 4748 |
|
|
end component;
|
| 4749 |
|
|
|
| 4750 |
|
|
component OAI1
|
| 4751 |
|
|
port( A : in std_logic := 'U';
|
| 4752 |
|
|
B : in std_logic := 'U';
|
| 4753 |
|
|
C : in std_logic := 'U';
|
| 4754 |
|
|
Y : out std_logic
|
| 4755 |
|
|
);
|
| 4756 |
|
|
end component;
|
| 4757 |
|
|
|
| 4758 |
|
|
component AO18
|
| 4759 |
|
|
port( A : in std_logic := 'U';
|
| 4760 |
|
|
B : in std_logic := 'U';
|
| 4761 |
|
|
C : in std_logic := 'U';
|
| 4762 |
|
|
Y : out std_logic
|
| 4763 |
|
|
);
|
| 4764 |
|
|
end component;
|
| 4765 |
|
|
|
| 4766 |
|
|
component NOR3A
|
| 4767 |
|
|
port( A : in std_logic := 'U';
|
| 4768 |
|
|
B : in std_logic := 'U';
|
| 4769 |
|
|
C : in std_logic := 'U';
|
| 4770 |
|
|
Y : out std_logic
|
| 4771 |
|
|
);
|
| 4772 |
|
|
end component;
|
| 4773 |
|
|
|
| 4774 |
|
|
component GND
|
| 4775 |
|
|
port( Y : out std_logic
|
| 4776 |
|
|
);
|
| 4777 |
|
|
end component;
|
| 4778 |
|
|
|
| 4779 |
|
|
component OR2B
|
| 4780 |
|
|
port( A : in std_logic := 'U';
|
| 4781 |
|
|
B : in std_logic := 'U';
|
| 4782 |
|
|
Y : out std_logic
|
| 4783 |
|
|
);
|
| 4784 |
|
|
end component;
|
| 4785 |
|
|
|
| 4786 |
|
|
component AXOI4
|
| 4787 |
|
|
port( A : in std_logic := 'U';
|
| 4788 |
|
|
B : in std_logic := 'U';
|
| 4789 |
|
|
C : in std_logic := 'U';
|
| 4790 |
|
|
Y : out std_logic
|
| 4791 |
|
|
);
|
| 4792 |
|
|
end component;
|
| 4793 |
|
|
|
| 4794 |
|
|
component MX2B
|
| 4795 |
|
|
port( A : in std_logic := 'U';
|
| 4796 |
|
|
B : in std_logic := 'U';
|
| 4797 |
|
|
S : in std_logic := 'U';
|
| 4798 |
|
|
Y : out std_logic
|
| 4799 |
|
|
);
|
| 4800 |
|
|
end component;
|
| 4801 |
|
|
|
| 4802 |
|
|
component AO1D
|
| 4803 |
|
|
port( A : in std_logic := 'U';
|
| 4804 |
|
|
B : in std_logic := 'U';
|
| 4805 |
|
|
C : in std_logic := 'U';
|
| 4806 |
|
|
Y : out std_logic
|
| 4807 |
|
|
);
|
| 4808 |
|
|
end component;
|
| 4809 |
|
|
|
| 4810 |
|
|
component MX2C
|
| 4811 |
|
|
port( A : in std_logic := 'U';
|
| 4812 |
|
|
B : in std_logic := 'U';
|
| 4813 |
|
|
S : in std_logic := 'U';
|
| 4814 |
|
|
Y : out std_logic
|
| 4815 |
|
|
);
|
| 4816 |
|
|
end component;
|
| 4817 |
|
|
|
| 4818 |
|
|
component NOR3C
|
| 4819 |
|
|
port( A : in std_logic := 'U';
|
| 4820 |
|
|
B : in std_logic := 'U';
|
| 4821 |
|
|
C : in std_logic := 'U';
|
| 4822 |
|
|
Y : out std_logic
|
| 4823 |
|
|
);
|
| 4824 |
|
|
end component;
|
| 4825 |
|
|
|
| 4826 |
|
|
component OR2
|
| 4827 |
|
|
port( A : in std_logic := 'U';
|
| 4828 |
|
|
B : in std_logic := 'U';
|
| 4829 |
|
|
Y : out std_logic
|
| 4830 |
|
|
);
|
| 4831 |
|
|
end component;
|
| 4832 |
|
|
|
| 4833 |
|
|
component DFN1E1P0
|
| 4834 |
|
|
port( D : in std_logic := 'U';
|
| 4835 |
|
|
CLK : in std_logic := 'U';
|
| 4836 |
|
|
PRE : in std_logic := 'U';
|
| 4837 |
|
|
E : in std_logic := 'U';
|
| 4838 |
|
|
Q : out std_logic
|
| 4839 |
|
|
);
|
| 4840 |
|
|
end component;
|
| 4841 |
|
|
|
| 4842 |
|
|
component XA1
|
| 4843 |
|
|
port( A : in std_logic := 'U';
|
| 4844 |
|
|
B : in std_logic := 'U';
|
| 4845 |
|
|
C : in std_logic := 'U';
|
| 4846 |
|
|
Y : out std_logic
|
| 4847 |
|
|
);
|
| 4848 |
|
|
end component;
|
| 4849 |
|
|
|
| 4850 |
|
|
component XNOR2
|
| 4851 |
|
|
port( A : in std_logic := 'U';
|
| 4852 |
|
|
B : in std_logic := 'U';
|
| 4853 |
|
|
Y : out std_logic
|
| 4854 |
|
|
);
|
| 4855 |
|
|
end component;
|
| 4856 |
|
|
|
| 4857 |
|
|
signal m65_e_2, \rx_bit_cnt[3]_net_1\, m65_e_1,
|
| 4858 |
|
|
\rx_bit_cnt[2]_net_1\, \rx_bit_cnt[1]_net_1\,
|
| 4859 |
|
|
\rx_bit_cnt[0]_net_1\, m24_1, \rx_state[1]_net_1\,
|
| 4860 |
|
|
\receive_count[3]_net_1\, \rx_state[0]_net_1\, m63_0,
|
| 4861 |
|
|
\receive_full\, un47_baud_clock_NE_1, m22_0, m6_0_1,
|
| 4862 |
|
|
\receive_count[1]_net_1\, m6_0_0,
|
| 4863 |
|
|
\receive_count[2]_net_1\, \receive_count[0]_net_1\,
|
| 4864 |
|
|
overflow_int_3, un47_baud_clock_i, rx_byte_xhdl5_1_sqmuxa,
|
| 4865 |
|
|
N_7_0, N_12_0, N_41_mux, N_38_mux, N_40_mux, N_86,
|
| 4866 |
|
|
framing_error_int_0_sqmuxa, i1_mux, N_78,
|
| 4867 |
|
|
\rx_shift_12[5]\, \rx_shift[6]_net_1\, N_82, N_82_mux,
|
| 4868 |
|
|
parity_err_xhdl2_9, \PARITY_ERR\, \rx_shift_12[1]\,
|
| 4869 |
|
|
\rx_shift[2]_net_1\, \rx_shift_12[0]\,
|
| 4870 |
|
|
\rx_shift[1]_net_1\, un1_framing_error_i4,
|
| 4871 |
|
|
framing_error_i_0_sqmuxa, \framing_error_int\,
|
| 4872 |
|
|
overflow_xhdl1_1_sqmuxa, N_72, \overflow_int\,
|
| 4873 |
|
|
\samples[1]_net_1\, \samples_i_0[0]\, \samples[2]_net_1\,
|
| 4874 |
|
|
\samples_RNO[2]_net_1\, \samples_RNO[0]_net_1\,
|
| 4875 |
|
|
\samples_RNO[1]_net_1\, N_14_i, N_13_0, rx_bit_cnt_n2,
|
| 4876 |
|
|
N_337, rx_bit_cnt_n3, N_14_0, N_92_mux, N_92,
|
| 4877 |
|
|
\rx_shift_12[6]\, \rx_shift[7]_net_1\, \rx_shift_12[4]\,
|
| 4878 |
|
|
\rx_shift[5]_net_1\, \rx_shift_12[3]\,
|
| 4879 |
|
|
\rx_shift[4]_net_1\, \rx_shift_12[2]\,
|
| 4880 |
|
|
\rx_shift[3]_net_1\, rx_bit_cnt_n1, N_21, N_341,
|
| 4881 |
|
|
\last_bit[0]_net_1\, N_329, N_9_0, N_34, N_11_i, N_12_i,
|
| 4882 |
|
|
framing_error_int_2_sqmuxa, N_33, N_91_mux, N_40, N_258,
|
| 4883 |
|
|
N_43, N_46, i14_mux, receive_count_e0, N_28, N_347,
|
| 4884 |
|
|
N_85_mux, \rx_shift[0]_net_1\, \GND\, \VCC\ : std_logic;
|
| 4885 |
|
|
|
| 4886 |
|
|
begin
|
| 4887 |
|
|
|
| 4888 |
|
|
PARITY_ERR <= \PARITY_ERR\;
|
| 4889 |
|
|
receive_full <= \receive_full\;
|
| 4890 |
|
|
|
| 4891 |
|
|
\rx_state_RNO_1[0]\ : MX2
|
| 4892 |
|
|
port map(A => N_14_i, B => N_33, S => \rx_state[0]_net_1\,
|
| 4893 |
|
|
Y => N_34);
|
| 4894 |
|
|
|
| 4895 |
|
|
\rx_byte_xhdl5[0]\ : DFN1E1C0
|
| 4896 |
|
|
port map(D => \rx_shift[0]_net_1\, CLK => HCLK_c, CLR =>
|
| 4897 |
|
|
HRESETn_c, E => rx_byte_xhdl5_1_sqmuxa, Q => data_out(0));
|
| 4898 |
|
|
|
| 4899 |
|
|
parity_err_xhdl2_RNIO8S9 : NOR2A
|
| 4900 |
|
|
port map(A => CoreAPB_0_APBmslave0_PENABLE, B =>
|
| 4901 |
|
|
\PARITY_ERR\, Y => N_78);
|
| 4902 |
|
|
|
| 4903 |
|
|
overflow_int : DFN1E1C0
|
| 4904 |
|
|
port map(D => overflow_int_3, CLK => HCLK_c, CLR =>
|
| 4905 |
|
|
HRESETn_c, E => baud_clock, Q => \overflow_int\);
|
| 4906 |
|
|
|
| 4907 |
|
|
\rx_shift_RNO[5]\ : NOR2A
|
| 4908 |
|
|
port map(A => \rx_shift[6]_net_1\, B => N_82, Y =>
|
| 4909 |
|
|
\rx_shift_12[5]\);
|
| 4910 |
|
|
|
| 4911 |
|
|
\rx_bit_cnt_RNIRKEI_0[1]\ : NOR2
|
| 4912 |
|
|
port map(A => \rx_bit_cnt[1]_net_1\, B =>
|
| 4913 |
|
|
\rx_bit_cnt[0]_net_1\, Y => m65_e_1);
|
| 4914 |
|
|
|
| 4915 |
|
|
\samples[0]\ : DFN1C0
|
| 4916 |
|
|
port map(D => \samples_RNO[0]_net_1\, CLK => HCLK_c, CLR
|
| 4917 |
|
|
=> HRESETn_c, Q => \samples_i_0[0]\);
|
| 4918 |
|
|
|
| 4919 |
|
|
\rx_state_RNO_2[0]\ : NOR2B
|
| 4920 |
|
|
port map(A => N_91_mux, B => \rx_state[1]_net_1\, Y => N_33);
|
| 4921 |
|
|
|
| 4922 |
|
|
\rx_shift[2]\ : DFN1E0C0
|
| 4923 |
|
|
port map(D => \rx_shift_12[2]\, CLK => HCLK_c, CLR =>
|
| 4924 |
|
|
HRESETn_c, E => N_92_mux, Q => \rx_shift[2]_net_1\);
|
| 4925 |
|
|
|
| 4926 |
|
|
\rx_byte_xhdl5[6]\ : DFN1E1C0
|
| 4927 |
|
|
port map(D => \rx_shift[6]_net_1\, CLK => HCLK_c, CLR =>
|
| 4928 |
|
|
HRESETn_c, E => rx_byte_xhdl5_1_sqmuxa, Q => data_out(6));
|
| 4929 |
|
|
|
| 4930 |
|
|
\rx_state_RNI8MII[0]\ : NOR2A
|
| 4931 |
|
|
port map(A => baud_clock, B => \rx_state[0]_net_1\, Y =>
|
| 4932 |
|
|
m22_0);
|
| 4933 |
|
|
|
| 4934 |
|
|
\rx_bit_cnt_RNIT3MR[3]\ : OR3A
|
| 4935 |
|
|
port map(A => \rx_bit_cnt[3]_net_1\, B =>
|
| 4936 |
|
|
\rx_bit_cnt[1]_net_1\, C => \rx_bit_cnt[2]_net_1\, Y =>
|
| 4937 |
|
|
un47_baud_clock_NE_1);
|
| 4938 |
|
|
|
| 4939 |
|
|
\rx_shift_RNO[3]\ : NOR2A
|
| 4940 |
|
|
port map(A => \rx_shift[4]_net_1\, B => N_82, Y =>
|
| 4941 |
|
|
\rx_shift_12[3]\);
|
| 4942 |
|
|
|
| 4943 |
|
|
\receive_count_RNINPCM[2]\ : NOR2B
|
| 4944 |
|
|
port map(A => N_11_i, B => \receive_count[2]_net_1\, Y =>
|
| 4945 |
|
|
N_12_i);
|
| 4946 |
|
|
|
| 4947 |
|
|
\receive_count[1]\ : DFN1E1C0
|
| 4948 |
|
|
port map(D => N_46, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 4949 |
|
|
baud_clock, Q => \receive_count[1]_net_1\);
|
| 4950 |
|
|
|
| 4951 |
|
|
\rx_state_RNO_0[1]\ : NOR2B
|
| 4952 |
|
|
port map(A => \rx_state[0]_net_1\, B => baud_clock, Y =>
|
| 4953 |
|
|
N_347);
|
| 4954 |
|
|
|
| 4955 |
|
|
\rx_shift[7]\ : DFN1E0C0
|
| 4956 |
|
|
port map(D => N_82_mux, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 4957 |
|
|
=> N_92_mux, Q => \rx_shift[7]_net_1\);
|
| 4958 |
|
|
|
| 4959 |
|
|
overflow_xhdl1_RNO : NOR2
|
| 4960 |
|
|
port map(A => N_72, B => un1_temp_xhdl10, Y =>
|
| 4961 |
|
|
overflow_xhdl1_1_sqmuxa);
|
| 4962 |
|
|
|
| 4963 |
|
|
\rx_shift[0]\ : DFN1E0C0
|
| 4964 |
|
|
port map(D => \rx_shift_12[0]\, CLK => HCLK_c, CLR =>
|
| 4965 |
|
|
HRESETn_c, E => N_92_mux, Q => \rx_shift[0]_net_1\);
|
| 4966 |
|
|
|
| 4967 |
|
|
\last_bit_RNITELD1[0]\ : OR2A
|
| 4968 |
|
|
port map(A => N_12_0, B => un47_baud_clock_NE_1, Y =>
|
| 4969 |
|
|
un47_baud_clock_i);
|
| 4970 |
|
|
|
| 4971 |
|
|
receive_full_int_RNO : AO1
|
| 4972 |
|
|
port map(A => N_7_0, B => m65_e_2, C => un1_temp_xhdl10, Y
|
| 4973 |
|
|
=> N_85_mux);
|
| 4974 |
|
|
|
| 4975 |
|
|
\rx_state_RNIRGPT2[1]\ : MX2
|
| 4976 |
|
|
port map(A => N_28, B => N_40_mux, S => \rx_state[1]_net_1\,
|
| 4977 |
|
|
Y => N_258);
|
| 4978 |
|
|
|
| 4979 |
|
|
\receive_count_RNIQRTE[2]\ : NOR2
|
| 4980 |
|
|
port map(A => \receive_count[2]_net_1\, B =>
|
| 4981 |
|
|
\receive_count[0]_net_1\, Y => m6_0_0);
|
| 4982 |
|
|
|
| 4983 |
|
|
VCC_i : VCC
|
| 4984 |
|
|
port map(Y => \VCC\);
|
| 4985 |
|
|
|
| 4986 |
|
|
framing_error_i : DFN1E0C0
|
| 4987 |
|
|
port map(D => framing_error_i_0_sqmuxa, CLK => HCLK_c, CLR
|
| 4988 |
|
|
=> HRESETn_c, E => un1_framing_error_i4, Q =>
|
| 4989 |
|
|
FRAMING_ERR);
|
| 4990 |
|
|
|
| 4991 |
|
|
\rx_shift_RNO[1]\ : NOR2A
|
| 4992 |
|
|
port map(A => \rx_shift[2]_net_1\, B => N_82, Y =>
|
| 4993 |
|
|
\rx_shift_12[1]\);
|
| 4994 |
|
|
|
| 4995 |
|
|
\rx_byte_xhdl5[7]\ : DFN1E1C0
|
| 4996 |
|
|
port map(D => \rx_shift[7]_net_1\, CLK => HCLK_c, CLR =>
|
| 4997 |
|
|
HRESETn_c, E => rx_byte_xhdl5_1_sqmuxa, Q => data_out(7));
|
| 4998 |
|
|
|
| 4999 |
|
|
\receive_count[3]\ : DFN1E1C0
|
| 5000 |
|
|
port map(D => N_40, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 5001 |
|
|
baud_clock, Q => \receive_count[3]_net_1\);
|
| 5002 |
|
|
|
| 5003 |
|
|
stop_strobe_i_RNO : NOR2A
|
| 5004 |
|
|
port map(A => N_14_i, B => \rx_state[0]_net_1\, Y =>
|
| 5005 |
|
|
framing_error_int_2_sqmuxa);
|
| 5006 |
|
|
|
| 5007 |
|
|
\receive_count_RNIHN511[3]\ : NOR3B
|
| 5008 |
|
|
port map(A => \rx_state[0]_net_1\, B => N_86, C =>
|
| 5009 |
|
|
\receive_count[3]_net_1\, Y => N_40_mux);
|
| 5010 |
|
|
|
| 5011 |
|
|
\rx_shift_RNO[2]\ : NOR2A
|
| 5012 |
|
|
port map(A => \rx_shift[3]_net_1\, B => N_82, Y =>
|
| 5013 |
|
|
\rx_shift_12[2]\);
|
| 5014 |
|
|
|
| 5015 |
|
|
\rx_bit_cnt[2]\ : DFN1E0C0
|
| 5016 |
|
|
port map(D => rx_bit_cnt_n2, CLK => HCLK_c, CLR =>
|
| 5017 |
|
|
HRESETn_c, E => N_92_mux, Q => \rx_bit_cnt[2]_net_1\);
|
| 5018 |
|
|
|
| 5019 |
|
|
framing_error_int_RNID1OO : NOR2B
|
| 5020 |
|
|
port map(A => \framing_error_int\, B => baud_clock, Y =>
|
| 5021 |
|
|
framing_error_i_0_sqmuxa);
|
| 5022 |
|
|
|
| 5023 |
|
|
\rx_bit_cnt[1]\ : DFN1E0C0
|
| 5024 |
|
|
port map(D => rx_bit_cnt_n1, CLK => HCLK_c, CLR =>
|
| 5025 |
|
|
HRESETn_c, E => N_92_mux, Q => \rx_bit_cnt[1]_net_1\);
|
| 5026 |
|
|
|
| 5027 |
|
|
\receive_count_RNIMPRT[1]\ : NOR2B
|
| 5028 |
|
|
port map(A => m6_0_1, B => m6_0_0, Y => N_38_mux);
|
| 5029 |
|
|
|
| 5030 |
|
|
\receive_count_RNIB6D31[3]\ : OA1A
|
| 5031 |
|
|
port map(A => N_86, B => \receive_count[3]_net_1\, C =>
|
| 5032 |
|
|
i1_mux, Y => N_91_mux);
|
| 5033 |
|
|
|
| 5034 |
|
|
\receive_count_RNIPQTE[1]\ : NOR2B
|
| 5035 |
|
|
port map(A => \receive_count[1]_net_1\, B =>
|
| 5036 |
|
|
\receive_count[0]_net_1\, Y => N_11_i);
|
| 5037 |
|
|
|
| 5038 |
|
|
\rx_bit_cnt_RNO[0]\ : NOR2A
|
| 5039 |
|
|
port map(A => N_92, B => \rx_bit_cnt[0]_net_1\, Y => N_21);
|
| 5040 |
|
|
|
| 5041 |
|
|
\receive_count_RNO[2]\ : XA1B
|
| 5042 |
|
|
port map(A => \receive_count[2]_net_1\, B => N_11_i, C =>
|
| 5043 |
|
|
N_258, Y => N_43);
|
| 5044 |
|
|
|
| 5045 |
|
|
\samples[1]\ : DFN1P0
|
| 5046 |
|
|
port map(D => \samples_RNO[1]_net_1\, CLK => HCLK_c, PRE
|
| 5047 |
|
|
=> HRESETn_c, Q => \samples[1]_net_1\);
|
| 5048 |
|
|
|
| 5049 |
|
|
\rx_state_RNINSJ6[1]\ : NOR2
|
| 5050 |
|
|
port map(A => \rx_state[0]_net_1\, B => \rx_state[1]_net_1\,
|
| 5051 |
|
|
Y => N_82);
|
| 5052 |
|
|
|
| 5053 |
|
|
\rx_shift_RNO[6]\ : NOR2A
|
| 5054 |
|
|
port map(A => \rx_shift[7]_net_1\, B => N_82, Y =>
|
| 5055 |
|
|
\rx_shift_12[6]\);
|
| 5056 |
|
|
|
| 5057 |
|
|
\rx_state_RNO[1]\ : MX2A
|
| 5058 |
|
|
port map(A => un47_baud_clock_i, B => N_91_mux, S =>
|
| 5059 |
|
|
\rx_state[1]_net_1\, Y => i14_mux);
|
| 5060 |
|
|
|
| 5061 |
|
|
\rx_shift_RNO[0]\ : NOR2A
|
| 5062 |
|
|
port map(A => \rx_shift[1]_net_1\, B => N_82, Y =>
|
| 5063 |
|
|
\rx_shift_12[0]\);
|
| 5064 |
|
|
|
| 5065 |
|
|
\rx_bit_cnt_RNO[2]\ : XA1B
|
| 5066 |
|
|
port map(A => \rx_bit_cnt[2]_net_1\, B => N_337, C => N_82,
|
| 5067 |
|
|
Y => rx_bit_cnt_n2);
|
| 5068 |
|
|
|
| 5069 |
|
|
\receive_count_RNIMPRT[3]\ : NOR2B
|
| 5070 |
|
|
port map(A => N_12_i, B => \receive_count[3]_net_1\, Y =>
|
| 5071 |
|
|
N_13_0);
|
| 5072 |
|
|
|
| 5073 |
|
|
\receive_count_RNIQEOJ1[3]\ : OAI1
|
| 5074 |
|
|
port map(A => N_82, B => N_13_0, C => baud_clock, Y =>
|
| 5075 |
|
|
N_92_mux);
|
| 5076 |
|
|
|
| 5077 |
|
|
\receive_count[2]\ : DFN1E1C0
|
| 5078 |
|
|
port map(D => N_43, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 5079 |
|
|
baud_clock, Q => \receive_count[2]_net_1\);
|
| 5080 |
|
|
|
| 5081 |
|
|
stop_strobe_i : DFN1E1C0
|
| 5082 |
|
|
port map(D => framing_error_int_2_sqmuxa, CLK => HCLK_c,
|
| 5083 |
|
|
CLR => HRESETn_c, E => baud_clock, Q => stop_strobe);
|
| 5084 |
|
|
|
| 5085 |
|
|
\rx_state[1]\ : DFN1E1C0
|
| 5086 |
|
|
port map(D => i14_mux, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 5087 |
|
|
=> N_347, Q => \rx_state[1]_net_1\);
|
| 5088 |
|
|
|
| 5089 |
|
|
\rx_shift_RNO[7]\ : NOR2
|
| 5090 |
|
|
port map(A => i1_mux, B => N_82, Y => N_82_mux);
|
| 5091 |
|
|
|
| 5092 |
|
|
\receive_count_RNO[1]\ : XA1B
|
| 5093 |
|
|
port map(A => \receive_count[0]_net_1\, B =>
|
| 5094 |
|
|
\receive_count[1]_net_1\, C => N_258, Y => N_46);
|
| 5095 |
|
|
|
| 5096 |
|
|
\samples_RNILCH5[0]\ : AO18
|
| 5097 |
|
|
port map(A => \samples[1]_net_1\, B => \samples_i_0[0]\, C
|
| 5098 |
|
|
=> \samples[2]_net_1\, Y => i1_mux);
|
| 5099 |
|
|
|
| 5100 |
|
|
\rx_shift[4]\ : DFN1E0C0
|
| 5101 |
|
|
port map(D => \rx_shift_12[4]\, CLK => HCLK_c, CLR =>
|
| 5102 |
|
|
HRESETn_c, E => N_92_mux, Q => \rx_shift[4]_net_1\);
|
| 5103 |
|
|
|
| 5104 |
|
|
\last_bit_RNO[0]\ : NOR2A
|
| 5105 |
|
|
port map(A => \last_bit[0]_net_1\, B => \rx_state[1]_net_1\,
|
| 5106 |
|
|
Y => N_341);
|
| 5107 |
|
|
|
| 5108 |
|
|
\rx_state_RNIIO511[1]\ : NOR2B
|
| 5109 |
|
|
port map(A => N_13_0, B => \rx_state[1]_net_1\, Y => N_14_i);
|
| 5110 |
|
|
|
| 5111 |
|
|
receive_full_int_RNI92452 : NOR3A
|
| 5112 |
|
|
port map(A => N_7_0, B => \receive_full\, C =>
|
| 5113 |
|
|
un47_baud_clock_i, Y => rx_byte_xhdl5_1_sqmuxa);
|
| 5114 |
|
|
|
| 5115 |
|
|
overflow_int_RNO_0 : NOR3B
|
| 5116 |
|
|
port map(A => \rx_state[0]_net_1\, B => \receive_full\, C
|
| 5117 |
|
|
=> \rx_state[1]_net_1\, Y => m63_0);
|
| 5118 |
|
|
|
| 5119 |
|
|
GND_i : GND
|
| 5120 |
|
|
port map(Y => \GND\);
|
| 5121 |
|
|
|
| 5122 |
|
|
\receive_count_RNO[3]\ : XA1B
|
| 5123 |
|
|
port map(A => \receive_count[3]_net_1\, B => N_12_i, C =>
|
| 5124 |
|
|
N_258, Y => N_40);
|
| 5125 |
|
|
|
| 5126 |
|
|
\rx_state_RNIUFEG1[0]\ : OR2B
|
| 5127 |
|
|
port map(A => m22_0, B => N_38_mux, Y => N_41_mux);
|
| 5128 |
|
|
|
| 5129 |
|
|
framing_error_int_RNO_0 : NOR3B
|
| 5130 |
|
|
port map(A => \rx_state[1]_net_1\, B =>
|
| 5131 |
|
|
\receive_count[3]_net_1\, C => \rx_state[0]_net_1\, Y =>
|
| 5132 |
|
|
m24_1);
|
| 5133 |
|
|
|
| 5134 |
|
|
receive_full_int : DFN1E1C0
|
| 5135 |
|
|
port map(D => un1_temp_xhdl10_i, CLK => HCLK_c, CLR =>
|
| 5136 |
|
|
HRESETn_c, E => N_85_mux, Q => \receive_full\);
|
| 5137 |
|
|
|
| 5138 |
|
|
\rx_state_RNI4LSL_0[1]\ : NOR2A
|
| 5139 |
|
|
port map(A => baud_clock, B => N_82, Y => N_92);
|
| 5140 |
|
|
|
| 5141 |
|
|
framing_error_i_RNO : NOR2
|
| 5142 |
|
|
port map(A => framing_error_i_0_sqmuxa, B =>
|
| 5143 |
|
|
un1_temp_xhdl10, Y => un1_framing_error_i4);
|
| 5144 |
|
|
|
| 5145 |
|
|
\receive_count_RNO[0]\ : AXOI4
|
| 5146 |
|
|
port map(A => N_258, B => baud_clock, C =>
|
| 5147 |
|
|
\receive_count[0]_net_1\, Y => receive_count_e0);
|
| 5148 |
|
|
|
| 5149 |
|
|
parity_err_xhdl2 : DFN1E1C0
|
| 5150 |
|
|
port map(D => parity_err_xhdl2_9, CLK => HCLK_c, CLR =>
|
| 5151 |
|
|
HRESETn_c, E => un1_temp_xhdl10, Q => \PARITY_ERR\);
|
| 5152 |
|
|
|
| 5153 |
|
|
\samples_RNO[0]\ : MX2B
|
| 5154 |
|
|
port map(A => \samples_i_0[0]\, B => \samples[1]_net_1\, S
|
| 5155 |
|
|
=> baud_clock, Y => \samples_RNO[0]_net_1\);
|
| 5156 |
|
|
|
| 5157 |
|
|
\rx_byte_xhdl5[4]\ : DFN1E1C0
|
| 5158 |
|
|
port map(D => \rx_shift[4]_net_1\, CLK => HCLK_c, CLR =>
|
| 5159 |
|
|
HRESETn_c, E => rx_byte_xhdl5_1_sqmuxa, Q => data_out(4));
|
| 5160 |
|
|
|
| 5161 |
|
|
\rx_shift[6]\ : DFN1E0C0
|
| 5162 |
|
|
port map(D => \rx_shift_12[6]\, CLK => HCLK_c, CLR =>
|
| 5163 |
|
|
HRESETn_c, E => N_92_mux, Q => \rx_shift[6]_net_1\);
|
| 5164 |
|
|
|
| 5165 |
|
|
\rx_state_RNO[0]\ : AO1D
|
| 5166 |
|
|
port map(A => N_9_0, B => \rx_state[1]_net_1\, C => N_34, Y
|
| 5167 |
|
|
=> N_329);
|
| 5168 |
|
|
|
| 5169 |
|
|
\rx_shift_RNO[4]\ : NOR2A
|
| 5170 |
|
|
port map(A => \rx_shift[5]_net_1\, B => N_82, Y =>
|
| 5171 |
|
|
\rx_shift_12[4]\);
|
| 5172 |
|
|
|
| 5173 |
|
|
\rx_shift[1]\ : DFN1E0C0
|
| 5174 |
|
|
port map(D => \rx_shift_12[1]\, CLK => HCLK_c, CLR =>
|
| 5175 |
|
|
HRESETn_c, E => N_92_mux, Q => \rx_shift[1]_net_1\);
|
| 5176 |
|
|
|
| 5177 |
|
|
\rx_shift[3]\ : DFN1E0C0
|
| 5178 |
|
|
port map(D => \rx_shift_12[3]\, CLK => HCLK_c, CLR =>
|
| 5179 |
|
|
HRESETn_c, E => N_92_mux, Q => \rx_shift[3]_net_1\);
|
| 5180 |
|
|
|
| 5181 |
|
|
framing_error_int : DFN1E1C0
|
| 5182 |
|
|
port map(D => framing_error_int_0_sqmuxa, CLK => HCLK_c,
|
| 5183 |
|
|
CLR => HRESETn_c, E => baud_clock, Q =>
|
| 5184 |
|
|
\framing_error_int\);
|
| 5185 |
|
|
|
| 5186 |
|
|
\rx_byte_xhdl5[2]\ : DFN1E1C0
|
| 5187 |
|
|
port map(D => \rx_shift[2]_net_1\, CLK => HCLK_c, CLR =>
|
| 5188 |
|
|
HRESETn_c, E => rx_byte_xhdl5_1_sqmuxa, Q => data_out(2));
|
| 5189 |
|
|
|
| 5190 |
|
|
\rx_state[0]\ : DFN1E1C0
|
| 5191 |
|
|
port map(D => N_329, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 5192 |
|
|
baud_clock, Q => \rx_state[0]_net_1\);
|
| 5193 |
|
|
|
| 5194 |
|
|
\samples[2]\ : DFN1P0
|
| 5195 |
|
|
port map(D => \samples_RNO[2]_net_1\, CLK => HCLK_c, PRE
|
| 5196 |
|
|
=> HRESETn_c, Q => \samples[2]_net_1\);
|
| 5197 |
|
|
|
| 5198 |
|
|
overflow_xhdl1_RNO_0 : NOR2B
|
| 5199 |
|
|
port map(A => \overflow_int\, B => baud_clock, Y => N_72);
|
| 5200 |
|
|
|
| 5201 |
|
|
\receive_count_RNISTTE[1]\ : NOR2A
|
| 5202 |
|
|
port map(A => \receive_count[3]_net_1\, B =>
|
| 5203 |
|
|
\receive_count[1]_net_1\, Y => m6_0_1);
|
| 5204 |
|
|
|
| 5205 |
|
|
\receive_count[0]\ : DFN1C0
|
| 5206 |
|
|
port map(D => receive_count_e0, CLK => HCLK_c, CLR =>
|
| 5207 |
|
|
HRESETn_c, Q => \receive_count[0]_net_1\);
|
| 5208 |
|
|
|
| 5209 |
|
|
parity_err_xhdl2_RNO : NOR3A
|
| 5210 |
|
|
port map(A => m65_e_2, B => un1_temp_xhdl10, C => i1_mux, Y
|
| 5211 |
|
|
=> parity_err_xhdl2_9);
|
| 5212 |
|
|
|
| 5213 |
|
|
\rx_state_RNIEQ9P1[0]\ : MX2C
|
| 5214 |
|
|
port map(A => \rx_state[0]_net_1\, B => N_41_mux, S =>
|
| 5215 |
|
|
i1_mux, Y => N_28);
|
| 5216 |
|
|
|
| 5217 |
|
|
\rx_byte_xhdl5[3]\ : DFN1E1C0
|
| 5218 |
|
|
port map(D => \rx_shift[3]_net_1\, CLK => HCLK_c, CLR =>
|
| 5219 |
|
|
HRESETn_c, E => rx_byte_xhdl5_1_sqmuxa, Q => data_out(3));
|
| 5220 |
|
|
|
| 5221 |
|
|
\rx_bit_cnt_RNIRKEI[1]\ : NOR2B
|
| 5222 |
|
|
port map(A => \rx_bit_cnt[0]_net_1\, B =>
|
| 5223 |
|
|
\rx_bit_cnt[1]_net_1\, Y => N_337);
|
| 5224 |
|
|
|
| 5225 |
|
|
framing_error_int_RNO : NOR3C
|
| 5226 |
|
|
port map(A => N_86, B => m24_1, C => i1_mux, Y =>
|
| 5227 |
|
|
framing_error_int_0_sqmuxa);
|
| 5228 |
|
|
|
| 5229 |
|
|
\samples_RNO[2]\ : OR2
|
| 5230 |
|
|
port map(A => \samples[2]_net_1\, B => baud_clock, Y =>
|
| 5231 |
|
|
\samples_RNO[2]_net_1\);
|
| 5232 |
|
|
|
| 5233 |
|
|
parity_err_xhdl2_RNI59R11 : NOR3A
|
| 5234 |
|
|
port map(A => m6_0, B => N_78, C => N_3_0, Y => N_84_mux);
|
| 5235 |
|
|
|
| 5236 |
|
|
\rx_shift[5]\ : DFN1E0C0
|
| 5237 |
|
|
port map(D => \rx_shift_12[5]\, CLK => HCLK_c, CLR =>
|
| 5238 |
|
|
HRESETn_c, E => N_92_mux, Q => \rx_shift[5]_net_1\);
|
| 5239 |
|
|
|
| 5240 |
|
|
\rx_state_RNI4LSL[1]\ : NOR3B
|
| 5241 |
|
|
port map(A => \rx_state[0]_net_1\, B => baud_clock, C =>
|
| 5242 |
|
|
\rx_state[1]_net_1\, Y => N_7_0);
|
| 5243 |
|
|
|
| 5244 |
|
|
\rx_bit_cnt[0]\ : DFN1E0C0
|
| 5245 |
|
|
port map(D => N_21, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 5246 |
|
|
N_92_mux, Q => \rx_bit_cnt[0]_net_1\);
|
| 5247 |
|
|
|
| 5248 |
|
|
\samples_RNO[1]\ : MX2
|
| 5249 |
|
|
port map(A => \samples[1]_net_1\, B => \samples[2]_net_1\,
|
| 5250 |
|
|
S => baud_clock, Y => \samples_RNO[1]_net_1\);
|
| 5251 |
|
|
|
| 5252 |
|
|
overflow_int_RNO : NOR2A
|
| 5253 |
|
|
port map(A => m63_0, B => un47_baud_clock_i, Y =>
|
| 5254 |
|
|
overflow_int_3);
|
| 5255 |
|
|
|
| 5256 |
|
|
\rx_byte_xhdl5[1]\ : DFN1E1C0
|
| 5257 |
|
|
port map(D => \rx_shift[1]_net_1\, CLK => HCLK_c, CLR =>
|
| 5258 |
|
|
HRESETn_c, E => rx_byte_xhdl5_1_sqmuxa, Q => data_out(1));
|
| 5259 |
|
|
|
| 5260 |
|
|
\rx_bit_cnt_RNO_0[3]\ : NOR2B
|
| 5261 |
|
|
port map(A => N_337, B => \rx_bit_cnt[2]_net_1\, Y =>
|
| 5262 |
|
|
N_14_0);
|
| 5263 |
|
|
|
| 5264 |
|
|
\receive_count_RNINPCM[1]\ : NOR3B
|
| 5265 |
|
|
port map(A => \receive_count[2]_net_1\, B =>
|
| 5266 |
|
|
\receive_count[1]_net_1\, C => \receive_count[0]_net_1\,
|
| 5267 |
|
|
Y => N_86);
|
| 5268 |
|
|
|
| 5269 |
|
|
\rx_bit_cnt_RNIQDT41[3]\ : NOR3B
|
| 5270 |
|
|
port map(A => \rx_bit_cnt[3]_net_1\, B => m65_e_1, C =>
|
| 5271 |
|
|
\rx_bit_cnt[2]_net_1\, Y => m65_e_2);
|
| 5272 |
|
|
|
| 5273 |
|
|
\last_bit[0]\ : DFN1E1P0
|
| 5274 |
|
|
port map(D => N_41_mux, CLK => HCLK_c, PRE => HRESETn_c, E
|
| 5275 |
|
|
=> N_341, Q => \last_bit[0]_net_1\);
|
| 5276 |
|
|
|
| 5277 |
|
|
\rx_bit_cnt_RNO[3]\ : XA1B
|
| 5278 |
|
|
port map(A => \rx_bit_cnt[3]_net_1\, B => N_14_0, C => N_82,
|
| 5279 |
|
|
Y => rx_bit_cnt_n3);
|
| 5280 |
|
|
|
| 5281 |
|
|
\rx_byte_xhdl5[5]\ : DFN1E1C0
|
| 5282 |
|
|
port map(D => \rx_shift[5]_net_1\, CLK => HCLK_c, CLR =>
|
| 5283 |
|
|
HRESETn_c, E => rx_byte_xhdl5_1_sqmuxa, Q => data_out(5));
|
| 5284 |
|
|
|
| 5285 |
|
|
\rx_bit_cnt[3]\ : DFN1E0C0
|
| 5286 |
|
|
port map(D => rx_bit_cnt_n3, CLK => HCLK_c, CLR =>
|
| 5287 |
|
|
HRESETn_c, E => N_92_mux, Q => \rx_bit_cnt[3]_net_1\);
|
| 5288 |
|
|
|
| 5289 |
|
|
\rx_state_RNO_0[0]\ : MX2C
|
| 5290 |
|
|
port map(A => N_38_mux, B => un47_baud_clock_i, S =>
|
| 5291 |
|
|
\rx_state[0]_net_1\, Y => N_9_0);
|
| 5292 |
|
|
|
| 5293 |
|
|
\rx_bit_cnt_RNO[1]\ : XA1
|
| 5294 |
|
|
port map(A => \rx_bit_cnt[0]_net_1\, B =>
|
| 5295 |
|
|
\rx_bit_cnt[1]_net_1\, C => N_92, Y => rx_bit_cnt_n1);
|
| 5296 |
|
|
|
| 5297 |
|
|
overflow_xhdl1 : DFN1E0C0
|
| 5298 |
|
|
port map(D => un1_temp_xhdl10_i, CLK => HCLK_c, CLR =>
|
| 5299 |
|
|
HRESETn_c, E => overflow_xhdl1_1_sqmuxa, Q => OVERFLOW);
|
| 5300 |
|
|
|
| 5301 |
|
|
\last_bit_RNI0BVH[0]\ : XNOR2
|
| 5302 |
|
|
port map(A => \rx_bit_cnt[0]_net_1\, B =>
|
| 5303 |
|
|
\last_bit[0]_net_1\, Y => N_12_0);
|
| 5304 |
|
|
|
| 5305 |
|
|
|
| 5306 |
|
|
end DEF_ARCH;
|
| 5307 |
|
|
|
| 5308 |
|
|
library ieee;
|
| 5309 |
|
|
use ieee.std_logic_1164.all;
|
| 5310 |
|
|
library proasic3;
|
| 5311 |
|
|
use proasic3.all;
|
| 5312 |
|
|
|
| 5313 |
|
|
entity top_CoreUARTapb_0_COREUART is
|
| 5314 |
|
|
|
| 5315 |
|
|
port( data_out : out std_logic_vector(7 downto 0);
|
| 5316 |
|
|
CoreAPB_0_APBmslave0_PWDATA : in std_logic_vector(7 downto 0);
|
| 5317 |
|
|
CoreAPB_0_APBmslave0_PADDR_0 : in std_logic;
|
| 5318 |
|
|
N_84_mux : out std_logic;
|
| 5319 |
|
|
N_3_0 : in std_logic;
|
| 5320 |
|
|
CoreAPB_0_APBmslave0_PENABLE : in std_logic;
|
| 5321 |
|
|
PARITY_ERR : out std_logic;
|
| 5322 |
|
|
FRAMING_ERR : out std_logic;
|
| 5323 |
|
|
OVERFLOW : out std_logic;
|
| 5324 |
|
|
TXRDY : out std_logic;
|
| 5325 |
|
|
TX_c : out std_logic;
|
| 5326 |
|
|
HRESETn_c : in std_logic;
|
| 5327 |
|
|
HCLK_c : in std_logic;
|
| 5328 |
|
|
RXRDY : out std_logic;
|
| 5329 |
|
|
N_15_0 : in std_logic;
|
| 5330 |
|
|
m6_0 : in std_logic;
|
| 5331 |
|
|
CoreAPB_0_APBmslave0_PWRITE : in std_logic;
|
| 5332 |
|
|
CoreAPB_0_APBmslave0_PSELx : in std_logic
|
| 5333 |
|
|
);
|
| 5334 |
|
|
|
| 5335 |
|
|
end top_CoreUARTapb_0_COREUART;
|
| 5336 |
|
|
|
| 5337 |
|
|
architecture DEF_ARCH of top_CoreUARTapb_0_COREUART is
|
| 5338 |
|
|
|
| 5339 |
|
|
component INV
|
| 5340 |
|
|
port( A : in std_logic := 'U';
|
| 5341 |
|
|
Y : out std_logic
|
| 5342 |
|
|
);
|
| 5343 |
|
|
end component;
|
| 5344 |
|
|
|
| 5345 |
|
|
component DFN1E1C0
|
| 5346 |
|
|
port( D : in std_logic := 'U';
|
| 5347 |
|
|
CLK : in std_logic := 'U';
|
| 5348 |
|
|
CLR : in std_logic := 'U';
|
| 5349 |
|
|
E : in std_logic := 'U';
|
| 5350 |
|
|
Q : out std_logic
|
| 5351 |
|
|
);
|
| 5352 |
|
|
end component;
|
| 5353 |
|
|
|
| 5354 |
|
|
component top_CoreUARTapb_0_Tx_async
|
| 5355 |
|
|
port( tx_hold_reg : in std_logic_vector(7 downto 0) := (others => 'U');
|
| 5356 |
|
|
HRESETn_c : in std_logic := 'U';
|
| 5357 |
|
|
HCLK_c : in std_logic := 'U';
|
| 5358 |
|
|
TX_c : out std_logic;
|
| 5359 |
|
|
TXRDY : out std_logic;
|
| 5360 |
|
|
xmit_pulse : in std_logic := 'U';
|
| 5361 |
|
|
un1_csn : in std_logic := 'U'
|
| 5362 |
|
|
);
|
| 5363 |
|
|
end component;
|
| 5364 |
|
|
|
| 5365 |
|
|
component NOR2B
|
| 5366 |
|
|
port( A : in std_logic := 'U';
|
| 5367 |
|
|
B : in std_logic := 'U';
|
| 5368 |
|
|
Y : out std_logic
|
| 5369 |
|
|
);
|
| 5370 |
|
|
end component;
|
| 5371 |
|
|
|
| 5372 |
|
|
component VCC
|
| 5373 |
|
|
port( Y : out std_logic
|
| 5374 |
|
|
);
|
| 5375 |
|
|
end component;
|
| 5376 |
|
|
|
| 5377 |
|
|
component OR2A
|
| 5378 |
|
|
port( A : in std_logic := 'U';
|
| 5379 |
|
|
B : in std_logic := 'U';
|
| 5380 |
|
|
Y : out std_logic
|
| 5381 |
|
|
);
|
| 5382 |
|
|
end component;
|
| 5383 |
|
|
|
| 5384 |
|
|
component GND
|
| 5385 |
|
|
port( Y : out std_logic
|
| 5386 |
|
|
);
|
| 5387 |
|
|
end component;
|
| 5388 |
|
|
|
| 5389 |
|
|
component top_CoreUARTapb_0_Clock_gen
|
| 5390 |
|
|
port( HRESETn_c : in std_logic := 'U';
|
| 5391 |
|
|
HCLK_c : in std_logic := 'U';
|
| 5392 |
|
|
baud_clock : out std_logic;
|
| 5393 |
|
|
xmit_pulse : out std_logic
|
| 5394 |
|
|
);
|
| 5395 |
|
|
end component;
|
| 5396 |
|
|
|
| 5397 |
|
|
component NOR3B
|
| 5398 |
|
|
port( A : in std_logic := 'U';
|
| 5399 |
|
|
B : in std_logic := 'U';
|
| 5400 |
|
|
C : in std_logic := 'U';
|
| 5401 |
|
|
Y : out std_logic
|
| 5402 |
|
|
);
|
| 5403 |
|
|
end component;
|
| 5404 |
|
|
|
| 5405 |
|
|
component top_CoreUARTapb_0_Rx_async
|
| 5406 |
|
|
port( data_out : out std_logic_vector(7 downto 0);
|
| 5407 |
|
|
OVERFLOW : out std_logic;
|
| 5408 |
|
|
FRAMING_ERR : out std_logic;
|
| 5409 |
|
|
stop_strobe : out std_logic;
|
| 5410 |
|
|
un1_temp_xhdl10_i : in std_logic := 'U';
|
| 5411 |
|
|
HRESETn_c : in std_logic := 'U';
|
| 5412 |
|
|
HCLK_c : in std_logic := 'U';
|
| 5413 |
|
|
PARITY_ERR : out std_logic;
|
| 5414 |
|
|
CoreAPB_0_APBmslave0_PENABLE : in std_logic := 'U';
|
| 5415 |
|
|
un1_temp_xhdl10 : in std_logic := 'U';
|
| 5416 |
|
|
N_3_0 : in std_logic := 'U';
|
| 5417 |
|
|
m6_0 : in std_logic := 'U';
|
| 5418 |
|
|
N_84_mux : out std_logic;
|
| 5419 |
|
|
baud_clock : in std_logic := 'U';
|
| 5420 |
|
|
receive_full : out std_logic
|
| 5421 |
|
|
);
|
| 5422 |
|
|
end component;
|
| 5423 |
|
|
|
| 5424 |
|
|
signal \un1_temp_xhdl10_i\, \un1_temp_xhdl10\, un1_csn_1,
|
| 5425 |
|
|
\un1_temp_xhdl10_1\, un1_csn, un1_rx_fifo, receive_full,
|
| 5426 |
|
|
stop_strobe, \tx_hold_reg[0]_net_1\,
|
| 5427 |
|
|
\tx_hold_reg[1]_net_1\, \tx_hold_reg[2]_net_1\,
|
| 5428 |
|
|
\tx_hold_reg[3]_net_1\, \tx_hold_reg[4]_net_1\,
|
| 5429 |
|
|
\tx_hold_reg[5]_net_1\, \tx_hold_reg[6]_net_1\,
|
| 5430 |
|
|
\tx_hold_reg[7]_net_1\, baud_clock, xmit_pulse, \GND\,
|
| 5431 |
|
|
\VCC\ : std_logic;
|
| 5432 |
|
|
|
| 5433 |
|
|
for all : top_CoreUARTapb_0_Tx_async
|
| 5434 |
|
|
Use entity work.top_CoreUARTapb_0_Tx_async(DEF_ARCH);
|
| 5435 |
|
|
for all : top_CoreUARTapb_0_Clock_gen
|
| 5436 |
|
|
Use entity work.top_CoreUARTapb_0_Clock_gen(DEF_ARCH);
|
| 5437 |
|
|
for all : top_CoreUARTapb_0_Rx_async
|
| 5438 |
|
|
Use entity work.top_CoreUARTapb_0_Rx_async(DEF_ARCH);
|
| 5439 |
|
|
begin
|
| 5440 |
|
|
|
| 5441 |
|
|
|
| 5442 |
|
|
un1_temp_xhdl10_i : INV
|
| 5443 |
|
|
port map(A => \un1_temp_xhdl10\, Y => \un1_temp_xhdl10_i\);
|
| 5444 |
|
|
|
| 5445 |
|
|
\tx_hold_reg[7]\ : DFN1E1C0
|
| 5446 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(7), CLK => HCLK_c,
|
| 5447 |
|
|
CLR => HRESETn_c, E => un1_csn, Q =>
|
| 5448 |
|
|
\tx_hold_reg[7]_net_1\);
|
| 5449 |
|
|
|
| 5450 |
|
|
make_TX : top_CoreUARTapb_0_Tx_async
|
| 5451 |
|
|
port map(tx_hold_reg(7) => \tx_hold_reg[7]_net_1\,
|
| 5452 |
|
|
tx_hold_reg(6) => \tx_hold_reg[6]_net_1\, tx_hold_reg(5)
|
| 5453 |
|
|
=> \tx_hold_reg[5]_net_1\, tx_hold_reg(4) =>
|
| 5454 |
|
|
\tx_hold_reg[4]_net_1\, tx_hold_reg(3) =>
|
| 5455 |
|
|
\tx_hold_reg[3]_net_1\, tx_hold_reg(2) =>
|
| 5456 |
|
|
\tx_hold_reg[2]_net_1\, tx_hold_reg(1) =>
|
| 5457 |
|
|
\tx_hold_reg[1]_net_1\, tx_hold_reg(0) =>
|
| 5458 |
|
|
\tx_hold_reg[0]_net_1\, HRESETn_c => HRESETn_c, HCLK_c
|
| 5459 |
|
|
=> HCLK_c, TX_c => TX_c, TXRDY => TXRDY, xmit_pulse =>
|
| 5460 |
|
|
xmit_pulse, un1_csn => un1_csn);
|
| 5461 |
|
|
|
| 5462 |
|
|
\tx_hold_reg[5]\ : DFN1E1C0
|
| 5463 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(5), CLK => HCLK_c,
|
| 5464 |
|
|
CLR => HRESETn_c, E => un1_csn, Q =>
|
| 5465 |
|
|
\tx_hold_reg[5]_net_1\);
|
| 5466 |
|
|
|
| 5467 |
|
|
\tx_hold_reg[0]\ : DFN1E1C0
|
| 5468 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(0), CLK => HCLK_c,
|
| 5469 |
|
|
CLR => HRESETn_c, E => un1_csn, Q =>
|
| 5470 |
|
|
\tx_hold_reg[0]_net_1\);
|
| 5471 |
|
|
|
| 5472 |
|
|
\reg_write.un1_csn\ : NOR2B
|
| 5473 |
|
|
port map(A => un1_csn_1, B => N_15_0, Y => un1_csn);
|
| 5474 |
|
|
|
| 5475 |
|
|
VCC_i : VCC
|
| 5476 |
|
|
port map(Y => \VCC\);
|
| 5477 |
|
|
|
| 5478 |
|
|
\tx_hold_reg[3]\ : DFN1E1C0
|
| 5479 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(3), CLK => HCLK_c,
|
| 5480 |
|
|
CLR => HRESETn_c, E => un1_csn, Q =>
|
| 5481 |
|
|
\tx_hold_reg[3]_net_1\);
|
| 5482 |
|
|
|
| 5483 |
|
|
rxrdy_xhdl4_RNO : OR2A
|
| 5484 |
|
|
port map(A => receive_full, B => stop_strobe, Y =>
|
| 5485 |
|
|
un1_rx_fifo);
|
| 5486 |
|
|
|
| 5487 |
|
|
un1_temp_xhdl10 : NOR2B
|
| 5488 |
|
|
port map(A => \un1_temp_xhdl10_1\, B => N_15_0, Y =>
|
| 5489 |
|
|
\un1_temp_xhdl10\);
|
| 5490 |
|
|
|
| 5491 |
|
|
\tx_hold_reg[2]\ : DFN1E1C0
|
| 5492 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(2), CLK => HCLK_c,
|
| 5493 |
|
|
CLR => HRESETn_c, E => un1_csn, Q =>
|
| 5494 |
|
|
\tx_hold_reg[2]_net_1\);
|
| 5495 |
|
|
|
| 5496 |
|
|
GND_i : GND
|
| 5497 |
|
|
port map(Y => \GND\);
|
| 5498 |
|
|
|
| 5499 |
|
|
\tx_hold_reg[1]\ : DFN1E1C0
|
| 5500 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(1), CLK => HCLK_c,
|
| 5501 |
|
|
CLR => HRESETn_c, E => un1_csn, Q =>
|
| 5502 |
|
|
\tx_hold_reg[1]_net_1\);
|
| 5503 |
|
|
|
| 5504 |
|
|
\tx_hold_reg[6]\ : DFN1E1C0
|
| 5505 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(6), CLK => HCLK_c,
|
| 5506 |
|
|
CLR => HRESETn_c, E => un1_csn, Q =>
|
| 5507 |
|
|
\tx_hold_reg[6]_net_1\);
|
| 5508 |
|
|
|
| 5509 |
|
|
un1_temp_xhdl10_1 : NOR2B
|
| 5510 |
|
|
port map(A => CoreAPB_0_APBmslave0_PADDR_0, B => m6_0, Y
|
| 5511 |
|
|
=> \un1_temp_xhdl10_1\);
|
| 5512 |
|
|
|
| 5513 |
|
|
\tx_hold_reg[4]\ : DFN1E1C0
|
| 5514 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(4), CLK => HCLK_c,
|
| 5515 |
|
|
CLR => HRESETn_c, E => un1_csn, Q =>
|
| 5516 |
|
|
\tx_hold_reg[4]_net_1\);
|
| 5517 |
|
|
|
| 5518 |
|
|
make_top_CoreUARTapb_0_Clock_gen :
|
| 5519 |
|
|
top_CoreUARTapb_0_Clock_gen
|
| 5520 |
|
|
port map(HRESETn_c => HRESETn_c, HCLK_c => HCLK_c,
|
| 5521 |
|
|
baud_clock => baud_clock, xmit_pulse => xmit_pulse);
|
| 5522 |
|
|
|
| 5523 |
|
|
\reg_write.un1_csn_1\ : NOR3B
|
| 5524 |
|
|
port map(A => CoreAPB_0_APBmslave0_PSELx, B =>
|
| 5525 |
|
|
CoreAPB_0_APBmslave0_PWRITE, C =>
|
| 5526 |
|
|
CoreAPB_0_APBmslave0_PADDR_0, Y => un1_csn_1);
|
| 5527 |
|
|
|
| 5528 |
|
|
make_RX : top_CoreUARTapb_0_Rx_async
|
| 5529 |
|
|
port map(data_out(7) => data_out(7), data_out(6) =>
|
| 5530 |
|
|
data_out(6), data_out(5) => data_out(5), data_out(4) =>
|
| 5531 |
|
|
data_out(4), data_out(3) => data_out(3), data_out(2) =>
|
| 5532 |
|
|
data_out(2), data_out(1) => data_out(1), data_out(0) =>
|
| 5533 |
|
|
data_out(0), OVERFLOW => OVERFLOW, FRAMING_ERR =>
|
| 5534 |
|
|
FRAMING_ERR, stop_strobe => stop_strobe,
|
| 5535 |
|
|
un1_temp_xhdl10_i => \un1_temp_xhdl10_i\, HRESETn_c =>
|
| 5536 |
|
|
HRESETn_c, HCLK_c => HCLK_c, PARITY_ERR => PARITY_ERR,
|
| 5537 |
|
|
CoreAPB_0_APBmslave0_PENABLE =>
|
| 5538 |
|
|
CoreAPB_0_APBmslave0_PENABLE, un1_temp_xhdl10 =>
|
| 5539 |
|
|
\un1_temp_xhdl10\, N_3_0 => N_3_0, m6_0 => m6_0, N_84_mux
|
| 5540 |
|
|
=> N_84_mux, baud_clock => baud_clock, receive_full =>
|
| 5541 |
|
|
receive_full);
|
| 5542 |
|
|
|
| 5543 |
|
|
rxrdy_xhdl4 : DFN1E1C0
|
| 5544 |
|
|
port map(D => receive_full, CLK => HCLK_c, CLR => HRESETn_c,
|
| 5545 |
|
|
E => un1_rx_fifo, Q => RXRDY);
|
| 5546 |
|
|
|
| 5547 |
|
|
|
| 5548 |
|
|
end DEF_ARCH;
|
| 5549 |
|
|
|
| 5550 |
|
|
library ieee;
|
| 5551 |
|
|
use ieee.std_logic_1164.all;
|
| 5552 |
|
|
library proasic3;
|
| 5553 |
|
|
use proasic3.all;
|
| 5554 |
|
|
|
| 5555 |
|
|
entity top_CoreUARTapb_0_CoreUARTapb is
|
| 5556 |
|
|
|
| 5557 |
|
|
port( CoreAPB_0_APBmslave0_PRDATA : out std_logic_vector(7 downto 0);
|
| 5558 |
|
|
CoreAPB_0_APBmslave0_PWDATA : in std_logic_vector(7 downto 0);
|
| 5559 |
|
|
CoreAPB_0_APBmslave0_PADDR : in std_logic_vector(4 downto 2);
|
| 5560 |
|
|
TX_c : out std_logic;
|
| 5561 |
|
|
HRESETn_c : in std_logic;
|
| 5562 |
|
|
HCLK_c : in std_logic;
|
| 5563 |
|
|
CoreAPB_0_APBmslave0_PENABLE : in std_logic;
|
| 5564 |
|
|
CoreAPB_0_APBmslave0_PWRITE : in std_logic;
|
| 5565 |
|
|
CoreAPB_0_APBmslave0_PSELx : in std_logic
|
| 5566 |
|
|
);
|
| 5567 |
|
|
|
| 5568 |
|
|
end top_CoreUARTapb_0_CoreUARTapb;
|
| 5569 |
|
|
|
| 5570 |
|
|
architecture DEF_ARCH of top_CoreUARTapb_0_CoreUARTapb is
|
| 5571 |
|
|
|
| 5572 |
|
|
component NOR2B
|
| 5573 |
|
|
port( A : in std_logic := 'U';
|
| 5574 |
|
|
B : in std_logic := 'U';
|
| 5575 |
|
|
Y : out std_logic
|
| 5576 |
|
|
);
|
| 5577 |
|
|
end component;
|
| 5578 |
|
|
|
| 5579 |
|
|
component NOR2
|
| 5580 |
|
|
port( A : in std_logic := 'U';
|
| 5581 |
|
|
B : in std_logic := 'U';
|
| 5582 |
|
|
Y : out std_logic
|
| 5583 |
|
|
);
|
| 5584 |
|
|
end component;
|
| 5585 |
|
|
|
| 5586 |
|
|
component DFN1E1C0
|
| 5587 |
|
|
port( D : in std_logic := 'U';
|
| 5588 |
|
|
CLK : in std_logic := 'U';
|
| 5589 |
|
|
CLR : in std_logic := 'U';
|
| 5590 |
|
|
E : in std_logic := 'U';
|
| 5591 |
|
|
Q : out std_logic
|
| 5592 |
|
|
);
|
| 5593 |
|
|
end component;
|
| 5594 |
|
|
|
| 5595 |
|
|
component AOI1
|
| 5596 |
|
|
port( A : in std_logic := 'U';
|
| 5597 |
|
|
B : in std_logic := 'U';
|
| 5598 |
|
|
C : in std_logic := 'U';
|
| 5599 |
|
|
Y : out std_logic
|
| 5600 |
|
|
);
|
| 5601 |
|
|
end component;
|
| 5602 |
|
|
|
| 5603 |
|
|
component MX2
|
| 5604 |
|
|
port( A : in std_logic := 'U';
|
| 5605 |
|
|
B : in std_logic := 'U';
|
| 5606 |
|
|
S : in std_logic := 'U';
|
| 5607 |
|
|
Y : out std_logic
|
| 5608 |
|
|
);
|
| 5609 |
|
|
end component;
|
| 5610 |
|
|
|
| 5611 |
|
|
component MX2C
|
| 5612 |
|
|
port( A : in std_logic := 'U';
|
| 5613 |
|
|
B : in std_logic := 'U';
|
| 5614 |
|
|
S : in std_logic := 'U';
|
| 5615 |
|
|
Y : out std_logic
|
| 5616 |
|
|
);
|
| 5617 |
|
|
end component;
|
| 5618 |
|
|
|
| 5619 |
|
|
component VCC
|
| 5620 |
|
|
port( Y : out std_logic
|
| 5621 |
|
|
);
|
| 5622 |
|
|
end component;
|
| 5623 |
|
|
|
| 5624 |
|
|
component MX2A
|
| 5625 |
|
|
port( A : in std_logic := 'U';
|
| 5626 |
|
|
B : in std_logic := 'U';
|
| 5627 |
|
|
S : in std_logic := 'U';
|
| 5628 |
|
|
Y : out std_logic
|
| 5629 |
|
|
);
|
| 5630 |
|
|
end component;
|
| 5631 |
|
|
|
| 5632 |
|
|
component NOR3C
|
| 5633 |
|
|
port( A : in std_logic := 'U';
|
| 5634 |
|
|
B : in std_logic := 'U';
|
| 5635 |
|
|
C : in std_logic := 'U';
|
| 5636 |
|
|
Y : out std_logic
|
| 5637 |
|
|
);
|
| 5638 |
|
|
end component;
|
| 5639 |
|
|
|
| 5640 |
|
|
component GND
|
| 5641 |
|
|
port( Y : out std_logic
|
| 5642 |
|
|
);
|
| 5643 |
|
|
end component;
|
| 5644 |
|
|
|
| 5645 |
|
|
component top_CoreUARTapb_0_COREUART
|
| 5646 |
|
|
port( data_out : out std_logic_vector(7 downto 0);
|
| 5647 |
|
|
CoreAPB_0_APBmslave0_PWDATA : in std_logic_vector(7 downto 0) := (others => 'U');
|
| 5648 |
|
|
CoreAPB_0_APBmslave0_PADDR_0 : in std_logic := 'U';
|
| 5649 |
|
|
N_84_mux : out std_logic;
|
| 5650 |
|
|
N_3_0 : in std_logic := 'U';
|
| 5651 |
|
|
CoreAPB_0_APBmslave0_PENABLE : in std_logic := 'U';
|
| 5652 |
|
|
PARITY_ERR : out std_logic;
|
| 5653 |
|
|
FRAMING_ERR : out std_logic;
|
| 5654 |
|
|
OVERFLOW : out std_logic;
|
| 5655 |
|
|
TXRDY : out std_logic;
|
| 5656 |
|
|
TX_c : out std_logic;
|
| 5657 |
|
|
HRESETn_c : in std_logic := 'U';
|
| 5658 |
|
|
HCLK_c : in std_logic := 'U';
|
| 5659 |
|
|
RXRDY : out std_logic;
|
| 5660 |
|
|
N_15_0 : in std_logic := 'U';
|
| 5661 |
|
|
m6_0 : in std_logic := 'U';
|
| 5662 |
|
|
CoreAPB_0_APBmslave0_PWRITE : in std_logic := 'U';
|
| 5663 |
|
|
CoreAPB_0_APBmslave0_PSELx : in std_logic := 'U'
|
| 5664 |
|
|
);
|
| 5665 |
|
|
end component;
|
| 5666 |
|
|
|
| 5667 |
|
|
component NOR2A
|
| 5668 |
|
|
port( A : in std_logic := 'U';
|
| 5669 |
|
|
B : in std_logic := 'U';
|
| 5670 |
|
|
Y : out std_logic
|
| 5671 |
|
|
);
|
| 5672 |
|
|
end component;
|
| 5673 |
|
|
|
| 5674 |
|
|
component NOR3B
|
| 5675 |
|
|
port( A : in std_logic := 'U';
|
| 5676 |
|
|
B : in std_logic := 'U';
|
| 5677 |
|
|
C : in std_logic := 'U';
|
| 5678 |
|
|
Y : out std_logic
|
| 5679 |
|
|
);
|
| 5680 |
|
|
end component;
|
| 5681 |
|
|
|
| 5682 |
|
|
component NOR3A
|
| 5683 |
|
|
port( A : in std_logic := 'U';
|
| 5684 |
|
|
B : in std_logic := 'U';
|
| 5685 |
|
|
C : in std_logic := 'U';
|
| 5686 |
|
|
Y : out std_logic
|
| 5687 |
|
|
);
|
| 5688 |
|
|
end component;
|
| 5689 |
|
|
|
| 5690 |
|
|
signal \m6_0\, \m10_1\, N_34_0, N_8_0,
|
| 5691 |
|
|
\controlReg1[3]_net_1\, N_35_0, N_36_0, OVERFLOW, N_37_0,
|
| 5692 |
|
|
N_68, \nxtprdata_xhdl7_1[3]\, \data_out[3]\,
|
| 5693 |
|
|
\controlReg2[3]_net_1\, N_26_0, \controlReg1[7]_net_1\,
|
| 5694 |
|
|
N_27_0, N_56_0, \nxtprdata_xhdl7_1[7]\, \data_out[7]\,
|
| 5695 |
|
|
\controlReg2[7]_net_1\, N_3_0, N_15_0, N_20_0,
|
| 5696 |
|
|
\controlReg1[5]_net_1\, N_21_0, N_62,
|
| 5697 |
|
|
\nxtprdata_xhdl7_1[5]\, \data_out[5]\,
|
| 5698 |
|
|
\controlReg2[5]_net_1\, N_74, \data_out[1]\,
|
| 5699 |
|
|
\controlReg2[1]_net_1\, N_71, \data_out[2]\,
|
| 5700 |
|
|
\controlReg2[2]_net_1\, N_65, \data_out[4]\,
|
| 5701 |
|
|
\controlReg2[4]_net_1\, \nxtprdata_xhdl7_1[1]\, N_46_0,
|
| 5702 |
|
|
N_47_0, N_44_0, N_45_0, RXRDY, \controlReg1[1]_net_1\,
|
| 5703 |
|
|
\nxtprdata_xhdl7_1[2]\, N_41_0, N_42_0, N_39_0, N_40_0,
|
| 5704 |
|
|
\controlReg1[2]_net_1\, PARITY_ERR,
|
| 5705 |
|
|
\nxtprdata_xhdl7_1[4]\, N_31_0, N_32_0, N_29_0, N_30_0,
|
| 5706 |
|
|
FRAMING_ERR, \controlReg1[4]_net_1\, N_77, \data_out[0]\,
|
| 5707 |
|
|
\controlReg2[0]_net_1\, N_59_0, \data_out[6]\,
|
| 5708 |
|
|
\controlReg2[6]_net_1\, \nxtprdata_xhdl7_1[0]\, N_51_0,
|
| 5709 |
|
|
N_52_0, N_49_0, N_50_0, TXRDY, \controlReg1[0]_net_1\,
|
| 5710 |
|
|
\nxtprdata_xhdl7_1[6]\, N_23_0, N_24_0,
|
| 5711 |
|
|
\controlReg1[6]_net_1\, un5_psel, un13_psel, N_84_mux,
|
| 5712 |
|
|
\GND\, \VCC\ : std_logic;
|
| 5713 |
|
|
|
| 5714 |
|
|
for all : top_CoreUARTapb_0_COREUART
|
| 5715 |
|
|
Use entity work.top_CoreUARTapb_0_COREUART(DEF_ARCH);
|
| 5716 |
|
|
begin
|
| 5717 |
|
|
|
| 5718 |
|
|
|
| 5719 |
|
|
\iPRDATA_RNO_0[6]\ : NOR2B
|
| 5720 |
|
|
port map(A => \controlReg1[6]_net_1\, B => N_8_0, Y =>
|
| 5721 |
|
|
N_23_0);
|
| 5722 |
|
|
|
| 5723 |
|
|
\iPRDATA_RNO_1[7]\ : NOR2
|
| 5724 |
|
|
port map(A => CoreAPB_0_APBmslave0_PADDR(4), B => N_56_0, Y
|
| 5725 |
|
|
=> N_27_0);
|
| 5726 |
|
|
|
| 5727 |
|
|
\controlReg1[5]\ : DFN1E1C0
|
| 5728 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(5), CLK => HCLK_c,
|
| 5729 |
|
|
CLR => HRESETn_c, E => un5_psel, Q =>
|
| 5730 |
|
|
\controlReg1[5]_net_1\);
|
| 5731 |
|
|
|
| 5732 |
|
|
\iPRDATA_RNO_1[0]\ : NOR2
|
| 5733 |
|
|
port map(A => N_77, B => CoreAPB_0_APBmslave0_PADDR(4), Y
|
| 5734 |
|
|
=> N_52_0);
|
| 5735 |
|
|
|
| 5736 |
|
|
\iPRDATA_RNO_2[2]\ : NOR2B
|
| 5737 |
|
|
port map(A => PARITY_ERR, B =>
|
| 5738 |
|
|
CoreAPB_0_APBmslave0_PADDR(4), Y => N_39_0);
|
| 5739 |
|
|
|
| 5740 |
|
|
\iPRDATA_RNO_2[1]\ : NOR2B
|
| 5741 |
|
|
port map(A => \controlReg1[1]_net_1\, B =>
|
| 5742 |
|
|
CoreAPB_0_APBmslave0_PADDR(3), Y => N_44_0);
|
| 5743 |
|
|
|
| 5744 |
|
|
\iPRDATA_RNO_3[4]\ : AOI1
|
| 5745 |
|
|
port map(A => \controlReg1[4]_net_1\, B =>
|
| 5746 |
|
|
CoreAPB_0_APBmslave0_PADDR(3), C =>
|
| 5747 |
|
|
CoreAPB_0_APBmslave0_PADDR(4), Y => N_30_0);
|
| 5748 |
|
|
|
| 5749 |
|
|
\iPRDATA_RNO_3[3]\ : AOI1
|
| 5750 |
|
|
port map(A => \controlReg1[3]_net_1\, B =>
|
| 5751 |
|
|
CoreAPB_0_APBmslave0_PADDR(3), C =>
|
| 5752 |
|
|
CoreAPB_0_APBmslave0_PADDR(4), Y => N_35_0);
|
| 5753 |
|
|
|
| 5754 |
|
|
\controlReg1[7]\ : DFN1E1C0
|
| 5755 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(7), CLK => HCLK_c,
|
| 5756 |
|
|
CLR => HRESETn_c, E => un5_psel, Q =>
|
| 5757 |
|
|
\controlReg1[7]_net_1\);
|
| 5758 |
|
|
|
| 5759 |
|
|
\iPRDATA[1]\ : DFN1E1C0
|
| 5760 |
|
|
port map(D => \nxtprdata_xhdl7_1[1]\, CLK => HCLK_c, CLR
|
| 5761 |
|
|
=> HRESETn_c, E => N_84_mux, Q =>
|
| 5762 |
|
|
CoreAPB_0_APBmslave0_PRDATA(1));
|
| 5763 |
|
|
|
| 5764 |
|
|
\iPRDATA_RNO[5]\ : MX2
|
| 5765 |
|
|
port map(A => N_20_0, B => N_21_0, S =>
|
| 5766 |
|
|
CoreAPB_0_APBmslave0_PADDR(2), Y =>
|
| 5767 |
|
|
\nxtprdata_xhdl7_1[5]\);
|
| 5768 |
|
|
|
| 5769 |
|
|
\controlReg2[4]\ : DFN1E1C0
|
| 5770 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(4), CLK => HCLK_c,
|
| 5771 |
|
|
CLR => HRESETn_c, E => un13_psel, Q =>
|
| 5772 |
|
|
\controlReg2[4]_net_1\);
|
| 5773 |
|
|
|
| 5774 |
|
|
\iPRDATA_RNO_2[7]\ : MX2C
|
| 5775 |
|
|
port map(A => \data_out[7]\, B => \controlReg2[7]_net_1\, S
|
| 5776 |
|
|
=> CoreAPB_0_APBmslave0_PADDR(3), Y => N_56_0);
|
| 5777 |
|
|
|
| 5778 |
|
|
\iPRDATA_RNO_2[5]\ : MX2C
|
| 5779 |
|
|
port map(A => \data_out[5]\, B => \controlReg2[5]_net_1\, S
|
| 5780 |
|
|
=> CoreAPB_0_APBmslave0_PADDR(3), Y => N_62);
|
| 5781 |
|
|
|
| 5782 |
|
|
VCC_i : VCC
|
| 5783 |
|
|
port map(Y => \VCC\);
|
| 5784 |
|
|
|
| 5785 |
|
|
\iPRDATA[4]\ : DFN1E1C0
|
| 5786 |
|
|
port map(D => \nxtprdata_xhdl7_1[4]\, CLK => HCLK_c, CLR
|
| 5787 |
|
|
=> HRESETn_c, E => N_84_mux, Q =>
|
| 5788 |
|
|
CoreAPB_0_APBmslave0_PRDATA(4));
|
| 5789 |
|
|
|
| 5790 |
|
|
\iPRDATA_RNO_3[0]\ : AOI1
|
| 5791 |
|
|
port map(A => \controlReg1[0]_net_1\, B =>
|
| 5792 |
|
|
CoreAPB_0_APBmslave0_PADDR(3), C =>
|
| 5793 |
|
|
CoreAPB_0_APBmslave0_PADDR(4), Y => N_50_0);
|
| 5794 |
|
|
|
| 5795 |
|
|
\iPRDATA_RNO[1]\ : MX2A
|
| 5796 |
|
|
port map(A => N_46_0, B => N_47_0, S =>
|
| 5797 |
|
|
CoreAPB_0_APBmslave0_PADDR(2), Y =>
|
| 5798 |
|
|
\nxtprdata_xhdl7_1[1]\);
|
| 5799 |
|
|
|
| 5800 |
|
|
\iPRDATA_RNO[4]\ : MX2A
|
| 5801 |
|
|
port map(A => N_31_0, B => N_32_0, S =>
|
| 5802 |
|
|
CoreAPB_0_APBmslave0_PADDR(2), Y =>
|
| 5803 |
|
|
\nxtprdata_xhdl7_1[4]\);
|
| 5804 |
|
|
|
| 5805 |
|
|
\iPRDATA[3]\ : DFN1E1C0
|
| 5806 |
|
|
port map(D => \nxtprdata_xhdl7_1[3]\, CLK => HCLK_c, CLR
|
| 5807 |
|
|
=> HRESETn_c, E => N_84_mux, Q =>
|
| 5808 |
|
|
CoreAPB_0_APBmslave0_PRDATA(3));
|
| 5809 |
|
|
|
| 5810 |
|
|
\controlReg2[6]\ : DFN1E1C0
|
| 5811 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(6), CLK => HCLK_c,
|
| 5812 |
|
|
CLR => HRESETn_c, E => un13_psel, Q =>
|
| 5813 |
|
|
\controlReg2[6]_net_1\);
|
| 5814 |
|
|
|
| 5815 |
|
|
\controlReg1[3]\ : DFN1E1C0
|
| 5816 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(3), CLK => HCLK_c,
|
| 5817 |
|
|
CLR => HRESETn_c, E => un5_psel, Q =>
|
| 5818 |
|
|
\controlReg1[3]_net_1\);
|
| 5819 |
|
|
|
| 5820 |
|
|
\iPRDATA_RNO_4[0]\ : MX2C
|
| 5821 |
|
|
port map(A => \data_out[0]\, B => \controlReg2[0]_net_1\, S
|
| 5822 |
|
|
=> CoreAPB_0_APBmslave0_PADDR(3), Y => N_77);
|
| 5823 |
|
|
|
| 5824 |
|
|
\iPRDATA_RNO_1[2]\ : NOR2
|
| 5825 |
|
|
port map(A => N_71, B => CoreAPB_0_APBmslave0_PADDR(4), Y
|
| 5826 |
|
|
=> N_42_0);
|
| 5827 |
|
|
|
| 5828 |
|
|
\controlReg1[6]\ : DFN1E1C0
|
| 5829 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(6), CLK => HCLK_c,
|
| 5830 |
|
|
CLR => HRESETn_c, E => un5_psel, Q =>
|
| 5831 |
|
|
\controlReg1[6]_net_1\);
|
| 5832 |
|
|
|
| 5833 |
|
|
\controlReg2[3]\ : DFN1E1C0
|
| 5834 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(3), CLK => HCLK_c,
|
| 5835 |
|
|
CLR => HRESETn_c, E => un13_psel, Q =>
|
| 5836 |
|
|
\controlReg2[3]_net_1\);
|
| 5837 |
|
|
|
| 5838 |
|
|
\controlReg1[2]\ : DFN1E1C0
|
| 5839 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(2), CLK => HCLK_c,
|
| 5840 |
|
|
CLR => HRESETn_c, E => un5_psel, Q =>
|
| 5841 |
|
|
\controlReg1[2]_net_1\);
|
| 5842 |
|
|
|
| 5843 |
|
|
\iPRDATA_RNO_3[2]\ : AOI1
|
| 5844 |
|
|
port map(A => PARITY_ERR, B =>
|
| 5845 |
|
|
CoreAPB_0_APBmslave0_PADDR(4), C =>
|
| 5846 |
|
|
CoreAPB_0_APBmslave0_PADDR(3), Y => N_40_0);
|
| 5847 |
|
|
|
| 5848 |
|
|
\iPRDATA_RNO_0[4]\ : MX2A
|
| 5849 |
|
|
port map(A => N_29_0, B => N_30_0, S => FRAMING_ERR, Y =>
|
| 5850 |
|
|
N_31_0);
|
| 5851 |
|
|
|
| 5852 |
|
|
\controlReg1[4]\ : DFN1E1C0
|
| 5853 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(4), CLK => HCLK_c,
|
| 5854 |
|
|
CLR => HRESETn_c, E => un5_psel, Q =>
|
| 5855 |
|
|
\controlReg1[4]_net_1\);
|
| 5856 |
|
|
|
| 5857 |
|
|
\iPRDATA[5]\ : DFN1E1C0
|
| 5858 |
|
|
port map(D => \nxtprdata_xhdl7_1[5]\, CLK => HCLK_c, CLR
|
| 5859 |
|
|
=> HRESETn_c, E => N_84_mux, Q =>
|
| 5860 |
|
|
CoreAPB_0_APBmslave0_PRDATA(5));
|
| 5861 |
|
|
|
| 5862 |
|
|
\iPRDATA[7]\ : DFN1E1C0
|
| 5863 |
|
|
port map(D => \nxtprdata_xhdl7_1[7]\, CLK => HCLK_c, CLR
|
| 5864 |
|
|
=> HRESETn_c, E => N_84_mux, Q =>
|
| 5865 |
|
|
CoreAPB_0_APBmslave0_PRDATA(7));
|
| 5866 |
|
|
|
| 5867 |
|
|
m2 : NOR2B
|
| 5868 |
|
|
port map(A => CoreAPB_0_APBmslave0_PADDR(3), B =>
|
| 5869 |
|
|
CoreAPB_0_APBmslave0_PADDR(4), Y => N_3_0);
|
| 5870 |
|
|
|
| 5871 |
|
|
\controlReg2[1]\ : DFN1E1C0
|
| 5872 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(1), CLK => HCLK_c,
|
| 5873 |
|
|
CLR => HRESETn_c, E => un13_psel, Q =>
|
| 5874 |
|
|
\controlReg2[1]_net_1\);
|
| 5875 |
|
|
|
| 5876 |
|
|
\iPRDATA_RNO[2]\ : MX2A
|
| 5877 |
|
|
port map(A => N_41_0, B => N_42_0, S =>
|
| 5878 |
|
|
CoreAPB_0_APBmslave0_PADDR(2), Y =>
|
| 5879 |
|
|
\nxtprdata_xhdl7_1[2]\);
|
| 5880 |
|
|
|
| 5881 |
|
|
\iPRDATA_RNO[0]\ : MX2A
|
| 5882 |
|
|
port map(A => N_51_0, B => N_52_0, S =>
|
| 5883 |
|
|
CoreAPB_0_APBmslave0_PADDR(2), Y =>
|
| 5884 |
|
|
\nxtprdata_xhdl7_1[0]\);
|
| 5885 |
|
|
|
| 5886 |
|
|
m10_1 : NOR3C
|
| 5887 |
|
|
port map(A => CoreAPB_0_APBmslave0_PWRITE, B =>
|
| 5888 |
|
|
CoreAPB_0_APBmslave0_PENABLE, C =>
|
| 5889 |
|
|
CoreAPB_0_APBmslave0_PSELx, Y => \m10_1\);
|
| 5890 |
|
|
|
| 5891 |
|
|
\iPRDATA_RNO_0[3]\ : MX2A
|
| 5892 |
|
|
port map(A => N_34_0, B => N_35_0, S => OVERFLOW, Y =>
|
| 5893 |
|
|
N_36_0);
|
| 5894 |
|
|
|
| 5895 |
|
|
\iPRDATA_RNO_3[1]\ : AOI1
|
| 5896 |
|
|
port map(A => \controlReg1[1]_net_1\, B =>
|
| 5897 |
|
|
CoreAPB_0_APBmslave0_PADDR(3), C =>
|
| 5898 |
|
|
CoreAPB_0_APBmslave0_PADDR(4), Y => N_45_0);
|
| 5899 |
|
|
|
| 5900 |
|
|
\controlReg2[7]\ : DFN1E1C0
|
| 5901 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(7), CLK => HCLK_c,
|
| 5902 |
|
|
CLR => HRESETn_c, E => un13_psel, Q =>
|
| 5903 |
|
|
\controlReg2[7]_net_1\);
|
| 5904 |
|
|
|
| 5905 |
|
|
\iPRDATA_RNO_0[1]\ : MX2A
|
| 5906 |
|
|
port map(A => N_44_0, B => N_45_0, S => RXRDY, Y => N_46_0);
|
| 5907 |
|
|
|
| 5908 |
|
|
\iPRDATA[2]\ : DFN1E1C0
|
| 5909 |
|
|
port map(D => \nxtprdata_xhdl7_1[2]\, CLK => HCLK_c, CLR
|
| 5910 |
|
|
=> HRESETn_c, E => N_84_mux, Q =>
|
| 5911 |
|
|
CoreAPB_0_APBmslave0_PRDATA(2));
|
| 5912 |
|
|
|
| 5913 |
|
|
GND_i : GND
|
| 5914 |
|
|
port map(Y => \GND\);
|
| 5915 |
|
|
|
| 5916 |
|
|
\iPRDATA_RNO_4[1]\ : MX2C
|
| 5917 |
|
|
port map(A => \data_out[1]\, B => \controlReg2[1]_net_1\, S
|
| 5918 |
|
|
=> CoreAPB_0_APBmslave0_PADDR(3), Y => N_74);
|
| 5919 |
|
|
|
| 5920 |
|
|
\iPRDATA_RNO_4[4]\ : MX2C
|
| 5921 |
|
|
port map(A => \data_out[4]\, B => \controlReg2[4]_net_1\, S
|
| 5922 |
|
|
=> CoreAPB_0_APBmslave0_PADDR(3), Y => N_65);
|
| 5923 |
|
|
|
| 5924 |
|
|
\controlReg2[5]\ : DFN1E1C0
|
| 5925 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(5), CLK => HCLK_c,
|
| 5926 |
|
|
CLR => HRESETn_c, E => un13_psel, Q =>
|
| 5927 |
|
|
\controlReg2[5]_net_1\);
|
| 5928 |
|
|
|
| 5929 |
|
|
\controlReg2[2]\ : DFN1E1C0
|
| 5930 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(2), CLK => HCLK_c,
|
| 5931 |
|
|
CLR => HRESETn_c, E => un13_psel, Q =>
|
| 5932 |
|
|
\controlReg2[2]_net_1\);
|
| 5933 |
|
|
|
| 5934 |
|
|
\iPRDATA_RNO_1[5]\ : NOR2
|
| 5935 |
|
|
port map(A => N_62, B => CoreAPB_0_APBmslave0_PADDR(4), Y
|
| 5936 |
|
|
=> N_21_0);
|
| 5937 |
|
|
|
| 5938 |
|
|
\iPRDATA_RNO_4[3]\ : MX2C
|
| 5939 |
|
|
port map(A => \data_out[3]\, B => \controlReg2[3]_net_1\, S
|
| 5940 |
|
|
=> CoreAPB_0_APBmslave0_PADDR(3), Y => N_68);
|
| 5941 |
|
|
|
| 5942 |
|
|
\iPRDATA_RNO_0[7]\ : NOR2B
|
| 5943 |
|
|
port map(A => N_8_0, B => \controlReg1[7]_net_1\, Y =>
|
| 5944 |
|
|
N_26_0);
|
| 5945 |
|
|
|
| 5946 |
|
|
\iPRDATA[6]\ : DFN1E1C0
|
| 5947 |
|
|
port map(D => \nxtprdata_xhdl7_1[6]\, CLK => HCLK_c, CLR
|
| 5948 |
|
|
=> HRESETn_c, E => N_84_mux, Q =>
|
| 5949 |
|
|
CoreAPB_0_APBmslave0_PRDATA(6));
|
| 5950 |
|
|
|
| 5951 |
|
|
\iPRDATA_RNO_1[3]\ : NOR2
|
| 5952 |
|
|
port map(A => N_68, B => CoreAPB_0_APBmslave0_PADDR(4), Y
|
| 5953 |
|
|
=> N_37_0);
|
| 5954 |
|
|
|
| 5955 |
|
|
\iPRDATA[0]\ : DFN1E1C0
|
| 5956 |
|
|
port map(D => \nxtprdata_xhdl7_1[0]\, CLK => HCLK_c, CLR
|
| 5957 |
|
|
=> HRESETn_c, E => N_84_mux, Q =>
|
| 5958 |
|
|
CoreAPB_0_APBmslave0_PRDATA(0));
|
| 5959 |
|
|
|
| 5960 |
|
|
uUART : top_CoreUARTapb_0_COREUART
|
| 5961 |
|
|
port map(data_out(7) => \data_out[7]\, data_out(6) =>
|
| 5962 |
|
|
\data_out[6]\, data_out(5) => \data_out[5]\, data_out(4)
|
| 5963 |
|
|
=> \data_out[4]\, data_out(3) => \data_out[3]\,
|
| 5964 |
|
|
data_out(2) => \data_out[2]\, data_out(1) =>
|
| 5965 |
|
|
\data_out[1]\, data_out(0) => \data_out[0]\,
|
| 5966 |
|
|
CoreAPB_0_APBmslave0_PWDATA(7) =>
|
| 5967 |
|
|
CoreAPB_0_APBmslave0_PWDATA(7),
|
| 5968 |
|
|
CoreAPB_0_APBmslave0_PWDATA(6) =>
|
| 5969 |
|
|
CoreAPB_0_APBmslave0_PWDATA(6),
|
| 5970 |
|
|
CoreAPB_0_APBmslave0_PWDATA(5) =>
|
| 5971 |
|
|
CoreAPB_0_APBmslave0_PWDATA(5),
|
| 5972 |
|
|
CoreAPB_0_APBmslave0_PWDATA(4) =>
|
| 5973 |
|
|
CoreAPB_0_APBmslave0_PWDATA(4),
|
| 5974 |
|
|
CoreAPB_0_APBmslave0_PWDATA(3) =>
|
| 5975 |
|
|
CoreAPB_0_APBmslave0_PWDATA(3),
|
| 5976 |
|
|
CoreAPB_0_APBmslave0_PWDATA(2) =>
|
| 5977 |
|
|
CoreAPB_0_APBmslave0_PWDATA(2),
|
| 5978 |
|
|
CoreAPB_0_APBmslave0_PWDATA(1) =>
|
| 5979 |
|
|
CoreAPB_0_APBmslave0_PWDATA(1),
|
| 5980 |
|
|
CoreAPB_0_APBmslave0_PWDATA(0) =>
|
| 5981 |
|
|
CoreAPB_0_APBmslave0_PWDATA(0),
|
| 5982 |
|
|
CoreAPB_0_APBmslave0_PADDR_0 =>
|
| 5983 |
|
|
CoreAPB_0_APBmslave0_PADDR(2), N_84_mux => N_84_mux,
|
| 5984 |
|
|
N_3_0 => N_3_0, CoreAPB_0_APBmslave0_PENABLE =>
|
| 5985 |
|
|
CoreAPB_0_APBmslave0_PENABLE, PARITY_ERR => PARITY_ERR,
|
| 5986 |
|
|
FRAMING_ERR => FRAMING_ERR, OVERFLOW => OVERFLOW, TXRDY
|
| 5987 |
|
|
=> TXRDY, TX_c => TX_c, HRESETn_c => HRESETn_c, HCLK_c
|
| 5988 |
|
|
=> HCLK_c, RXRDY => RXRDY, N_15_0 => N_15_0, m6_0 =>
|
| 5989 |
|
|
\m6_0\, CoreAPB_0_APBmslave0_PWRITE =>
|
| 5990 |
|
|
CoreAPB_0_APBmslave0_PWRITE, CoreAPB_0_APBmslave0_PSELx
|
| 5991 |
|
|
=> CoreAPB_0_APBmslave0_PSELx);
|
| 5992 |
|
|
|
| 5993 |
|
|
\iPRDATA_RNO_2[3]\ : NOR2B
|
| 5994 |
|
|
port map(A => N_8_0, B => \controlReg1[3]_net_1\, Y =>
|
| 5995 |
|
|
N_34_0);
|
| 5996 |
|
|
|
| 5997 |
|
|
\iPRDATA_RNO_0[2]\ : MX2A
|
| 5998 |
|
|
port map(A => N_39_0, B => N_40_0, S =>
|
| 5999 |
|
|
\controlReg1[2]_net_1\, Y => N_41_0);
|
| 6000 |
|
|
|
| 6001 |
|
|
\iPRDATA_RNO_0[5]\ : NOR2B
|
| 6002 |
|
|
port map(A => \controlReg1[5]_net_1\, B =>
|
| 6003 |
|
|
CoreAPB_0_APBmslave0_PADDR(3), Y => N_20_0);
|
| 6004 |
|
|
|
| 6005 |
|
|
m7 : NOR2A
|
| 6006 |
|
|
port map(A => CoreAPB_0_APBmslave0_PADDR(3), B =>
|
| 6007 |
|
|
CoreAPB_0_APBmslave0_PADDR(4), Y => N_8_0);
|
| 6008 |
|
|
|
| 6009 |
|
|
\iPRDATA_RNO_1[6]\ : NOR2
|
| 6010 |
|
|
port map(A => N_59_0, B => CoreAPB_0_APBmslave0_PADDR(4), Y
|
| 6011 |
|
|
=> N_24_0);
|
| 6012 |
|
|
|
| 6013 |
|
|
\iPRDATA_RNO_2[6]\ : MX2C
|
| 6014 |
|
|
port map(A => \data_out[6]\, B => \controlReg2[6]_net_1\, S
|
| 6015 |
|
|
=> CoreAPB_0_APBmslave0_PADDR(3), Y => N_59_0);
|
| 6016 |
|
|
|
| 6017 |
|
|
\iPRDATA_RNO_1[1]\ : NOR2
|
| 6018 |
|
|
port map(A => N_74, B => CoreAPB_0_APBmslave0_PADDR(4), Y
|
| 6019 |
|
|
=> N_47_0);
|
| 6020 |
|
|
|
| 6021 |
|
|
\iPRDATA_RNO_2[0]\ : NOR2B
|
| 6022 |
|
|
port map(A => \controlReg1[0]_net_1\, B => N_8_0, Y =>
|
| 6023 |
|
|
N_49_0);
|
| 6024 |
|
|
|
| 6025 |
|
|
m6_0 : NOR2A
|
| 6026 |
|
|
port map(A => CoreAPB_0_APBmslave0_PSELx, B =>
|
| 6027 |
|
|
CoreAPB_0_APBmslave0_PWRITE, Y => \m6_0\);
|
| 6028 |
|
|
|
| 6029 |
|
|
\iPRDATA_RNO_4[2]\ : MX2C
|
| 6030 |
|
|
port map(A => \data_out[2]\, B => \controlReg2[2]_net_1\, S
|
| 6031 |
|
|
=> CoreAPB_0_APBmslave0_PADDR(3), Y => N_71);
|
| 6032 |
|
|
|
| 6033 |
|
|
\controlReg2[0]\ : DFN1E1C0
|
| 6034 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(0), CLK => HCLK_c,
|
| 6035 |
|
|
CLR => HRESETn_c, E => un13_psel, Q =>
|
| 6036 |
|
|
\controlReg2[0]_net_1\);
|
| 6037 |
|
|
|
| 6038 |
|
|
\iPRDATA_RNO[7]\ : MX2
|
| 6039 |
|
|
port map(A => N_26_0, B => N_27_0, S =>
|
| 6040 |
|
|
CoreAPB_0_APBmslave0_PADDR(2), Y =>
|
| 6041 |
|
|
\nxtprdata_xhdl7_1[7]\);
|
| 6042 |
|
|
|
| 6043 |
|
|
\iPRDATA_RNO_2[4]\ : NOR2B
|
| 6044 |
|
|
port map(A => \controlReg1[4]_net_1\, B =>
|
| 6045 |
|
|
CoreAPB_0_APBmslave0_PADDR(3), Y => N_29_0);
|
| 6046 |
|
|
|
| 6047 |
|
|
m11 : NOR3C
|
| 6048 |
|
|
port map(A => N_8_0, B => \m10_1\, C =>
|
| 6049 |
|
|
CoreAPB_0_APBmslave0_PADDR(2), Y => un13_psel);
|
| 6050 |
|
|
|
| 6051 |
|
|
\controlReg1[1]\ : DFN1E1C0
|
| 6052 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(1), CLK => HCLK_c,
|
| 6053 |
|
|
CLR => HRESETn_c, E => un5_psel, Q =>
|
| 6054 |
|
|
\controlReg1[1]_net_1\);
|
| 6055 |
|
|
|
| 6056 |
|
|
\iPRDATA_RNO_0[0]\ : MX2A
|
| 6057 |
|
|
port map(A => N_49_0, B => N_50_0, S => TXRDY, Y => N_51_0);
|
| 6058 |
|
|
|
| 6059 |
|
|
m12 : NOR3B
|
| 6060 |
|
|
port map(A => N_8_0, B => \m10_1\, C =>
|
| 6061 |
|
|
CoreAPB_0_APBmslave0_PADDR(2), Y => un5_psel);
|
| 6062 |
|
|
|
| 6063 |
|
|
\iPRDATA_RNO_1[4]\ : NOR2
|
| 6064 |
|
|
port map(A => N_65, B => CoreAPB_0_APBmslave0_PADDR(4), Y
|
| 6065 |
|
|
=> N_32_0);
|
| 6066 |
|
|
|
| 6067 |
|
|
\iPRDATA_RNO[3]\ : MX2A
|
| 6068 |
|
|
port map(A => N_36_0, B => N_37_0, S =>
|
| 6069 |
|
|
CoreAPB_0_APBmslave0_PADDR(2), Y =>
|
| 6070 |
|
|
\nxtprdata_xhdl7_1[3]\);
|
| 6071 |
|
|
|
| 6072 |
|
|
m14 : NOR3A
|
| 6073 |
|
|
port map(A => CoreAPB_0_APBmslave0_PENABLE, B =>
|
| 6074 |
|
|
CoreAPB_0_APBmslave0_PADDR(4), C =>
|
| 6075 |
|
|
CoreAPB_0_APBmslave0_PADDR(3), Y => N_15_0);
|
| 6076 |
|
|
|
| 6077 |
|
|
\controlReg1[0]\ : DFN1E1C0
|
| 6078 |
|
|
port map(D => CoreAPB_0_APBmslave0_PWDATA(0), CLK => HCLK_c,
|
| 6079 |
|
|
CLR => HRESETn_c, E => un5_psel, Q =>
|
| 6080 |
|
|
\controlReg1[0]_net_1\);
|
| 6081 |
|
|
|
| 6082 |
|
|
\iPRDATA_RNO[6]\ : MX2
|
| 6083 |
|
|
port map(A => N_23_0, B => N_24_0, S =>
|
| 6084 |
|
|
CoreAPB_0_APBmslave0_PADDR(2), Y =>
|
| 6085 |
|
|
\nxtprdata_xhdl7_1[6]\);
|
| 6086 |
|
|
|
| 6087 |
|
|
|
| 6088 |
|
|
end DEF_ARCH;
|
| 6089 |
|
|
|
| 6090 |
|
|
library ieee;
|
| 6091 |
|
|
use ieee.std_logic_1164.all;
|
| 6092 |
|
|
library proasic3;
|
| 6093 |
|
|
use proasic3.all;
|
| 6094 |
|
|
|
| 6095 |
|
|
entity CoreAHB2APB is
|
| 6096 |
|
|
|
| 6097 |
|
|
port( CoreAHBLite_0_AHBmslave0_HWDATA : in std_logic_vector(7 downto 0);
|
| 6098 |
|
|
CoreAPB_0_APBmslave0_PWDATA : out std_logic_vector(7 downto 0);
|
| 6099 |
|
|
CoreAPB_0_APBmslave0_PADDR : out std_logic_vector(4 downto 2);
|
| 6100 |
|
|
CoreAHB2APB_0_APBmaster_PSELx : out std_logic_vector(15 downto 1);
|
| 6101 |
|
|
arbRegSMCurrentState_i_0_0 : in std_logic;
|
| 6102 |
|
|
arbRegSMCurrentState_i_0_3 : in std_logic;
|
| 6103 |
|
|
xhdl1222_0 : in std_logic;
|
| 6104 |
|
|
masterAddrInProg_i_1_0 : in std_logic;
|
| 6105 |
|
|
arbRegSMCurrentState_RNICAHF7_0 : in std_logic;
|
| 6106 |
|
|
CoreAPB_0_APBmslave0_PWRITE : out std_logic;
|
| 6107 |
|
|
CoreAPB_0_APBmslave0_PSELx : out std_logic;
|
| 6108 |
|
|
HRESETn_c : in std_logic;
|
| 6109 |
|
|
HCLK_c : in std_logic;
|
| 6110 |
|
|
CoreAPB_0_APBmslave0_PENABLE : out std_logic;
|
| 6111 |
|
|
N_124_0 : in std_logic;
|
| 6112 |
|
|
N_128_0 : in std_logic;
|
| 6113 |
|
|
N_22 : in std_logic;
|
| 6114 |
|
|
N_20 : in std_logic;
|
| 6115 |
|
|
N_18 : in std_logic;
|
| 6116 |
|
|
N_395 : in std_logic;
|
| 6117 |
|
|
N_363 : in std_logic;
|
| 6118 |
|
|
N_364 : in std_logic;
|
| 6119 |
|
|
HTRANS_0_a3_i_a2_3_0 : in std_logic;
|
| 6120 |
|
|
N_265 : in std_logic;
|
| 6121 |
|
|
N_392 : in std_logic;
|
| 6122 |
|
|
N_135 : in std_logic;
|
| 6123 |
|
|
N_367 : in std_logic;
|
| 6124 |
|
|
defSlaveSMCurrentState : in std_logic;
|
| 6125 |
|
|
N_391 : in std_logic;
|
| 6126 |
|
|
HTRANS_0_a3_i_a2_4_0 : in std_logic;
|
| 6127 |
|
|
N_398 : out std_logic;
|
| 6128 |
|
|
un1_N_11_mux_i_5_a1_1 : out std_logic;
|
| 6129 |
|
|
N_327 : in std_logic;
|
| 6130 |
|
|
un4_m5_0_a3_1 : out std_logic;
|
| 6131 |
|
|
un4_m5_0_a3_2 : out std_logic;
|
| 6132 |
|
|
N_171 : in std_logic;
|
| 6133 |
|
|
N_330 : in std_logic;
|
| 6134 |
|
|
N_397 : in std_logic;
|
| 6135 |
|
|
N_326 : in std_logic;
|
| 6136 |
|
|
un1_m1_e_0_0 : out std_logic;
|
| 6137 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY : out std_logic;
|
| 6138 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx : in std_logic;
|
| 6139 |
|
|
HADDR_24_0_a3_i_out : in std_logic;
|
| 6140 |
|
|
N_263 : in std_logic;
|
| 6141 |
|
|
N_323 : in std_logic;
|
| 6142 |
|
|
N_365 : in std_logic;
|
| 6143 |
|
|
N_254 : in std_logic;
|
| 6144 |
|
|
N_120 : in std_logic
|
| 6145 |
|
|
);
|
| 6146 |
|
|
|
| 6147 |
|
|
end CoreAHB2APB;
|
| 6148 |
|
|
|
| 6149 |
|
|
architecture DEF_ARCH of CoreAHB2APB is
|
| 6150 |
|
|
|
| 6151 |
|
|
component NOR3B
|
| 6152 |
|
|
port( A : in std_logic := 'U';
|
| 6153 |
|
|
B : in std_logic := 'U';
|
| 6154 |
|
|
C : in std_logic := 'U';
|
| 6155 |
|
|
Y : out std_logic
|
| 6156 |
|
|
);
|
| 6157 |
|
|
end component;
|
| 6158 |
|
|
|
| 6159 |
|
|
component NOR3C
|
| 6160 |
|
|
port( A : in std_logic := 'U';
|
| 6161 |
|
|
B : in std_logic := 'U';
|
| 6162 |
|
|
C : in std_logic := 'U';
|
| 6163 |
|
|
Y : out std_logic
|
| 6164 |
|
|
);
|
| 6165 |
|
|
end component;
|
| 6166 |
|
|
|
| 6167 |
|
|
component AO1
|
| 6168 |
|
|
port( A : in std_logic := 'U';
|
| 6169 |
|
|
B : in std_logic := 'U';
|
| 6170 |
|
|
C : in std_logic := 'U';
|
| 6171 |
|
|
Y : out std_logic
|
| 6172 |
|
|
);
|
| 6173 |
|
|
end component;
|
| 6174 |
|
|
|
| 6175 |
|
|
component DFN1E0C0
|
| 6176 |
|
|
port( D : in std_logic := 'U';
|
| 6177 |
|
|
CLK : in std_logic := 'U';
|
| 6178 |
|
|
CLR : in std_logic := 'U';
|
| 6179 |
|
|
E : in std_logic := 'U';
|
| 6180 |
|
|
Q : out std_logic
|
| 6181 |
|
|
);
|
| 6182 |
|
|
end component;
|
| 6183 |
|
|
|
| 6184 |
|
|
component NOR3A
|
| 6185 |
|
|
port( A : in std_logic := 'U';
|
| 6186 |
|
|
B : in std_logic := 'U';
|
| 6187 |
|
|
C : in std_logic := 'U';
|
| 6188 |
|
|
Y : out std_logic
|
| 6189 |
|
|
);
|
| 6190 |
|
|
end component;
|
| 6191 |
|
|
|
| 6192 |
|
|
component OAI1
|
| 6193 |
|
|
port( A : in std_logic := 'U';
|
| 6194 |
|
|
B : in std_logic := 'U';
|
| 6195 |
|
|
C : in std_logic := 'U';
|
| 6196 |
|
|
Y : out std_logic
|
| 6197 |
|
|
);
|
| 6198 |
|
|
end component;
|
| 6199 |
|
|
|
| 6200 |
|
|
component NOR2A
|
| 6201 |
|
|
port( A : in std_logic := 'U';
|
| 6202 |
|
|
B : in std_logic := 'U';
|
| 6203 |
|
|
Y : out std_logic
|
| 6204 |
|
|
);
|
| 6205 |
|
|
end component;
|
| 6206 |
|
|
|
| 6207 |
|
|
component NOR2
|
| 6208 |
|
|
port( A : in std_logic := 'U';
|
| 6209 |
|
|
B : in std_logic := 'U';
|
| 6210 |
|
|
Y : out std_logic
|
| 6211 |
|
|
);
|
| 6212 |
|
|
end component;
|
| 6213 |
|
|
|
| 6214 |
|
|
component DFN1E1C0
|
| 6215 |
|
|
port( D : in std_logic := 'U';
|
| 6216 |
|
|
CLK : in std_logic := 'U';
|
| 6217 |
|
|
CLR : in std_logic := 'U';
|
| 6218 |
|
|
E : in std_logic := 'U';
|
| 6219 |
|
|
Q : out std_logic
|
| 6220 |
|
|
);
|
| 6221 |
|
|
end component;
|
| 6222 |
|
|
|
| 6223 |
|
|
component NOR2B
|
| 6224 |
|
|
port( A : in std_logic := 'U';
|
| 6225 |
|
|
B : in std_logic := 'U';
|
| 6226 |
|
|
Y : out std_logic
|
| 6227 |
|
|
);
|
| 6228 |
|
|
end component;
|
| 6229 |
|
|
|
| 6230 |
|
|
component MX2
|
| 6231 |
|
|
port( A : in std_logic := 'U';
|
| 6232 |
|
|
B : in std_logic := 'U';
|
| 6233 |
|
|
S : in std_logic := 'U';
|
| 6234 |
|
|
Y : out std_logic
|
| 6235 |
|
|
);
|
| 6236 |
|
|
end component;
|
| 6237 |
|
|
|
| 6238 |
|
|
component DFN1P0
|
| 6239 |
|
|
port( D : in std_logic := 'U';
|
| 6240 |
|
|
CLK : in std_logic := 'U';
|
| 6241 |
|
|
PRE : in std_logic := 'U';
|
| 6242 |
|
|
Q : out std_logic
|
| 6243 |
|
|
);
|
| 6244 |
|
|
end component;
|
| 6245 |
|
|
|
| 6246 |
|
|
component AO1D
|
| 6247 |
|
|
port( A : in std_logic := 'U';
|
| 6248 |
|
|
B : in std_logic := 'U';
|
| 6249 |
|
|
C : in std_logic := 'U';
|
| 6250 |
|
|
Y : out std_logic
|
| 6251 |
|
|
);
|
| 6252 |
|
|
end component;
|
| 6253 |
|
|
|
| 6254 |
|
|
component AO1B
|
| 6255 |
|
|
port( A : in std_logic := 'U';
|
| 6256 |
|
|
B : in std_logic := 'U';
|
| 6257 |
|
|
C : in std_logic := 'U';
|
| 6258 |
|
|
Y : out std_logic
|
| 6259 |
|
|
);
|
| 6260 |
|
|
end component;
|
| 6261 |
|
|
|
| 6262 |
|
|
component OR2A
|
| 6263 |
|
|
port( A : in std_logic := 'U';
|
| 6264 |
|
|
B : in std_logic := 'U';
|
| 6265 |
|
|
Y : out std_logic
|
| 6266 |
|
|
);
|
| 6267 |
|
|
end component;
|
| 6268 |
|
|
|
| 6269 |
|
|
component OR3A
|
| 6270 |
|
|
port( A : in std_logic := 'U';
|
| 6271 |
|
|
B : in std_logic := 'U';
|
| 6272 |
|
|
C : in std_logic := 'U';
|
| 6273 |
|
|
Y : out std_logic
|
| 6274 |
|
|
);
|
| 6275 |
|
|
end component;
|
| 6276 |
|
|
|
| 6277 |
|
|
component GND
|
| 6278 |
|
|
port( Y : out std_logic
|
| 6279 |
|
|
);
|
| 6280 |
|
|
end component;
|
| 6281 |
|
|
|
| 6282 |
|
|
component AOI1B
|
| 6283 |
|
|
port( A : in std_logic := 'U';
|
| 6284 |
|
|
B : in std_logic := 'U';
|
| 6285 |
|
|
C : in std_logic := 'U';
|
| 6286 |
|
|
Y : out std_logic
|
| 6287 |
|
|
);
|
| 6288 |
|
|
end component;
|
| 6289 |
|
|
|
| 6290 |
|
|
component OR3
|
| 6291 |
|
|
port( A : in std_logic := 'U';
|
| 6292 |
|
|
B : in std_logic := 'U';
|
| 6293 |
|
|
C : in std_logic := 'U';
|
| 6294 |
|
|
Y : out std_logic
|
| 6295 |
|
|
);
|
| 6296 |
|
|
end component;
|
| 6297 |
|
|
|
| 6298 |
|
|
component NOR3
|
| 6299 |
|
|
port( A : in std_logic := 'U';
|
| 6300 |
|
|
B : in std_logic := 'U';
|
| 6301 |
|
|
C : in std_logic := 'U';
|
| 6302 |
|
|
Y : out std_logic
|
| 6303 |
|
|
);
|
| 6304 |
|
|
end component;
|
| 6305 |
|
|
|
| 6306 |
|
|
component OR2
|
| 6307 |
|
|
port( A : in std_logic := 'U';
|
| 6308 |
|
|
B : in std_logic := 'U';
|
| 6309 |
|
|
Y : out std_logic
|
| 6310 |
|
|
);
|
| 6311 |
|
|
end component;
|
| 6312 |
|
|
|
| 6313 |
|
|
component DFN1C0
|
| 6314 |
|
|
port( D : in std_logic := 'U';
|
| 6315 |
|
|
CLK : in std_logic := 'U';
|
| 6316 |
|
|
CLR : in std_logic := 'U';
|
| 6317 |
|
|
Q : out std_logic
|
| 6318 |
|
|
);
|
| 6319 |
|
|
end component;
|
| 6320 |
|
|
|
| 6321 |
|
|
component VCC
|
| 6322 |
|
|
port( Y : out std_logic
|
| 6323 |
|
|
);
|
| 6324 |
|
|
end component;
|
| 6325 |
|
|
|
| 6326 |
|
|
component AO1A
|
| 6327 |
|
|
port( A : in std_logic := 'U';
|
| 6328 |
|
|
B : in std_logic := 'U';
|
| 6329 |
|
|
C : in std_logic := 'U';
|
| 6330 |
|
|
Y : out std_logic
|
| 6331 |
|
|
);
|
| 6332 |
|
|
end component;
|
| 6333 |
|
|
|
| 6334 |
|
|
component OA1C
|
| 6335 |
|
|
port( A : in std_logic := 'U';
|
| 6336 |
|
|
B : in std_logic := 'U';
|
| 6337 |
|
|
C : in std_logic := 'U';
|
| 6338 |
|
|
Y : out std_logic
|
| 6339 |
|
|
);
|
| 6340 |
|
|
end component;
|
| 6341 |
|
|
|
| 6342 |
|
|
component OA1A
|
| 6343 |
|
|
port( A : in std_logic := 'U';
|
| 6344 |
|
|
B : in std_logic := 'U';
|
| 6345 |
|
|
C : in std_logic := 'U';
|
| 6346 |
|
|
Y : out std_logic
|
| 6347 |
|
|
);
|
| 6348 |
|
|
end component;
|
| 6349 |
|
|
|
| 6350 |
|
|
component INV
|
| 6351 |
|
|
port( A : in std_logic := 'U';
|
| 6352 |
|
|
Y : out std_logic
|
| 6353 |
|
|
);
|
| 6354 |
|
|
end component;
|
| 6355 |
|
|
|
| 6356 |
|
|
signal \CurrentState_i[6]\, \CurrentState[6]_net_1\,
|
| 6357 |
|
|
\CurrentState_ns_i_0_0[1]\, N_55, \NextState[2]\,
|
| 6358 |
|
|
HreadyNext_0_0_0, HreadyNext_m4_0_0, HreadyNext_N_4,
|
| 6359 |
|
|
Psel1Mux_0_a2_0_1, Psel12Mux_0_a2_6_0, N_117,
|
| 6360 |
|
|
Psel5Mux_m1_e_2, N_37, Psel0Mux_0_a2_0_1, Psel5Mux_m1_e_1,
|
| 6361 |
|
|
N_118, Psel8Mux_0_a2_0_1, N_119, Psel9Mux_0_a2_0_1,
|
| 6362 |
|
|
Psel4Mux_m2_e_0_1, Psel2Mux_0_a2_0_2, Psel14Mux_0_a2_0_1,
|
| 6363 |
|
|
N_116, Psel13Mux_0_a2_0_1, HreadyNext_0_0_a2_0, N_54,
|
| 6364 |
|
|
N_34, \un1_N_11_mux_i_0_4\, \un4_valid_4_2\,
|
| 6365 |
|
|
\un1_N_11_mux_i_0_2\, \un1_N_11_mux_i_0_1\,
|
| 6366 |
|
|
\un1_N_11_mux_i_5_a0\, \un1_N_11_mux_i_5_a1\, N_366,
|
| 6367 |
|
|
Psel15Mux_0_a2_0_4, \un4_valid_4\, Psel15Mux_0_a2_0_2,
|
| 6368 |
|
|
Psel15Mux_0_a2_0_0, un1_m5_0_a2_1_0, un4_valid_2,
|
| 6369 |
|
|
un4_N_13_mux, un4_valid_0,
|
| 6370 |
|
|
\CoreAHBLite_0_AHBmslave0_HREADY\,
|
| 6371 |
|
|
\CurrentState[0]_net_1\, \CurrentState[2]_net_1\,
|
| 6372 |
|
|
\un4_valid_4_1\, un1_m5_0_a2_5_2, un1_m1_e_0_0_net_1,
|
| 6373 |
|
|
un1_m5_0_a2_5_1, HreadyNext_m2_e_0, un4_m5_0_a3_2_net_1,
|
| 6374 |
|
|
un4_m5_0_a3_1_net_1, un1_N_11_mux_i_5_a1_1_net_1, \N_398\,
|
| 6375 |
|
|
\un1_N_11_mux_i_5_a0_1\, HreadyNext_N_7_mux,
|
| 6376 |
|
|
\iHREADYOUT_RNIAOEJP1\, HreadyNext, N_98, N_97,
|
| 6377 |
|
|
\CurrentState_RNO[6]_net_1\, N_520, \CurrentState_i_0[5]\,
|
| 6378 |
|
|
\CurrentState_i_0[1]\, \CurrentState[7]_net_1\, N_102,
|
| 6379 |
|
|
un1_N_5_mux, \un1_m5_0_a2_a1\, Psel12Mux, N_71, Psel11Mux,
|
| 6380 |
|
|
N_73, Psel4Mux_N_7_mux, N_87, Psel6Mux_N_7_mux, N_83,
|
| 6381 |
|
|
Psel5Mux_N_5_mux_0, N_85, \HaddrReg[26]_net_1\, N_124,
|
| 6382 |
|
|
\HaddrReg[27]_net_1\, N_91, N_127, N_93, N_128, N_95,
|
| 6383 |
|
|
N_104, \CurrentState_ns[4]\, N_123, \HaddrReg[24]_net_1\,
|
| 6384 |
|
|
\HaddrReg[25]_net_1\, N_339, Psel2Mux, Psel1Mux, Psel0Mux,
|
| 6385 |
|
|
\HwriteReg\, \CurrentState[4]_net_1\,
|
| 6386 |
|
|
\CurrentState[3]_net_1\, \CurrentState_RNO[2]_net_1\,
|
| 6387 |
|
|
\CurrentState_ns[7]\, N_326_0, \CurrentState_ns[6]\,
|
| 6388 |
|
|
Psel3Mux, N_89, Psel7Mux, N_81, Psel8Mux, N_79, Psel9Mux,
|
| 6389 |
|
|
N_77, Psel10Mux, N_75, Psel13Mux, N_69, Psel14Mux, N_67,
|
| 6390 |
|
|
Psel15Mux, N_65, \iHREADYOUT_RNI2L8VN\, \HaddrMux[2]\,
|
| 6391 |
|
|
\HaddrReg[2]_net_1\, \HaddrMux[3]\, \HaddrReg[3]_net_1\,
|
| 6392 |
|
|
\HaddrMux[4]\, \HaddrReg[4]_net_1\, \GND\, \VCC\
|
| 6393 |
|
|
: std_logic;
|
| 6394 |
|
|
|
| 6395 |
|
|
begin
|
| 6396 |
|
|
|
| 6397 |
|
|
N_398 <= \N_398\;
|
| 6398 |
|
|
un1_N_11_mux_i_5_a1_1 <= un1_N_11_mux_i_5_a1_1_net_1;
|
| 6399 |
|
|
un4_m5_0_a3_1 <= un4_m5_0_a3_1_net_1;
|
| 6400 |
|
|
un4_m5_0_a3_2 <= un4_m5_0_a3_2_net_1;
|
| 6401 |
|
|
un1_m1_e_0_0 <= un1_m1_e_0_0_net_1;
|
| 6402 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY <=
|
| 6403 |
|
|
\CoreAHBLite_0_AHBmslave0_HREADY\;
|
| 6404 |
|
|
|
| 6405 |
|
|
\HaddrReg_RNINSQI[24]\ : NOR3B
|
| 6406 |
|
|
port map(A => \HaddrReg[24]_net_1\, B =>
|
| 6407 |
|
|
\HaddrReg[25]_net_1\, C => N_339, Y => N_123);
|
| 6408 |
|
|
|
| 6409 |
|
|
iPSEL13_RNO_0 : NOR3C
|
| 6410 |
|
|
port map(A => arbRegSMCurrentState_RNICAHF7_0, B =>
|
| 6411 |
|
|
Psel12Mux_0_a2_6_0, C => N_116, Y => Psel13Mux_0_a2_0_1);
|
| 6412 |
|
|
|
| 6413 |
|
|
iPSEL15_RNO : AO1
|
| 6414 |
|
|
port map(A => Psel15Mux_0_a2_0_4, B => N_116, C => N_65, Y
|
| 6415 |
|
|
=> Psel15Mux);
|
| 6416 |
|
|
|
| 6417 |
|
|
\PADDR[2]\ : DFN1E0C0
|
| 6418 |
|
|
port map(D => \HaddrMux[2]\, CLK => HCLK_c, CLR =>
|
| 6419 |
|
|
HRESETn_c, E => N_326_0, Q =>
|
| 6420 |
|
|
CoreAPB_0_APBmslave0_PADDR(2));
|
| 6421 |
|
|
|
| 6422 |
|
|
\HaddrReg_RNINSQI_1[24]\ : NOR3A
|
| 6423 |
|
|
port map(A => \HaddrReg[25]_net_1\, B => N_339, C =>
|
| 6424 |
|
|
\HaddrReg[24]_net_1\, Y => N_127);
|
| 6425 |
|
|
|
| 6426 |
|
|
un1_m2_0 : OAI1
|
| 6427 |
|
|
port map(A => N_327, B => N_171, C => un1_m1_e_0_0_net_1, Y
|
| 6428 |
|
|
=> un1_N_5_mux);
|
| 6429 |
|
|
|
| 6430 |
|
|
iHREADYOUT_RNIJJ351 : NOR2A
|
| 6431 |
|
|
port map(A => \CoreAHBLite_0_AHBmslave0_HREADY\, B => N_263,
|
| 6432 |
|
|
Y => un4_valid_0);
|
| 6433 |
|
|
|
| 6434 |
|
|
iHREADYOUT_RNI3NEKC1_0 : NOR2
|
| 6435 |
|
|
port map(A => N_37, B => N_120, Y => Psel5Mux_m1_e_2);
|
| 6436 |
|
|
|
| 6437 |
|
|
\HaddrReg[27]\ : DFN1E1C0
|
| 6438 |
|
|
port map(D => N_128_0, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 6439 |
|
|
=> \iHREADYOUT_RNI2L8VN\, Q => \HaddrReg[27]_net_1\);
|
| 6440 |
|
|
|
| 6441 |
|
|
iHREADYOUT_RNO_2 : NOR2B
|
| 6442 |
|
|
port map(A => HreadyNext_0_0_a2_0, B => N_135, Y => N_97);
|
| 6443 |
|
|
|
| 6444 |
|
|
\un4_m5_0_a3_1\ : NOR2A
|
| 6445 |
|
|
port map(A => N_397, B => N_327, Y => un4_m5_0_a3_1_net_1);
|
| 6446 |
|
|
|
| 6447 |
|
|
un1_N_11_mux_i_5_a0 : NOR3C
|
| 6448 |
|
|
port map(A => \un1_N_11_mux_i_5_a0_1\, B =>
|
| 6449 |
|
|
HTRANS_0_a3_i_a2_4_0, C => N_392, Y =>
|
| 6450 |
|
|
\un1_N_11_mux_i_5_a0\);
|
| 6451 |
|
|
|
| 6452 |
|
|
\PADDR_RNO[2]\ : MX2
|
| 6453 |
|
|
port map(A => \HaddrReg[2]_net_1\, B => N_18, S => N_339, Y
|
| 6454 |
|
|
=> \HaddrMux[2]\);
|
| 6455 |
|
|
|
| 6456 |
|
|
iPSEL10 : DFN1E0C0
|
| 6457 |
|
|
port map(D => Psel10Mux, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 6458 |
|
|
=> \NextState[2]\, Q =>
|
| 6459 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(10));
|
| 6460 |
|
|
|
| 6461 |
|
|
iHREADYOUT : DFN1P0
|
| 6462 |
|
|
port map(D => HreadyNext, CLK => HCLK_c, PRE => HRESETn_c,
|
| 6463 |
|
|
Q => \CoreAHBLite_0_AHBmslave0_HREADY\);
|
| 6464 |
|
|
|
| 6465 |
|
|
\HaddrReg[3]\ : DFN1E1C0
|
| 6466 |
|
|
port map(D => N_20, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 6467 |
|
|
\iHREADYOUT_RNI2L8VN\, Q => \HaddrReg[3]_net_1\);
|
| 6468 |
|
|
|
| 6469 |
|
|
iPSEL3_RNO : AO1
|
| 6470 |
|
|
port map(A => Psel2Mux_0_a2_0_2, B => Psel1Mux_0_a2_0_1, C
|
| 6471 |
|
|
=> N_89, Y => Psel3Mux);
|
| 6472 |
|
|
|
| 6473 |
|
|
iPSEL1_RNO_0 : NOR3A
|
| 6474 |
|
|
port map(A => N_128, B => \HaddrReg[27]_net_1\, C =>
|
| 6475 |
|
|
\HaddrReg[26]_net_1\, Y => N_93);
|
| 6476 |
|
|
|
| 6477 |
|
|
iHREADYOUT_RNO_1 : AO1D
|
| 6478 |
|
|
port map(A => HreadyNext_m4_0_0, B => HreadyNext_N_4, C =>
|
| 6479 |
|
|
\CurrentState[6]_net_1\, Y => HreadyNext_0_0_0);
|
| 6480 |
|
|
|
| 6481 |
|
|
un1_N_11_mux_i_5_a1 : NOR2B
|
| 6482 |
|
|
port map(A => un1_N_11_mux_i_5_a1_1_net_1, B => N_263, Y
|
| 6483 |
|
|
=> \un1_N_11_mux_i_5_a1\);
|
| 6484 |
|
|
|
| 6485 |
|
|
iPSEL4 : DFN1E0C0
|
| 6486 |
|
|
port map(D => Psel4Mux_N_7_mux, CLK => HCLK_c, CLR =>
|
| 6487 |
|
|
HRESETn_c, E => \NextState[2]\, Q =>
|
| 6488 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(4));
|
| 6489 |
|
|
|
| 6490 |
|
|
\CurrentState_RNIJ4KGQ_0[4]\ : NOR3C
|
| 6491 |
|
|
port map(A => arbRegSMCurrentState_RNICAHF7_0, B =>
|
| 6492 |
|
|
Psel12Mux_0_a2_6_0, C => N_118, Y => Psel5Mux_m1_e_1);
|
| 6493 |
|
|
|
| 6494 |
|
|
\CurrentState_RNIJ4KGQ_5[4]\ : NOR3B
|
| 6495 |
|
|
port map(A => Psel12Mux_0_a2_6_0, B => N_118, C =>
|
| 6496 |
|
|
arbRegSMCurrentState_RNICAHF7_0, Y => Psel4Mux_m2_e_0_1);
|
| 6497 |
|
|
|
| 6498 |
|
|
\CurrentState_RNIJ4KGQ_4[4]\ : NOR3B
|
| 6499 |
|
|
port map(A => Psel12Mux_0_a2_6_0, B => N_119, C =>
|
| 6500 |
|
|
arbRegSMCurrentState_RNICAHF7_0, Y => Psel8Mux_0_a2_0_1);
|
| 6501 |
|
|
|
| 6502 |
|
|
iPSEL0_RNO_0 : NOR3A
|
| 6503 |
|
|
port map(A => N_124, B => \HaddrReg[27]_net_1\, C =>
|
| 6504 |
|
|
\HaddrReg[26]_net_1\, Y => N_95);
|
| 6505 |
|
|
|
| 6506 |
|
|
iPSEL9 : DFN1E0C0
|
| 6507 |
|
|
port map(D => Psel9Mux, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 6508 |
|
|
=> \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(9));
|
| 6509 |
|
|
|
| 6510 |
|
|
iPSEL13_RNO : AO1
|
| 6511 |
|
|
port map(A => Psel5Mux_m1_e_2, B => Psel13Mux_0_a2_0_1, C
|
| 6512 |
|
|
=> N_69, Y => Psel13Mux);
|
| 6513 |
|
|
|
| 6514 |
|
|
iPSEL15_RNO_1 : NOR3C
|
| 6515 |
|
|
port map(A => \HaddrReg[27]_net_1\, B =>
|
| 6516 |
|
|
\HaddrReg[26]_net_1\, C => N_123, Y => N_65);
|
| 6517 |
|
|
|
| 6518 |
|
|
un4_m5_0 : AO1B
|
| 6519 |
|
|
port map(A => un4_m5_0_a3_2_net_1, B => un4_m5_0_a3_1_net_1,
|
| 6520 |
|
|
C => un1_m1_e_0_0_net_1, Y => un4_N_13_mux);
|
| 6521 |
|
|
|
| 6522 |
|
|
\CurrentState_RNICEQ3[2]\ : NOR2
|
| 6523 |
|
|
port map(A => \CurrentState[2]_net_1\, B => N_34, Y =>
|
| 6524 |
|
|
N_339);
|
| 6525 |
|
|
|
| 6526 |
|
|
iHREADYOUT_RNO_7 : AO1D
|
| 6527 |
|
|
port map(A => \CurrentState[3]_net_1\, B =>
|
| 6528 |
|
|
\CurrentState[2]_net_1\, C => \HwriteReg\, Y => N_54);
|
| 6529 |
|
|
|
| 6530 |
|
|
iHREADYOUT_RNILAT451 : OR2A
|
| 6531 |
|
|
port map(A => un1_m5_0_a2_1_0, B => \un1_N_11_mux_i_0_4\, Y
|
| 6532 |
|
|
=> N_37);
|
| 6533 |
|
|
|
| 6534 |
|
|
\CurrentState[7]\ : DFN1P0
|
| 6535 |
|
|
port map(D => N_104, CLK => HCLK_c, PRE => HRESETn_c, Q =>
|
| 6536 |
|
|
\CurrentState[7]_net_1\);
|
| 6537 |
|
|
|
| 6538 |
|
|
\CurrentState_RNO[1]\ : OR2A
|
| 6539 |
|
|
port map(A => \CurrentState[3]_net_1\, B =>
|
| 6540 |
|
|
\iHREADYOUT_RNIAOEJP1\, Y => \CurrentState_ns[6]\);
|
| 6541 |
|
|
|
| 6542 |
|
|
iPSEL12 : DFN1E0C0
|
| 6543 |
|
|
port map(D => Psel12Mux, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 6544 |
|
|
=> \NextState[2]\, Q =>
|
| 6545 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(12));
|
| 6546 |
|
|
|
| 6547 |
|
|
iPSEL3 : DFN1E0C0
|
| 6548 |
|
|
port map(D => Psel3Mux, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 6549 |
|
|
=> \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(3));
|
| 6550 |
|
|
|
| 6551 |
|
|
un1_N_11_mux_i_0_2 : OR3A
|
| 6552 |
|
|
port map(A => N_254, B => \un1_N_11_mux_i_5_a0\, C =>
|
| 6553 |
|
|
\un1_N_11_mux_i_5_a1\, Y => \un1_N_11_mux_i_0_2\);
|
| 6554 |
|
|
|
| 6555 |
|
|
\CurrentState_RNO[3]\ : NOR2A
|
| 6556 |
|
|
port map(A => N_55, B => \iHREADYOUT_RNIAOEJP1\, Y =>
|
| 6557 |
|
|
\CurrentState_ns[4]\);
|
| 6558 |
|
|
|
| 6559 |
|
|
\PWDATA[4]\ : DFN1E1C0
|
| 6560 |
|
|
port map(D => CoreAHBLite_0_AHBmslave0_HWDATA(4), CLK =>
|
| 6561 |
|
|
HCLK_c, CLR => HRESETn_c, E => N_55, Q =>
|
| 6562 |
|
|
CoreAPB_0_APBmslave0_PWDATA(4));
|
| 6563 |
|
|
|
| 6564 |
|
|
iPSEL12_RNO : AO1
|
| 6565 |
|
|
port map(A => Psel5Mux_m1_e_2, B => Psel14Mux_0_a2_0_1, C
|
| 6566 |
|
|
=> N_71, Y => Psel12Mux);
|
| 6567 |
|
|
|
| 6568 |
|
|
iHREADYOUT_RNI3NEKC1 : NOR2A
|
| 6569 |
|
|
port map(A => N_120, B => N_37, Y => Psel2Mux_0_a2_0_2);
|
| 6570 |
|
|
|
| 6571 |
|
|
iPSEL2_RNO : AO1
|
| 6572 |
|
|
port map(A => Psel2Mux_0_a2_0_2, B => Psel0Mux_0_a2_0_1, C
|
| 6573 |
|
|
=> N_91, Y => Psel2Mux);
|
| 6574 |
|
|
|
| 6575 |
|
|
\un4_m5_0_a3_2\ : NOR3A
|
| 6576 |
|
|
port map(A => N_254, B => N_330, C => N_171, Y =>
|
| 6577 |
|
|
un4_m5_0_a3_2_net_1);
|
| 6578 |
|
|
|
| 6579 |
|
|
iHREADYOUT_RNO_5 : NOR2A
|
| 6580 |
|
|
port map(A => N_54, B => N_34, Y => HreadyNext_0_0_a2_0);
|
| 6581 |
|
|
|
| 6582 |
|
|
\PWDATA[7]\ : DFN1E1C0
|
| 6583 |
|
|
port map(D => CoreAHBLite_0_AHBmslave0_HWDATA(7), CLK =>
|
| 6584 |
|
|
HCLK_c, CLR => HRESETn_c, E => N_55, Q =>
|
| 6585 |
|
|
CoreAPB_0_APBmslave0_PWDATA(7));
|
| 6586 |
|
|
|
| 6587 |
|
|
GND_i : GND
|
| 6588 |
|
|
port map(Y => \GND\);
|
| 6589 |
|
|
|
| 6590 |
|
|
\PWDATA[0]\ : DFN1E1C0
|
| 6591 |
|
|
port map(D => CoreAHBLite_0_AHBmslave0_HWDATA(0), CLK =>
|
| 6592 |
|
|
HCLK_c, CLR => HRESETn_c, E => N_55, Q =>
|
| 6593 |
|
|
CoreAPB_0_APBmslave0_PWDATA(0));
|
| 6594 |
|
|
|
| 6595 |
|
|
iHREADYOUT_RNO_6 : AOI1B
|
| 6596 |
|
|
port map(A => HreadyNext_m2_e_0, B => N_395, C =>
|
| 6597 |
|
|
un1_m1_e_0_0_net_1, Y => HreadyNext_N_7_mux);
|
| 6598 |
|
|
|
| 6599 |
|
|
\CurrentState_RNIJ4KGQ_2[4]\ : NOR3B
|
| 6600 |
|
|
port map(A => Psel12Mux_0_a2_6_0, B => N_117, C =>
|
| 6601 |
|
|
arbRegSMCurrentState_RNICAHF7_0, Y => Psel0Mux_0_a2_0_1);
|
| 6602 |
|
|
|
| 6603 |
|
|
un4_valid_4_2 : NOR2
|
| 6604 |
|
|
port map(A => N_364, B => N_363, Y => \un4_valid_4_2\);
|
| 6605 |
|
|
|
| 6606 |
|
|
iHREADYOUT_RNO : OR3
|
| 6607 |
|
|
port map(A => N_98, B => HreadyNext_0_0_0, C => N_97, Y =>
|
| 6608 |
|
|
HreadyNext);
|
| 6609 |
|
|
|
| 6610 |
|
|
\CurrentState_RNIJ4KGQ[4]\ : NOR3C
|
| 6611 |
|
|
port map(A => arbRegSMCurrentState_RNICAHF7_0, B =>
|
| 6612 |
|
|
Psel12Mux_0_a2_6_0, C => N_117, Y => Psel1Mux_0_a2_0_1);
|
| 6613 |
|
|
|
| 6614 |
|
|
\HaddrReg[2]\ : DFN1E1C0
|
| 6615 |
|
|
port map(D => N_18, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 6616 |
|
|
\iHREADYOUT_RNI2L8VN\, Q => \HaddrReg[2]_net_1\);
|
| 6617 |
|
|
|
| 6618 |
|
|
iPSEL12_RNO_0 : NOR3C
|
| 6619 |
|
|
port map(A => \HaddrReg[27]_net_1\, B =>
|
| 6620 |
|
|
\HaddrReg[26]_net_1\, C => N_124, Y => N_71);
|
| 6621 |
|
|
|
| 6622 |
|
|
iPSEL9_RNO : AO1
|
| 6623 |
|
|
port map(A => Psel5Mux_m1_e_2, B => Psel9Mux_0_a2_0_1, C
|
| 6624 |
|
|
=> N_77, Y => Psel9Mux);
|
| 6625 |
|
|
|
| 6626 |
|
|
iPSEL15_RNO_2 : NOR3C
|
| 6627 |
|
|
port map(A => Psel12Mux_0_a2_6_0, B => Psel15Mux_0_a2_0_0,
|
| 6628 |
|
|
C => un1_m5_0_a2_1_0, Y => Psel15Mux_0_a2_0_2);
|
| 6629 |
|
|
|
| 6630 |
|
|
\CurrentState_RNIJ4KGQ_3[4]\ : NOR3B
|
| 6631 |
|
|
port map(A => Psel12Mux_0_a2_6_0, B => N_116, C =>
|
| 6632 |
|
|
arbRegSMCurrentState_RNICAHF7_0, Y => Psel14Mux_0_a2_0_1);
|
| 6633 |
|
|
|
| 6634 |
|
|
iHREADYOUT_RNO_4 : NOR3B
|
| 6635 |
|
|
port map(A => un4_valid_0, B => \un4_valid_4\, C =>
|
| 6636 |
|
|
HreadyNext_N_7_mux, Y => HreadyNext_N_4);
|
| 6637 |
|
|
|
| 6638 |
|
|
iHREADYOUT_RNO_0 : NOR2A
|
| 6639 |
|
|
port map(A => \HwriteReg\, B => \iHREADYOUT_RNIAOEJP1\, Y
|
| 6640 |
|
|
=> N_98);
|
| 6641 |
|
|
|
| 6642 |
|
|
iPSEL15_RNO_3 : NOR3
|
| 6643 |
|
|
port map(A => N_323, B => N_263, C => HADDR_24_0_a3_i_out,
|
| 6644 |
|
|
Y => Psel15Mux_0_a2_0_0);
|
| 6645 |
|
|
|
| 6646 |
|
|
iPSEL10_RNO_0 : NOR3B
|
| 6647 |
|
|
port map(A => \HaddrReg[27]_net_1\, B => N_127, C =>
|
| 6648 |
|
|
\HaddrReg[26]_net_1\, Y => N_75);
|
| 6649 |
|
|
|
| 6650 |
|
|
HwriteReg : DFN1E1C0
|
| 6651 |
|
|
port map(D => N_135, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 6652 |
|
|
\iHREADYOUT_RNI2L8VN\, Q => \HwriteReg\);
|
| 6653 |
|
|
|
| 6654 |
|
|
iPSEL7_RNO : AO1
|
| 6655 |
|
|
port map(A => Psel2Mux_0_a2_0_2, B => Psel5Mux_m1_e_1, C
|
| 6656 |
|
|
=> N_81, Y => Psel7Mux);
|
| 6657 |
|
|
|
| 6658 |
|
|
iHREADYOUT_RNI2L8VN : NOR2B
|
| 6659 |
|
|
port map(A => CoreAHBLite_0_AHBmslave0_HSELx, B =>
|
| 6660 |
|
|
\CoreAHBLite_0_AHBmslave0_HREADY\, Y =>
|
| 6661 |
|
|
\iHREADYOUT_RNI2L8VN\);
|
| 6662 |
|
|
|
| 6663 |
|
|
iPSEL8_RNO_0 : NOR3B
|
| 6664 |
|
|
port map(A => \HaddrReg[27]_net_1\, B => N_124, C =>
|
| 6665 |
|
|
\HaddrReg[26]_net_1\, Y => N_79);
|
| 6666 |
|
|
|
| 6667 |
|
|
iPSEL1 : DFN1E0C0
|
| 6668 |
|
|
port map(D => Psel1Mux, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 6669 |
|
|
=> \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(1));
|
| 6670 |
|
|
|
| 6671 |
|
|
iHREADYOUT_RNO_3 : OR2
|
| 6672 |
|
|
port map(A => \CurrentState[0]_net_1\, B =>
|
| 6673 |
|
|
\CurrentState[2]_net_1\, Y => HreadyNext_m4_0_0);
|
| 6674 |
|
|
|
| 6675 |
|
|
\CurrentState[1]\ : DFN1P0
|
| 6676 |
|
|
port map(D => \CurrentState_ns[6]\, CLK => HCLK_c, PRE =>
|
| 6677 |
|
|
HRESETn_c, Q => \CurrentState_i_0[1]\);
|
| 6678 |
|
|
|
| 6679 |
|
|
\CurrentState_RNO[0]\ : AO1
|
| 6680 |
|
|
port map(A => \CurrentState[3]_net_1\, B =>
|
| 6681 |
|
|
\iHREADYOUT_RNIAOEJP1\, C => \CurrentState[2]_net_1\, Y
|
| 6682 |
|
|
=> \CurrentState_ns[7]\);
|
| 6683 |
|
|
|
| 6684 |
|
|
\CurrentState[2]\ : DFN1C0
|
| 6685 |
|
|
port map(D => \CurrentState_RNO[2]_net_1\, CLK => HCLK_c,
|
| 6686 |
|
|
CLR => HRESETn_c, Q => \CurrentState[2]_net_1\);
|
| 6687 |
|
|
|
| 6688 |
|
|
VCC_i : VCC
|
| 6689 |
|
|
port map(Y => \VCC\);
|
| 6690 |
|
|
|
| 6691 |
|
|
iPSEL6_RNO_0 : NOR3B
|
| 6692 |
|
|
port map(A => \HaddrReg[26]_net_1\, B => N_127, C =>
|
| 6693 |
|
|
\HaddrReg[27]_net_1\, Y => N_83);
|
| 6694 |
|
|
|
| 6695 |
|
|
\CurrentState_RNO[2]\ : NOR2B
|
| 6696 |
|
|
port map(A => \iHREADYOUT_RNIAOEJP1\, B => N_55, Y =>
|
| 6697 |
|
|
\CurrentState_RNO[2]_net_1\);
|
| 6698 |
|
|
|
| 6699 |
|
|
iPSEL14_RNO_0 : NOR3C
|
| 6700 |
|
|
port map(A => \HaddrReg[27]_net_1\, B =>
|
| 6701 |
|
|
\HaddrReg[26]_net_1\, C => N_127, Y => N_67);
|
| 6702 |
|
|
|
| 6703 |
|
|
un1_N_11_mux_i_0_4 : OR3A
|
| 6704 |
|
|
port map(A => \un4_valid_4_2\, B => \un1_N_11_mux_i_0_2\, C
|
| 6705 |
|
|
=> \un1_N_11_mux_i_0_1\, Y => \un1_N_11_mux_i_0_4\);
|
| 6706 |
|
|
|
| 6707 |
|
|
iPSEL6 : DFN1E0C0
|
| 6708 |
|
|
port map(D => Psel6Mux_N_7_mux, CLK => HCLK_c, CLR =>
|
| 6709 |
|
|
HRESETn_c, E => \NextState[2]\, Q =>
|
| 6710 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(6));
|
| 6711 |
|
|
|
| 6712 |
|
|
\CurrentState_RNIEI9B51[4]\ : AO1A
|
| 6713 |
|
|
port map(A => N_34, B => N_37, C => \NextState[2]\, Y =>
|
| 6714 |
|
|
N_326_0);
|
| 6715 |
|
|
|
| 6716 |
|
|
PENABLE : DFN1C0
|
| 6717 |
|
|
port map(D => \NextState[2]\, CLK => HCLK_c, CLR =>
|
| 6718 |
|
|
HRESETn_c, Q => CoreAPB_0_APBmslave0_PENABLE);
|
| 6719 |
|
|
|
| 6720 |
|
|
\PWDATA[1]\ : DFN1E1C0
|
| 6721 |
|
|
port map(D => CoreAHBLite_0_AHBmslave0_HWDATA(1), CLK =>
|
| 6722 |
|
|
HCLK_c, CLR => HRESETn_c, E => N_55, Q =>
|
| 6723 |
|
|
CoreAPB_0_APBmslave0_PWDATA(1));
|
| 6724 |
|
|
|
| 6725 |
|
|
\un1_m1_e_0_0\ : NOR2B
|
| 6726 |
|
|
port map(A => arbRegSMCurrentState_i_0_0, B =>
|
| 6727 |
|
|
arbRegSMCurrentState_i_0_3, Y => un1_m1_e_0_0_net_1);
|
| 6728 |
|
|
|
| 6729 |
|
|
un1_N_11_mux_i_0_1 : OR2
|
| 6730 |
|
|
port map(A => N_365, B => N_366, Y => \un1_N_11_mux_i_0_1\);
|
| 6731 |
|
|
|
| 6732 |
|
|
iPSEL1_RNO : AO1
|
| 6733 |
|
|
port map(A => Psel5Mux_m1_e_2, B => Psel1Mux_0_a2_0_1, C
|
| 6734 |
|
|
=> N_93, Y => Psel1Mux);
|
| 6735 |
|
|
|
| 6736 |
|
|
iPSEL8 : DFN1E0C0
|
| 6737 |
|
|
port map(D => Psel8Mux, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 6738 |
|
|
=> \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(8));
|
| 6739 |
|
|
|
| 6740 |
|
|
iPSEL11_RNO_0 : NOR3B
|
| 6741 |
|
|
port map(A => \HaddrReg[27]_net_1\, B => N_123, C =>
|
| 6742 |
|
|
\HaddrReg[26]_net_1\, Y => N_73);
|
| 6743 |
|
|
|
| 6744 |
|
|
\CurrentState_RNO_0[6]\ : OR2
|
| 6745 |
|
|
port map(A => N_55, B => \NextState[2]\, Y =>
|
| 6746 |
|
|
\CurrentState_ns_i_0_0[1]\);
|
| 6747 |
|
|
|
| 6748 |
|
|
iPSEL8_RNO : AO1
|
| 6749 |
|
|
port map(A => Psel5Mux_m1_e_2, B => Psel8Mux_0_a2_0_1, C
|
| 6750 |
|
|
=> N_79, Y => Psel8Mux);
|
| 6751 |
|
|
|
| 6752 |
|
|
\CurrentState_RNIJLQ3[1]\ : NOR3B
|
| 6753 |
|
|
port map(A => \CurrentState_i_0[5]\, B =>
|
| 6754 |
|
|
\CurrentState_i_0[1]\, C => \CurrentState[7]_net_1\, Y
|
| 6755 |
|
|
=> N_520);
|
| 6756 |
|
|
|
| 6757 |
|
|
iPSEL4_RNO : AO1
|
| 6758 |
|
|
port map(A => Psel5Mux_m1_e_2, B => Psel4Mux_m2_e_0_1, C
|
| 6759 |
|
|
=> N_87, Y => Psel4Mux_N_7_mux);
|
| 6760 |
|
|
|
| 6761 |
|
|
iHREADYOUT_RNISPLKU : NOR3C
|
| 6762 |
|
|
port map(A => un4_N_13_mux, B => un4_valid_0, C =>
|
| 6763 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx, Y => un4_valid_2);
|
| 6764 |
|
|
|
| 6765 |
|
|
\HaddrReg[26]\ : DFN1E1C0
|
| 6766 |
|
|
port map(D => N_124_0, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 6767 |
|
|
=> \iHREADYOUT_RNI2L8VN\, Q => \HaddrReg[26]_net_1\);
|
| 6768 |
|
|
|
| 6769 |
|
|
iPSEL9_RNO_0 : NOR3B
|
| 6770 |
|
|
port map(A => \HaddrReg[27]_net_1\, B => N_128, C =>
|
| 6771 |
|
|
\HaddrReg[26]_net_1\, Y => N_77);
|
| 6772 |
|
|
|
| 6773 |
|
|
iPSEL7_RNO_0 : NOR3B
|
| 6774 |
|
|
port map(A => \HaddrReg[26]_net_1\, B => N_123, C =>
|
| 6775 |
|
|
\HaddrReg[27]_net_1\, Y => N_81);
|
| 6776 |
|
|
|
| 6777 |
|
|
iPSEL4_RNO_0 : NOR3B
|
| 6778 |
|
|
port map(A => \HaddrReg[26]_net_1\, B => N_124, C =>
|
| 6779 |
|
|
\HaddrReg[27]_net_1\, Y => N_87);
|
| 6780 |
|
|
|
| 6781 |
|
|
iPSEL2 : DFN1E0C0
|
| 6782 |
|
|
port map(D => Psel2Mux, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 6783 |
|
|
=> \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(2));
|
| 6784 |
|
|
|
| 6785 |
|
|
\un1_N_11_mux_i_5_a1_1\ : NOR2B
|
| 6786 |
|
|
port map(A => \N_398\, B => HTRANS_0_a3_i_a2_4_0, Y =>
|
| 6787 |
|
|
un1_N_11_mux_i_5_a1_1_net_1);
|
| 6788 |
|
|
|
| 6789 |
|
|
iPSEL11_RNO : AO1
|
| 6790 |
|
|
port map(A => Psel2Mux_0_a2_0_2, B => Psel9Mux_0_a2_0_1, C
|
| 6791 |
|
|
=> N_73, Y => Psel11Mux);
|
| 6792 |
|
|
|
| 6793 |
|
|
iPSEL0 : DFN1E0C0
|
| 6794 |
|
|
port map(D => Psel0Mux, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 6795 |
|
|
=> \NextState[2]\, Q => CoreAPB_0_APBmslave0_PSELx);
|
| 6796 |
|
|
|
| 6797 |
|
|
iHREADYOUT_RNI97C92 : NOR3B
|
| 6798 |
|
|
port map(A => N_326, B => \CoreAHBLite_0_AHBmslave0_HREADY\,
|
| 6799 |
|
|
C => N_263, Y => un1_m5_0_a2_5_1);
|
| 6800 |
|
|
|
| 6801 |
|
|
iPSEL3_RNO_0 : NOR3A
|
| 6802 |
|
|
port map(A => N_123, B => \HaddrReg[27]_net_1\, C =>
|
| 6803 |
|
|
\HaddrReg[26]_net_1\, Y => N_89);
|
| 6804 |
|
|
|
| 6805 |
|
|
\PADDR[3]\ : DFN1E0C0
|
| 6806 |
|
|
port map(D => \HaddrMux[3]\, CLK => HCLK_c, CLR =>
|
| 6807 |
|
|
HRESETn_c, E => N_326_0, Q =>
|
| 6808 |
|
|
CoreAPB_0_APBmslave0_PADDR(3));
|
| 6809 |
|
|
|
| 6810 |
|
|
\CurrentState[6]\ : DFN1C0
|
| 6811 |
|
|
port map(D => \CurrentState_RNO[6]_net_1\, CLK => HCLK_c,
|
| 6812 |
|
|
CLR => HRESETn_c, Q => \CurrentState[6]_net_1\);
|
| 6813 |
|
|
|
| 6814 |
|
|
iPSEL0_RNO : AO1
|
| 6815 |
|
|
port map(A => Psel5Mux_m1_e_2, B => Psel0Mux_0_a2_0_1, C
|
| 6816 |
|
|
=> N_95, Y => Psel0Mux);
|
| 6817 |
|
|
|
| 6818 |
|
|
iPSEL10_RNO : AO1
|
| 6819 |
|
|
port map(A => Psel2Mux_0_a2_0_2, B => Psel8Mux_0_a2_0_1, C
|
| 6820 |
|
|
=> N_75, Y => Psel10Mux);
|
| 6821 |
|
|
|
| 6822 |
|
|
PWRITE : DFN1E0C0
|
| 6823 |
|
|
port map(D => N_55, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 6824 |
|
|
N_326_0, Q => CoreAPB_0_APBmslave0_PWRITE);
|
| 6825 |
|
|
|
| 6826 |
|
|
iPSEL2_RNO_0 : NOR3A
|
| 6827 |
|
|
port map(A => N_127, B => \HaddrReg[27]_net_1\, C =>
|
| 6828 |
|
|
\HaddrReg[26]_net_1\, Y => N_91);
|
| 6829 |
|
|
|
| 6830 |
|
|
\HaddrReg_RNINSQI_0[24]\ : NOR3A
|
| 6831 |
|
|
port map(A => \HaddrReg[24]_net_1\, B => N_339, C =>
|
| 6832 |
|
|
\HaddrReg[25]_net_1\, Y => N_128);
|
| 6833 |
|
|
|
| 6834 |
|
|
\CurrentState[5]\ : DFN1P0
|
| 6835 |
|
|
port map(D => \CurrentState_i[6]\, CLK => HCLK_c, PRE =>
|
| 6836 |
|
|
HRESETn_c, Q => \CurrentState_i_0[5]\);
|
| 6837 |
|
|
|
| 6838 |
|
|
un4_valid_4 : NOR3B
|
| 6839 |
|
|
port map(A => \un4_valid_4_1\, B => \un4_valid_4_2\, C =>
|
| 6840 |
|
|
N_367, Y => \un4_valid_4\);
|
| 6841 |
|
|
|
| 6842 |
|
|
\HaddrReg[4]\ : DFN1E1C0
|
| 6843 |
|
|
port map(D => N_22, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 6844 |
|
|
\iHREADYOUT_RNI2L8VN\, Q => \HaddrReg[4]_net_1\);
|
| 6845 |
|
|
|
| 6846 |
|
|
\PWDATA[6]\ : DFN1E1C0
|
| 6847 |
|
|
port map(D => CoreAHBLite_0_AHBmslave0_HWDATA(6), CLK =>
|
| 6848 |
|
|
HCLK_c, CLR => HRESETn_c, E => N_55, Q =>
|
| 6849 |
|
|
CoreAPB_0_APBmslave0_PWDATA(6));
|
| 6850 |
|
|
|
| 6851 |
|
|
\CurrentState_RNO[6]\ : OA1C
|
| 6852 |
|
|
port map(A => N_37, B => \CurrentState[0]_net_1\, C =>
|
| 6853 |
|
|
\CurrentState_ns_i_0_0[1]\, Y =>
|
| 6854 |
|
|
\CurrentState_RNO[6]_net_1\);
|
| 6855 |
|
|
|
| 6856 |
|
|
\CurrentState[3]\ : DFN1C0
|
| 6857 |
|
|
port map(D => \CurrentState_ns[4]\, CLK => HCLK_c, CLR =>
|
| 6858 |
|
|
HRESETn_c, Q => \CurrentState[3]_net_1\);
|
| 6859 |
|
|
|
| 6860 |
|
|
\CurrentState[0]\ : DFN1C0
|
| 6861 |
|
|
port map(D => \CurrentState_ns[7]\, CLK => HCLK_c, CLR =>
|
| 6862 |
|
|
HRESETn_c, Q => \CurrentState[0]_net_1\);
|
| 6863 |
|
|
|
| 6864 |
|
|
iPSEL11 : DFN1E0C0
|
| 6865 |
|
|
port map(D => Psel11Mux, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 6866 |
|
|
=> \NextState[2]\, Q =>
|
| 6867 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(11));
|
| 6868 |
|
|
|
| 6869 |
|
|
iPSEL13_RNO_1 : NOR3C
|
| 6870 |
|
|
port map(A => \HaddrReg[27]_net_1\, B =>
|
| 6871 |
|
|
\HaddrReg[26]_net_1\, C => N_128, Y => N_69);
|
| 6872 |
|
|
|
| 6873 |
|
|
\PADDR_RNO[4]\ : MX2
|
| 6874 |
|
|
port map(A => \HaddrReg[4]_net_1\, B => N_22, S => N_339, Y
|
| 6875 |
|
|
=> \HaddrMux[4]\);
|
| 6876 |
|
|
|
| 6877 |
|
|
Psel3Mux_0_a2_2 : NOR2
|
| 6878 |
|
|
port map(A => N_128_0, B => N_124_0, Y => N_117);
|
| 6879 |
|
|
|
| 6880 |
|
|
iHREADYOUT_RNO_8 : NOR3A
|
| 6881 |
|
|
port map(A => N_397, B => N_330, C => N_171, Y =>
|
| 6882 |
|
|
HreadyNext_m2_e_0);
|
| 6883 |
|
|
|
| 6884 |
|
|
iPSEL5_RNO_0 : NOR3B
|
| 6885 |
|
|
port map(A => \HaddrReg[26]_net_1\, B => N_128, C =>
|
| 6886 |
|
|
\HaddrReg[27]_net_1\, Y => N_85);
|
| 6887 |
|
|
|
| 6888 |
|
|
iPSEL5 : DFN1E0C0
|
| 6889 |
|
|
port map(D => Psel5Mux_N_5_mux_0, CLK => HCLK_c, CLR =>
|
| 6890 |
|
|
HRESETn_c, E => \NextState[2]\, Q =>
|
| 6891 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(5));
|
| 6892 |
|
|
|
| 6893 |
|
|
\CurrentState_RNO[4]\ : NOR3B
|
| 6894 |
|
|
port map(A => \iHREADYOUT_RNIAOEJP1\, B => N_135, C =>
|
| 6895 |
|
|
N_520, Y => N_102);
|
| 6896 |
|
|
|
| 6897 |
|
|
\CurrentState[4]\ : DFN1C0
|
| 6898 |
|
|
port map(D => N_102, CLK => HCLK_c, CLR => HRESETn_c, Q =>
|
| 6899 |
|
|
\CurrentState[4]_net_1\);
|
| 6900 |
|
|
|
| 6901 |
|
|
\PADDR[4]\ : DFN1E0C0
|
| 6902 |
|
|
port map(D => \HaddrMux[4]\, CLK => HCLK_c, CLR =>
|
| 6903 |
|
|
HRESETn_c, E => N_326_0, Q =>
|
| 6904 |
|
|
CoreAPB_0_APBmslave0_PADDR(4));
|
| 6905 |
|
|
|
| 6906 |
|
|
iHREADYOUT_RNITE0M3 : OA1A
|
| 6907 |
|
|
port map(A => un1_m1_e_0_0_net_1, B => N_254, C =>
|
| 6908 |
|
|
un1_m5_0_a2_5_1, Y => un1_m5_0_a2_5_2);
|
| 6909 |
|
|
|
| 6910 |
|
|
\HaddrReg_RNINSQI_2[24]\ : NOR3
|
| 6911 |
|
|
port map(A => N_339, B => \HaddrReg[24]_net_1\, C =>
|
| 6912 |
|
|
\HaddrReg[25]_net_1\, Y => N_124);
|
| 6913 |
|
|
|
| 6914 |
|
|
iPSEL15 : DFN1E0C0
|
| 6915 |
|
|
port map(D => Psel15Mux, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 6916 |
|
|
=> \NextState[2]\, Q =>
|
| 6917 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(15));
|
| 6918 |
|
|
|
| 6919 |
|
|
\CurrentState_RNI8KH2[4]\ : OR2
|
| 6920 |
|
|
port map(A => \CurrentState[4]_net_1\, B =>
|
| 6921 |
|
|
\CurrentState[0]_net_1\, Y => N_34);
|
| 6922 |
|
|
|
| 6923 |
|
|
\CurrentState_RNO[5]\ : INV
|
| 6924 |
|
|
port map(A => \CurrentState[6]_net_1\, Y =>
|
| 6925 |
|
|
\CurrentState_i[6]\);
|
| 6926 |
|
|
|
| 6927 |
|
|
un1_N_11_mux_i_5_a0_1 : NOR2B
|
| 6928 |
|
|
port map(A => \N_398\, B => N_391, Y =>
|
| 6929 |
|
|
\un1_N_11_mux_i_5_a0_1\);
|
| 6930 |
|
|
|
| 6931 |
|
|
\PADDR_RNO[3]\ : MX2
|
| 6932 |
|
|
port map(A => \HaddrReg[3]_net_1\, B => N_20, S => N_339, Y
|
| 6933 |
|
|
=> \HaddrMux[3]\);
|
| 6934 |
|
|
|
| 6935 |
|
|
un1_N_11_mux_i_5_a0_0 : NOR2
|
| 6936 |
|
|
port map(A => defSlaveSMCurrentState, B => xhdl1222_0, Y
|
| 6937 |
|
|
=> \N_398\);
|
| 6938 |
|
|
|
| 6939 |
|
|
iPSEL6_RNO : AO1
|
| 6940 |
|
|
port map(A => Psel2Mux_0_a2_0_2, B => Psel4Mux_m2_e_0_1, C
|
| 6941 |
|
|
=> N_83, Y => Psel6Mux_N_7_mux);
|
| 6942 |
|
|
|
| 6943 |
|
|
Psel7Mux_0_a2_1 : NOR2A
|
| 6944 |
|
|
port map(A => N_124_0, B => N_128_0, Y => N_118);
|
| 6945 |
|
|
|
| 6946 |
|
|
\PWDATA[5]\ : DFN1E1C0
|
| 6947 |
|
|
port map(D => CoreAHBLite_0_AHBmslave0_HWDATA(5), CLK =>
|
| 6948 |
|
|
HCLK_c, CLR => HRESETn_c, E => N_55, Q =>
|
| 6949 |
|
|
CoreAPB_0_APBmslave0_PWDATA(5));
|
| 6950 |
|
|
|
| 6951 |
|
|
iPSEL5_RNO : AO1
|
| 6952 |
|
|
port map(A => Psel5Mux_m1_e_2, B => Psel5Mux_m1_e_1, C =>
|
| 6953 |
|
|
N_85, Y => Psel5Mux_N_5_mux_0);
|
| 6954 |
|
|
|
| 6955 |
|
|
iPSEL13 : DFN1E0C0
|
| 6956 |
|
|
port map(D => Psel13Mux, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 6957 |
|
|
=> \NextState[2]\, Q =>
|
| 6958 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(13));
|
| 6959 |
|
|
|
| 6960 |
|
|
\CurrentState_RNIHJQ3[6]\ : OR3
|
| 6961 |
|
|
port map(A => \CurrentState[2]_net_1\, B =>
|
| 6962 |
|
|
\CurrentState[3]_net_1\, C => \CurrentState[6]_net_1\, Y
|
| 6963 |
|
|
=> \NextState[2]\);
|
| 6964 |
|
|
|
| 6965 |
|
|
\HaddrReg[25]\ : DFN1E1C0
|
| 6966 |
|
|
port map(D => N_120, CLK => HCLK_c, CLR => HRESETn_c, E =>
|
| 6967 |
|
|
\iHREADYOUT_RNI2L8VN\, Q => \HaddrReg[25]_net_1\);
|
| 6968 |
|
|
|
| 6969 |
|
|
un1_m5_0_a2_a1 : OA1A
|
| 6970 |
|
|
port map(A => N_397, B => N_330, C => un1_m1_e_0_0_net_1, Y
|
| 6971 |
|
|
=> \un1_m5_0_a2_a1\);
|
| 6972 |
|
|
|
| 6973 |
|
|
\CurrentState_RNIF8AB[4]\ : AO1
|
| 6974 |
|
|
port map(A => \HwriteReg\, B => \CurrentState[0]_net_1\, C
|
| 6975 |
|
|
=> \CurrentState[4]_net_1\, Y => N_55);
|
| 6976 |
|
|
|
| 6977 |
|
|
\HaddrReg[24]\ : DFN1E1C0
|
| 6978 |
|
|
port map(D => arbRegSMCurrentState_RNICAHF7_0, CLK =>
|
| 6979 |
|
|
HCLK_c, CLR => HRESETn_c, E => \iHREADYOUT_RNI2L8VN\, Q
|
| 6980 |
|
|
=> \HaddrReg[24]_net_1\);
|
| 6981 |
|
|
|
| 6982 |
|
|
iPSEL14_RNO : AO1
|
| 6983 |
|
|
port map(A => Psel2Mux_0_a2_0_2, B => Psel14Mux_0_a2_0_1, C
|
| 6984 |
|
|
=> N_67, Y => Psel14Mux);
|
| 6985 |
|
|
|
| 6986 |
|
|
iHREADYOUT_RNIQN2S8 : NOR3B
|
| 6987 |
|
|
port map(A => un1_m5_0_a2_5_2, B => un1_N_5_mux, C =>
|
| 6988 |
|
|
\un1_m5_0_a2_a1\, Y => un1_m5_0_a2_1_0);
|
| 6989 |
|
|
|
| 6990 |
|
|
Psel15Mux_0_a2_2 : NOR2B
|
| 6991 |
|
|
port map(A => N_128_0, B => N_124_0, Y => N_116);
|
| 6992 |
|
|
|
| 6993 |
|
|
\PWDATA[2]\ : DFN1E1C0
|
| 6994 |
|
|
port map(D => CoreAHBLite_0_AHBmslave0_HWDATA(2), CLK =>
|
| 6995 |
|
|
HCLK_c, CLR => HRESETn_c, E => N_55, Q =>
|
| 6996 |
|
|
CoreAPB_0_APBmslave0_PWDATA(2));
|
| 6997 |
|
|
|
| 6998 |
|
|
Psel11Mux_0_a2_1 : NOR2A
|
| 6999 |
|
|
port map(A => N_128_0, B => N_124_0, Y => N_119);
|
| 7000 |
|
|
|
| 7001 |
|
|
\CurrentState_RNIJ4KGQ_1[4]\ : NOR3C
|
| 7002 |
|
|
port map(A => arbRegSMCurrentState_RNICAHF7_0, B =>
|
| 7003 |
|
|
Psel12Mux_0_a2_6_0, C => N_119, Y => Psel9Mux_0_a2_0_1);
|
| 7004 |
|
|
|
| 7005 |
|
|
iPSEL14 : DFN1E0C0
|
| 7006 |
|
|
port map(D => Psel14Mux, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 7007 |
|
|
=> \NextState[2]\, Q =>
|
| 7008 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(14));
|
| 7009 |
|
|
|
| 7010 |
|
|
\CurrentState_RNO[7]\ : NOR2
|
| 7011 |
|
|
port map(A => N_520, B => \iHREADYOUT_RNIAOEJP1\, Y =>
|
| 7012 |
|
|
N_104);
|
| 7013 |
|
|
|
| 7014 |
|
|
iPSEL7 : DFN1E0C0
|
| 7015 |
|
|
port map(D => Psel7Mux, CLK => HCLK_c, CLR => HRESETn_c, E
|
| 7016 |
|
|
=> \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(7));
|
| 7017 |
|
|
|
| 7018 |
|
|
\PWDATA[3]\ : DFN1E1C0
|
| 7019 |
|
|
port map(D => CoreAHBLite_0_AHBmslave0_HWDATA(3), CLK =>
|
| 7020 |
|
|
HCLK_c, CLR => HRESETn_c, E => N_55, Q =>
|
| 7021 |
|
|
CoreAPB_0_APBmslave0_PWDATA(3));
|
| 7022 |
|
|
|
| 7023 |
|
|
iHREADYOUT_RNIAOEJP1 : NOR2B
|
| 7024 |
|
|
port map(A => un4_valid_2, B => \un4_valid_4\, Y =>
|
| 7025 |
|
|
\iHREADYOUT_RNIAOEJP1\);
|
| 7026 |
|
|
|
| 7027 |
|
|
\CurrentState_RNIP7C6[4]\ : NOR2
|
| 7028 |
|
|
port map(A => N_34, B => \NextState[2]\, Y =>
|
| 7029 |
|
|
Psel12Mux_0_a2_6_0);
|
| 7030 |
|
|
|
| 7031 |
|
|
un1_N_11_mux_i_a1 : NOR3C
|
| 7032 |
|
|
port map(A => N_392, B => N_265, C => HTRANS_0_a3_i_a2_3_0,
|
| 7033 |
|
|
Y => N_366);
|
| 7034 |
|
|
|
| 7035 |
|
|
un4_valid_4_1 : NOR3A
|
| 7036 |
|
|
port map(A => N_254, B => N_365, C => N_366, Y =>
|
| 7037 |
|
|
\un4_valid_4_1\);
|
| 7038 |
|
|
|
| 7039 |
|
|
iPSEL15_RNO_0 : NOR3C
|
| 7040 |
|
|
port map(A => \un4_valid_4\, B => masterAddrInProg_i_1_0, C
|
| 7041 |
|
|
=> Psel15Mux_0_a2_0_2, Y => Psel15Mux_0_a2_0_4);
|
| 7042 |
|
|
|
| 7043 |
|
|
|
| 7044 |
|
|
end DEF_ARCH;
|
| 7045 |
|
|
|
| 7046 |
|
|
library ieee;
|
| 7047 |
|
|
use ieee.std_logic_1164.all;
|
| 7048 |
|
|
library proasic3;
|
| 7049 |
|
|
use proasic3.all;
|
| 7050 |
|
|
|
| 7051 |
|
|
entity top is
|
| 7052 |
|
|
|
| 7053 |
|
|
port( ADDR : in std_logic_vector(31 downto 0);
|
| 7054 |
|
|
DATAIN : in std_logic_vector(31 downto 0);
|
| 7055 |
|
|
HCLK : in std_logic;
|
| 7056 |
|
|
HRESETn : in std_logic;
|
| 7057 |
|
|
LREAD : in std_logic;
|
| 7058 |
|
|
LWRITE : in std_logic;
|
| 7059 |
|
|
DATAOUT : out std_logic_vector(31 downto 0);
|
| 7060 |
|
|
RESP_err : out std_logic_vector(1 downto 0);
|
| 7061 |
|
|
TX : out std_logic;
|
| 7062 |
|
|
ahb_busy : out std_logic
|
| 7063 |
|
|
);
|
| 7064 |
|
|
|
| 7065 |
|
|
end top;
|
| 7066 |
|
|
|
| 7067 |
|
|
architecture DEF_ARCH of top is
|
| 7068 |
|
|
|
| 7069 |
|
|
component OUTBUF
|
| 7070 |
|
|
port( D : in std_logic := 'U';
|
| 7071 |
|
|
PAD : out std_logic
|
| 7072 |
|
|
);
|
| 7073 |
|
|
end component;
|
| 7074 |
|
|
|
| 7075 |
|
|
component AHBMASTER_FIC
|
| 7076 |
|
|
port( AHBMASTER_FIC_0_AHBmaster_HADDR_0 : out std_logic;
|
| 7077 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_1 : out std_logic;
|
| 7078 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_2 : out std_logic;
|
| 7079 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_22 : out std_logic;
|
| 7080 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_23 : out std_logic;
|
| 7081 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_24 : out std_logic;
|
| 7082 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_25 : out std_logic;
|
| 7083 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_26 : out std_logic;
|
| 7084 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_27 : out std_logic;
|
| 7085 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_28 : out std_logic;
|
| 7086 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_29 : out std_logic;
|
| 7087 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA : in std_logic_vector(7 downto 0) := (others => 'U');
|
| 7088 |
|
|
DATAOUT_c : out std_logic_vector(7 downto 0);
|
| 7089 |
|
|
DATAIN_c : in std_logic_vector(7 downto 0) := (others => 'U');
|
| 7090 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA : out std_logic_vector(7 downto 0);
|
| 7091 |
|
|
AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : out std_logic;
|
| 7092 |
|
|
ADDR_c_29 : in std_logic := 'U';
|
| 7093 |
|
|
ADDR_c_23 : in std_logic := 'U';
|
| 7094 |
|
|
ADDR_c_26 : in std_logic := 'U';
|
| 7095 |
|
|
ADDR_c_22 : in std_logic := 'U';
|
| 7096 |
|
|
ADDR_c_24 : in std_logic := 'U';
|
| 7097 |
|
|
ADDR_c_25 : in std_logic := 'U';
|
| 7098 |
|
|
ADDR_c_27 : in std_logic := 'U';
|
| 7099 |
|
|
ADDR_c_1 : in std_logic := 'U';
|
| 7100 |
|
|
ADDR_c_0 : in std_logic := 'U';
|
| 7101 |
|
|
ADDR_c_28 : in std_logic := 'U';
|
| 7102 |
|
|
ADDR_c_2 : in std_logic := 'U';
|
| 7103 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWRITE : out std_logic;
|
| 7104 |
|
|
HCLK_c : in std_logic := 'U';
|
| 7105 |
|
|
ahb_busy_c : out std_logic;
|
| 7106 |
|
|
HRESETn_c : in std_logic := 'U';
|
| 7107 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_0 : in std_logic := 'U';
|
| 7108 |
|
|
N_163 : in std_logic := 'U';
|
| 7109 |
|
|
LWRITE_c : in std_logic := 'U';
|
| 7110 |
|
|
LREAD_c : in std_logic := 'U';
|
| 7111 |
|
|
N_398 : in std_logic := 'U';
|
| 7112 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_1 : in std_logic := 'U';
|
| 7113 |
|
|
N_340 : in std_logic := 'U'
|
| 7114 |
|
|
);
|
| 7115 |
|
|
end component;
|
| 7116 |
|
|
|
| 7117 |
|
|
component INBUF
|
| 7118 |
|
|
port( PAD : in std_logic := 'U';
|
| 7119 |
|
|
Y : out std_logic
|
| 7120 |
|
|
);
|
| 7121 |
|
|
end component;
|
| 7122 |
|
|
|
| 7123 |
|
|
component VCC
|
| 7124 |
|
|
port( Y : out std_logic
|
| 7125 |
|
|
);
|
| 7126 |
|
|
end component;
|
| 7127 |
|
|
|
| 7128 |
|
|
component COREAPB
|
| 7129 |
|
|
port( CoreAHB2APB_0_APBmaster_PSELx : in std_logic_vector(15 downto 1) := (others => 'U');
|
| 7130 |
|
|
PRDATA_0_sqmuxa_0_a2_13 : out std_logic;
|
| 7131 |
|
|
CoreAPB_0_APBmslave0_PSELx : in std_logic := 'U';
|
| 7132 |
|
|
PRDATA_0_sqmuxa_0_a2_12 : out std_logic
|
| 7133 |
|
|
);
|
| 7134 |
|
|
end component;
|
| 7135 |
|
|
|
| 7136 |
|
|
component CLKBUF
|
| 7137 |
|
|
port( PAD : in std_logic := 'U';
|
| 7138 |
|
|
Y : out std_logic
|
| 7139 |
|
|
);
|
| 7140 |
|
|
end component;
|
| 7141 |
|
|
|
| 7142 |
|
|
component top_CoreAHBLite_0_CoreAHBLite
|
| 7143 |
|
|
port( AHBMASTER_FIC_0_AHBmaster_HADDR_26 : in std_logic := 'U';
|
| 7144 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_27 : in std_logic := 'U';
|
| 7145 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_28 : in std_logic := 'U';
|
| 7146 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_29 : in std_logic := 'U';
|
| 7147 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_0 : in std_logic := 'U';
|
| 7148 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_1 : in std_logic := 'U';
|
| 7149 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_2 : in std_logic := 'U';
|
| 7150 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_22 : in std_logic := 'U';
|
| 7151 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_23 : in std_logic := 'U';
|
| 7152 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_24 : in std_logic := 'U';
|
| 7153 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_25 : in std_logic := 'U';
|
| 7154 |
|
|
masterAddrInProg_i_1_0 : out std_logic;
|
| 7155 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA : out std_logic_vector(7 downto 0);
|
| 7156 |
|
|
xhdl1222_0 : out std_logic;
|
| 7157 |
|
|
CoreAPB_0_APBmslave0_PRDATA : in std_logic_vector(7 downto 0) := (others => 'U');
|
| 7158 |
|
|
AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : in std_logic := 'U';
|
| 7159 |
|
|
arbRegSMCurrentState_RNICAHF7_0 : out std_logic;
|
| 7160 |
|
|
arbRegSMCurrentState_i_0_3 : out std_logic;
|
| 7161 |
|
|
arbRegSMCurrentState_i_0_0 : out std_logic;
|
| 7162 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA : in std_logic_vector(7 downto 0) := (others => 'U');
|
| 7163 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA : out std_logic_vector(7 downto 0);
|
| 7164 |
|
|
defSlaveSMCurrentState : out std_logic;
|
| 7165 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWRITE : in std_logic := 'U';
|
| 7166 |
|
|
HRESETn_c : in std_logic := 'U';
|
| 7167 |
|
|
HCLK_c : in std_logic := 'U';
|
| 7168 |
|
|
N_163 : out std_logic;
|
| 7169 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY : in std_logic := 'U';
|
| 7170 |
|
|
N_254 : out std_logic;
|
| 7171 |
|
|
N_395 : out std_logic;
|
| 7172 |
|
|
N_265 : out std_logic;
|
| 7173 |
|
|
N_339_c : out std_logic;
|
| 7174 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_0 : out std_logic;
|
| 7175 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_1 : out std_logic;
|
| 7176 |
|
|
N_392 : out std_logic;
|
| 7177 |
|
|
N_391 : out std_logic;
|
| 7178 |
|
|
PRDATA_0_sqmuxa_0_a2_13 : in std_logic := 'U';
|
| 7179 |
|
|
PRDATA_0_sqmuxa_0_a2_12 : in std_logic := 'U';
|
| 7180 |
|
|
N_327 : out std_logic;
|
| 7181 |
|
|
N_340 : out std_logic;
|
| 7182 |
|
|
N_330 : out std_logic;
|
| 7183 |
|
|
N_397 : out std_logic;
|
| 7184 |
|
|
N_398 : in std_logic := 'U';
|
| 7185 |
|
|
N_171 : out std_logic;
|
| 7186 |
|
|
N_263 : out std_logic;
|
| 7187 |
|
|
N_367 : out std_logic;
|
| 7188 |
|
|
un1_N_11_mux_i_5_a1_1 : in std_logic := 'U';
|
| 7189 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx : out std_logic;
|
| 7190 |
|
|
N_363 : out std_logic;
|
| 7191 |
|
|
HADDR_24_0_a3_i_out : out std_logic;
|
| 7192 |
|
|
un4_m5_0_a3_2 : in std_logic := 'U';
|
| 7193 |
|
|
N_128 : out std_logic;
|
| 7194 |
|
|
N_124 : out std_logic;
|
| 7195 |
|
|
N_120 : out std_logic;
|
| 7196 |
|
|
N_22 : out std_logic;
|
| 7197 |
|
|
N_20 : out std_logic;
|
| 7198 |
|
|
N_135 : out std_logic;
|
| 7199 |
|
|
N_18 : out std_logic;
|
| 7200 |
|
|
N_326 : out std_logic;
|
| 7201 |
|
|
N_323 : out std_logic;
|
| 7202 |
|
|
HTRANS_0_a3_i_a2_3_0 : out std_logic;
|
| 7203 |
|
|
HTRANS_0_a3_i_a2_4_0 : out std_logic;
|
| 7204 |
|
|
N_365 : out std_logic;
|
| 7205 |
|
|
N_364 : out std_logic;
|
| 7206 |
|
|
un1_m1_e_0_0 : in std_logic := 'U';
|
| 7207 |
|
|
un4_m5_0_a3_1 : in std_logic := 'U'
|
| 7208 |
|
|
);
|
| 7209 |
|
|
end component;
|
| 7210 |
|
|
|
| 7211 |
|
|
component GND
|
| 7212 |
|
|
port( Y : out std_logic
|
| 7213 |
|
|
);
|
| 7214 |
|
|
end component;
|
| 7215 |
|
|
|
| 7216 |
|
|
component top_CoreUARTapb_0_CoreUARTapb
|
| 7217 |
|
|
port( CoreAPB_0_APBmslave0_PRDATA : out std_logic_vector(7 downto 0);
|
| 7218 |
|
|
CoreAPB_0_APBmslave0_PWDATA : in std_logic_vector(7 downto 0) := (others => 'U');
|
| 7219 |
|
|
CoreAPB_0_APBmslave0_PADDR : in std_logic_vector(4 downto 2) := (others => 'U');
|
| 7220 |
|
|
TX_c : out std_logic;
|
| 7221 |
|
|
HRESETn_c : in std_logic := 'U';
|
| 7222 |
|
|
HCLK_c : in std_logic := 'U';
|
| 7223 |
|
|
CoreAPB_0_APBmslave0_PENABLE : in std_logic := 'U';
|
| 7224 |
|
|
CoreAPB_0_APBmslave0_PWRITE : in std_logic := 'U';
|
| 7225 |
|
|
CoreAPB_0_APBmslave0_PSELx : in std_logic := 'U'
|
| 7226 |
|
|
);
|
| 7227 |
|
|
end component;
|
| 7228 |
|
|
|
| 7229 |
|
|
component CoreAHB2APB
|
| 7230 |
|
|
port( CoreAHBLite_0_AHBmslave0_HWDATA : in std_logic_vector(7 downto 0) := (others => 'U');
|
| 7231 |
|
|
CoreAPB_0_APBmslave0_PWDATA : out std_logic_vector(7 downto 0);
|
| 7232 |
|
|
CoreAPB_0_APBmslave0_PADDR : out std_logic_vector(4 downto 2);
|
| 7233 |
|
|
CoreAHB2APB_0_APBmaster_PSELx : out std_logic_vector(15 downto 1);
|
| 7234 |
|
|
arbRegSMCurrentState_i_0_0 : in std_logic := 'U';
|
| 7235 |
|
|
arbRegSMCurrentState_i_0_3 : in std_logic := 'U';
|
| 7236 |
|
|
xhdl1222_0 : in std_logic := 'U';
|
| 7237 |
|
|
masterAddrInProg_i_1_0 : in std_logic := 'U';
|
| 7238 |
|
|
arbRegSMCurrentState_RNICAHF7_0 : in std_logic := 'U';
|
| 7239 |
|
|
CoreAPB_0_APBmslave0_PWRITE : out std_logic;
|
| 7240 |
|
|
CoreAPB_0_APBmslave0_PSELx : out std_logic;
|
| 7241 |
|
|
HRESETn_c : in std_logic := 'U';
|
| 7242 |
|
|
HCLK_c : in std_logic := 'U';
|
| 7243 |
|
|
CoreAPB_0_APBmslave0_PENABLE : out std_logic;
|
| 7244 |
|
|
N_124_0 : in std_logic := 'U';
|
| 7245 |
|
|
N_128_0 : in std_logic := 'U';
|
| 7246 |
|
|
N_22 : in std_logic := 'U';
|
| 7247 |
|
|
N_20 : in std_logic := 'U';
|
| 7248 |
|
|
N_18 : in std_logic := 'U';
|
| 7249 |
|
|
N_395 : in std_logic := 'U';
|
| 7250 |
|
|
N_363 : in std_logic := 'U';
|
| 7251 |
|
|
N_364 : in std_logic := 'U';
|
| 7252 |
|
|
HTRANS_0_a3_i_a2_3_0 : in std_logic := 'U';
|
| 7253 |
|
|
N_265 : in std_logic := 'U';
|
| 7254 |
|
|
N_392 : in std_logic := 'U';
|
| 7255 |
|
|
N_135 : in std_logic := 'U';
|
| 7256 |
|
|
N_367 : in std_logic := 'U';
|
| 7257 |
|
|
defSlaveSMCurrentState : in std_logic := 'U';
|
| 7258 |
|
|
N_391 : in std_logic := 'U';
|
| 7259 |
|
|
HTRANS_0_a3_i_a2_4_0 : in std_logic := 'U';
|
| 7260 |
|
|
N_398 : out std_logic;
|
| 7261 |
|
|
un1_N_11_mux_i_5_a1_1 : out std_logic;
|
| 7262 |
|
|
N_327 : in std_logic := 'U';
|
| 7263 |
|
|
un4_m5_0_a3_1 : out std_logic;
|
| 7264 |
|
|
un4_m5_0_a3_2 : out std_logic;
|
| 7265 |
|
|
N_171 : in std_logic := 'U';
|
| 7266 |
|
|
N_330 : in std_logic := 'U';
|
| 7267 |
|
|
N_397 : in std_logic := 'U';
|
| 7268 |
|
|
N_326 : in std_logic := 'U';
|
| 7269 |
|
|
un1_m1_e_0_0 : out std_logic;
|
| 7270 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY : out std_logic;
|
| 7271 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx : in std_logic := 'U';
|
| 7272 |
|
|
HADDR_24_0_a3_i_out : in std_logic := 'U';
|
| 7273 |
|
|
N_263 : in std_logic := 'U';
|
| 7274 |
|
|
N_323 : in std_logic := 'U';
|
| 7275 |
|
|
N_365 : in std_logic := 'U';
|
| 7276 |
|
|
N_254 : in std_logic := 'U';
|
| 7277 |
|
|
N_120 : in std_logic := 'U'
|
| 7278 |
|
|
);
|
| 7279 |
|
|
end component;
|
| 7280 |
|
|
|
| 7281 |
|
|
signal \AHBMASTER_FIC_0_AHBmaster_HADDR[2]\,
|
| 7282 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[3]\,
|
| 7283 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[4]\,
|
| 7284 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[24]\,
|
| 7285 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[25]\,
|
| 7286 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[26]\,
|
| 7287 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[27]\,
|
| 7288 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[28]\,
|
| 7289 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[29]\,
|
| 7290 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[30]\,
|
| 7291 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[31]\,
|
| 7292 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HTRANS[1]\,
|
| 7293 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWRITE,
|
| 7294 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[0]\,
|
| 7295 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[1]\,
|
| 7296 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[2]\,
|
| 7297 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[3]\,
|
| 7298 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[4]\,
|
| 7299 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[5]\,
|
| 7300 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[6]\,
|
| 7301 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[7]\,
|
| 7302 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY,
|
| 7303 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[0]\,
|
| 7304 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[1]\,
|
| 7305 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[2]\,
|
| 7306 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[3]\,
|
| 7307 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[4]\,
|
| 7308 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[5]\,
|
| 7309 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[6]\,
|
| 7310 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[7]\,
|
| 7311 |
|
|
CoreAPB_0_APBmslave0_PENABLE, CoreAPB_0_APBmslave0_PSELx,
|
| 7312 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[1]\,
|
| 7313 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[2]\,
|
| 7314 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[3]\,
|
| 7315 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[4]\,
|
| 7316 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[5]\,
|
| 7317 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[6]\,
|
| 7318 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[7]\,
|
| 7319 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[8]\,
|
| 7320 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[9]\,
|
| 7321 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[10]\,
|
| 7322 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[11]\,
|
| 7323 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[12]\,
|
| 7324 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[13]\,
|
| 7325 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[14]\,
|
| 7326 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[15]\,
|
| 7327 |
|
|
\CoreAPB_0_APBmslave0_PADDR[2]\,
|
| 7328 |
|
|
\CoreAPB_0_APBmslave0_PADDR[3]\,
|
| 7329 |
|
|
\CoreAPB_0_APBmslave0_PADDR[4]\,
|
| 7330 |
|
|
CoreAPB_0_APBmslave0_PWRITE, \VCC\,
|
| 7331 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[0]\,
|
| 7332 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[1]\,
|
| 7333 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[2]\,
|
| 7334 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[3]\,
|
| 7335 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[4]\,
|
| 7336 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[5]\,
|
| 7337 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[6]\,
|
| 7338 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[7]\,
|
| 7339 |
|
|
\CoreAHBLite_0.matrix4x16.xhdl1222[0]\,
|
| 7340 |
|
|
\CoreAHBLite_0.matrix4x16.masterstage_0.default_slave_sm.defSlaveSMCurrentState\,
|
| 7341 |
|
|
N_120, N_124, N_128, N_135, N_163, N_254, N_263, N_265,
|
| 7342 |
|
|
N_340, N_363, N_364, N_365, N_367, N_397, \ADDR_c[2]\,
|
| 7343 |
|
|
\ADDR_c[3]\, \ADDR_c[4]\, \ADDR_c[24]\, \ADDR_c[25]\,
|
| 7344 |
|
|
\ADDR_c[26]\, \ADDR_c[27]\, \ADDR_c[28]\, \ADDR_c[29]\,
|
| 7345 |
|
|
\ADDR_c[30]\, \ADDR_c[31]\, \DATAIN_c[0]\, \DATAIN_c[1]\,
|
| 7346 |
|
|
\DATAIN_c[2]\, \DATAIN_c[3]\, \DATAIN_c[4]\,
|
| 7347 |
|
|
\DATAIN_c[5]\, \DATAIN_c[6]\, \DATAIN_c[7]\, HCLK_c,
|
| 7348 |
|
|
HRESETn_c, LREAD_c, LWRITE_c, \DATAOUT_c[0]\,
|
| 7349 |
|
|
\DATAOUT_c[1]\, \DATAOUT_c[2]\, \DATAOUT_c[3]\,
|
| 7350 |
|
|
\DATAOUT_c[4]\, \DATAOUT_c[5]\, \DATAOUT_c[6]\,
|
| 7351 |
|
|
\DATAOUT_c[7]\, N_339_c, \GND\, TX_c, ahb_busy_c, N_22,
|
| 7352 |
|
|
N_20, N_18,
|
| 7353 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.masterAddrInProg_i_1[0]\,
|
| 7354 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx, N_391, N_326,
|
| 7355 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[7]\,
|
| 7356 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[6]\,
|
| 7357 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[5]\,
|
| 7358 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[4]\,
|
| 7359 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[3]\,
|
| 7360 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[2]\,
|
| 7361 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[1]\,
|
| 7362 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[0]\, N_327, N_330, N_323,
|
| 7363 |
|
|
N_395, N_392,
|
| 7364 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.N_171\,
|
| 7365 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[7]\,
|
| 7366 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[6]\,
|
| 7367 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[5]\,
|
| 7368 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[4]\,
|
| 7369 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[3]\,
|
| 7370 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[2]\,
|
| 7371 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[1]\,
|
| 7372 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[0]\,
|
| 7373 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.HTRANS_0_a3_i_a2_3_0\,
|
| 7374 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.HTRANS_0_a3_i_a2_4_0\,
|
| 7375 |
|
|
\CoreAHBLite_0.matrix4x16.masterstage_0.PREVDATASLAVEREADY_iv_i_0_i_o4_0\,
|
| 7376 |
|
|
\CoreAHBLite_0.matrix4x16.masterstage_0.PREVDATASLAVEREADY_iv_i_0_i_o4_1\,
|
| 7377 |
|
|
\CoreAHB2APB_0.un1_m1_e_0_0\,
|
| 7378 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.HADDR_24_0_a3_i_out\,
|
| 7379 |
|
|
\arbRegSMCurrentState_RNICAHF7[0]\,
|
| 7380 |
|
|
\CoreAPB_0.COREAPB_oi0.PRDATA_0_sqmuxa_0_a2_12\,
|
| 7381 |
|
|
\CoreAPB_0.COREAPB_oi0.PRDATA_0_sqmuxa_0_a2_13\, N_398,
|
| 7382 |
|
|
\CoreAHB2APB_0.un1_N_11_mux_i_5_a1_1\,
|
| 7383 |
|
|
\CoreAHB2APB_0.un4_m5_0_a3_1\,
|
| 7384 |
|
|
\CoreAHB2APB_0.un4_m5_0_a3_2\,
|
| 7385 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_i_0[12]\,
|
| 7386 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_i_0[15]\
|
| 7387 |
|
|
: std_logic;
|
| 7388 |
|
|
|
| 7389 |
|
|
for all : AHBMASTER_FIC
|
| 7390 |
|
|
Use entity work.AHBMASTER_FIC(DEF_ARCH);
|
| 7391 |
|
|
for all : COREAPB
|
| 7392 |
|
|
Use entity work.COREAPB(DEF_ARCH);
|
| 7393 |
|
|
for all : top_CoreAHBLite_0_CoreAHBLite
|
| 7394 |
|
|
Use entity work.top_CoreAHBLite_0_CoreAHBLite(DEF_ARCH);
|
| 7395 |
|
|
for all : top_CoreUARTapb_0_CoreUARTapb
|
| 7396 |
|
|
Use entity work.top_CoreUARTapb_0_CoreUARTapb(DEF_ARCH);
|
| 7397 |
|
|
for all : CoreAHB2APB
|
| 7398 |
|
|
Use entity work.CoreAHB2APB(DEF_ARCH);
|
| 7399 |
|
|
begin
|
| 7400 |
|
|
|
| 7401 |
|
|
|
| 7402 |
|
|
\DATAOUT_pad[16]\ : OUTBUF
|
| 7403 |
|
|
port map(D => \GND\, PAD => DATAOUT(16));
|
| 7404 |
|
|
|
| 7405 |
|
|
AHBMASTER_FIC_0 : AHBMASTER_FIC
|
| 7406 |
|
|
port map(AHBMASTER_FIC_0_AHBmaster_HADDR_0 =>
|
| 7407 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[2]\,
|
| 7408 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_1 =>
|
| 7409 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[3]\,
|
| 7410 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_2 =>
|
| 7411 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[4]\,
|
| 7412 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_22 =>
|
| 7413 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[24]\,
|
| 7414 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_23 =>
|
| 7415 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[25]\,
|
| 7416 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_24 =>
|
| 7417 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[26]\,
|
| 7418 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_25 =>
|
| 7419 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[27]\,
|
| 7420 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_26 =>
|
| 7421 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[28]\,
|
| 7422 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_27 =>
|
| 7423 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[29]\,
|
| 7424 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_28 =>
|
| 7425 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[30]\,
|
| 7426 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_29 =>
|
| 7427 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[31]\,
|
| 7428 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(7) =>
|
| 7429 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[7]\,
|
| 7430 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(6) =>
|
| 7431 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[6]\,
|
| 7432 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(5) =>
|
| 7433 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[5]\,
|
| 7434 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(4) =>
|
| 7435 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[4]\,
|
| 7436 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(3) =>
|
| 7437 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[3]\,
|
| 7438 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(2) =>
|
| 7439 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[2]\,
|
| 7440 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(1) =>
|
| 7441 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[1]\,
|
| 7442 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(0) =>
|
| 7443 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[0]\, DATAOUT_c(7) =>
|
| 7444 |
|
|
\DATAOUT_c[7]\, DATAOUT_c(6) => \DATAOUT_c[6]\,
|
| 7445 |
|
|
DATAOUT_c(5) => \DATAOUT_c[5]\, DATAOUT_c(4) =>
|
| 7446 |
|
|
\DATAOUT_c[4]\, DATAOUT_c(3) => \DATAOUT_c[3]\,
|
| 7447 |
|
|
DATAOUT_c(2) => \DATAOUT_c[2]\, DATAOUT_c(1) =>
|
| 7448 |
|
|
\DATAOUT_c[1]\, DATAOUT_c(0) => \DATAOUT_c[0]\,
|
| 7449 |
|
|
DATAIN_c(7) => \DATAIN_c[7]\, DATAIN_c(6) =>
|
| 7450 |
|
|
\DATAIN_c[6]\, DATAIN_c(5) => \DATAIN_c[5]\, DATAIN_c(4)
|
| 7451 |
|
|
=> \DATAIN_c[4]\, DATAIN_c(3) => \DATAIN_c[3]\,
|
| 7452 |
|
|
DATAIN_c(2) => \DATAIN_c[2]\, DATAIN_c(1) =>
|
| 7453 |
|
|
\DATAIN_c[1]\, DATAIN_c(0) => \DATAIN_c[0]\,
|
| 7454 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(7) =>
|
| 7455 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[7]\,
|
| 7456 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(6) =>
|
| 7457 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[6]\,
|
| 7458 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(5) =>
|
| 7459 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[5]\,
|
| 7460 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(4) =>
|
| 7461 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[4]\,
|
| 7462 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(3) =>
|
| 7463 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[3]\,
|
| 7464 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(2) =>
|
| 7465 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[2]\,
|
| 7466 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(1) =>
|
| 7467 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[1]\,
|
| 7468 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(0) =>
|
| 7469 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[0]\,
|
| 7470 |
|
|
AHBMASTER_FIC_0_AHBmaster_HTRANS_0 =>
|
| 7471 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HTRANS[1]\, ADDR_c_29 =>
|
| 7472 |
|
|
\ADDR_c[31]\, ADDR_c_23 => \ADDR_c[25]\, ADDR_c_26 =>
|
| 7473 |
|
|
\ADDR_c[28]\, ADDR_c_22 => \ADDR_c[24]\, ADDR_c_24 =>
|
| 7474 |
|
|
\ADDR_c[26]\, ADDR_c_25 => \ADDR_c[27]\, ADDR_c_27 =>
|
| 7475 |
|
|
\ADDR_c[29]\, ADDR_c_1 => \ADDR_c[3]\, ADDR_c_0 =>
|
| 7476 |
|
|
\ADDR_c[2]\, ADDR_c_28 => \ADDR_c[30]\, ADDR_c_2 =>
|
| 7477 |
|
|
\ADDR_c[4]\, AHBMASTER_FIC_0_AHBmaster_HWRITE =>
|
| 7478 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWRITE, HCLK_c => HCLK_c,
|
| 7479 |
|
|
ahb_busy_c => ahb_busy_c, HRESETn_c => HRESETn_c,
|
| 7480 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_0 =>
|
| 7481 |
|
|
\CoreAHBLite_0.matrix4x16.masterstage_0.PREVDATASLAVEREADY_iv_i_0_i_o4_0\,
|
| 7482 |
|
|
N_163 => N_163, LWRITE_c => LWRITE_c, LREAD_c => LREAD_c,
|
| 7483 |
|
|
N_398 => N_398, PREVDATASLAVEREADY_iv_i_0_i_o4_1 =>
|
| 7484 |
|
|
\CoreAHBLite_0.matrix4x16.masterstage_0.PREVDATASLAVEREADY_iv_i_0_i_o4_1\,
|
| 7485 |
|
|
N_340 => N_340);
|
| 7486 |
|
|
|
| 7487 |
|
|
\DATAOUT_pad[25]\ : OUTBUF
|
| 7488 |
|
|
port map(D => \GND\, PAD => DATAOUT(25));
|
| 7489 |
|
|
|
| 7490 |
|
|
\DATAIN_pad[4]\ : INBUF
|
| 7491 |
|
|
port map(PAD => DATAIN(4), Y => \DATAIN_c[4]\);
|
| 7492 |
|
|
|
| 7493 |
|
|
\DATAIN_pad[5]\ : INBUF
|
| 7494 |
|
|
port map(PAD => DATAIN(5), Y => \DATAIN_c[5]\);
|
| 7495 |
|
|
|
| 7496 |
|
|
\DATAIN_pad[7]\ : INBUF
|
| 7497 |
|
|
port map(PAD => DATAIN(7), Y => \DATAIN_c[7]\);
|
| 7498 |
|
|
|
| 7499 |
|
|
\DATAOUT_pad[2]\ : OUTBUF
|
| 7500 |
|
|
port map(D => \DATAOUT_c[2]\, PAD => DATAOUT(2));
|
| 7501 |
|
|
|
| 7502 |
|
|
\DATAIN_pad[2]\ : INBUF
|
| 7503 |
|
|
port map(PAD => DATAIN(2), Y => \DATAIN_c[2]\);
|
| 7504 |
|
|
|
| 7505 |
|
|
\ADDR_pad[28]\ : INBUF
|
| 7506 |
|
|
port map(PAD => ADDR(28), Y => \ADDR_c[28]\);
|
| 7507 |
|
|
|
| 7508 |
|
|
\DATAOUT_pad[27]\ : OUTBUF
|
| 7509 |
|
|
port map(D => \GND\, PAD => DATAOUT(27));
|
| 7510 |
|
|
|
| 7511 |
|
|
\DATAOUT_pad[18]\ : OUTBUF
|
| 7512 |
|
|
port map(D => \GND\, PAD => DATAOUT(18));
|
| 7513 |
|
|
|
| 7514 |
|
|
\DATAOUT_pad[0]\ : OUTBUF
|
| 7515 |
|
|
port map(D => \DATAOUT_c[0]\, PAD => DATAOUT(0));
|
| 7516 |
|
|
|
| 7517 |
|
|
VCC_i : VCC
|
| 7518 |
|
|
port map(Y => \VCC\);
|
| 7519 |
|
|
|
| 7520 |
|
|
CoreAPB_0 : COREAPB
|
| 7521 |
|
|
port map(CoreAHB2APB_0_APBmaster_PSELx(15) =>
|
| 7522 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[15]\,
|
| 7523 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(14) =>
|
| 7524 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[14]\,
|
| 7525 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(13) =>
|
| 7526 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[13]\,
|
| 7527 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(12) =>
|
| 7528 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[12]\,
|
| 7529 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(11) =>
|
| 7530 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[11]\,
|
| 7531 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(10) =>
|
| 7532 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[10]\,
|
| 7533 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(9) =>
|
| 7534 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[9]\,
|
| 7535 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(8) =>
|
| 7536 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[8]\,
|
| 7537 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(7) =>
|
| 7538 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[7]\,
|
| 7539 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(6) =>
|
| 7540 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[6]\,
|
| 7541 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(5) =>
|
| 7542 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[5]\,
|
| 7543 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(4) =>
|
| 7544 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[4]\,
|
| 7545 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(3) =>
|
| 7546 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[3]\,
|
| 7547 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(2) =>
|
| 7548 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[2]\,
|
| 7549 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(1) =>
|
| 7550 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[1]\,
|
| 7551 |
|
|
PRDATA_0_sqmuxa_0_a2_13 =>
|
| 7552 |
|
|
\CoreAPB_0.COREAPB_oi0.PRDATA_0_sqmuxa_0_a2_13\,
|
| 7553 |
|
|
CoreAPB_0_APBmslave0_PSELx => CoreAPB_0_APBmslave0_PSELx,
|
| 7554 |
|
|
PRDATA_0_sqmuxa_0_a2_12 =>
|
| 7555 |
|
|
\CoreAPB_0.COREAPB_oi0.PRDATA_0_sqmuxa_0_a2_12\);
|
| 7556 |
|
|
|
| 7557 |
|
|
\DATAOUT_pad[12]\ : OUTBUF
|
| 7558 |
|
|
port map(D => \GND\, PAD => DATAOUT(12));
|
| 7559 |
|
|
|
| 7560 |
|
|
\ADDR_pad[2]\ : INBUF
|
| 7561 |
|
|
port map(PAD => ADDR(2), Y => \ADDR_c[2]\);
|
| 7562 |
|
|
|
| 7563 |
|
|
HCLK_pad : CLKBUF
|
| 7564 |
|
|
port map(PAD => HCLK, Y => HCLK_c);
|
| 7565 |
|
|
|
| 7566 |
|
|
TX_pad : OUTBUF
|
| 7567 |
|
|
port map(D => TX_c, PAD => TX);
|
| 7568 |
|
|
|
| 7569 |
|
|
\RESP_err_pad[0]\ : OUTBUF
|
| 7570 |
|
|
port map(D => N_339_c, PAD => RESP_err(0));
|
| 7571 |
|
|
|
| 7572 |
|
|
\DATAOUT_pad[8]\ : OUTBUF
|
| 7573 |
|
|
port map(D => \GND\, PAD => DATAOUT(8));
|
| 7574 |
|
|
|
| 7575 |
|
|
\DATAOUT_pad[13]\ : OUTBUF
|
| 7576 |
|
|
port map(D => \GND\, PAD => DATAOUT(13));
|
| 7577 |
|
|
|
| 7578 |
|
|
\DATAIN_pad[0]\ : INBUF
|
| 7579 |
|
|
port map(PAD => DATAIN(0), Y => \DATAIN_c[0]\);
|
| 7580 |
|
|
|
| 7581 |
|
|
CoreAHBLite_0 : top_CoreAHBLite_0_CoreAHBLite
|
| 7582 |
|
|
port map(AHBMASTER_FIC_0_AHBmaster_HADDR_26 =>
|
| 7583 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[28]\,
|
| 7584 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_27 =>
|
| 7585 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[29]\,
|
| 7586 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_28 =>
|
| 7587 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[30]\,
|
| 7588 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_29 =>
|
| 7589 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[31]\,
|
| 7590 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_0 =>
|
| 7591 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[2]\,
|
| 7592 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_1 =>
|
| 7593 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[3]\,
|
| 7594 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_2 =>
|
| 7595 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[4]\,
|
| 7596 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_22 =>
|
| 7597 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[24]\,
|
| 7598 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_23 =>
|
| 7599 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[25]\,
|
| 7600 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_24 =>
|
| 7601 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[26]\,
|
| 7602 |
|
|
AHBMASTER_FIC_0_AHBmaster_HADDR_25 =>
|
| 7603 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HADDR[27]\,
|
| 7604 |
|
|
masterAddrInProg_i_1_0 =>
|
| 7605 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.masterAddrInProg_i_1[0]\,
|
| 7606 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(7) =>
|
| 7607 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[7]\,
|
| 7608 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(6) =>
|
| 7609 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[6]\,
|
| 7610 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(5) =>
|
| 7611 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[5]\,
|
| 7612 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(4) =>
|
| 7613 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[4]\,
|
| 7614 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(3) =>
|
| 7615 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[3]\,
|
| 7616 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(2) =>
|
| 7617 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[2]\,
|
| 7618 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(1) =>
|
| 7619 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[1]\,
|
| 7620 |
|
|
AHBMASTER_FIC_0_AHBmaster_HRDATA(0) =>
|
| 7621 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HRDATA[0]\, xhdl1222_0 =>
|
| 7622 |
|
|
\CoreAHBLite_0.matrix4x16.xhdl1222[0]\,
|
| 7623 |
|
|
CoreAPB_0_APBmslave0_PRDATA(7) =>
|
| 7624 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[7]\,
|
| 7625 |
|
|
CoreAPB_0_APBmslave0_PRDATA(6) =>
|
| 7626 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[6]\,
|
| 7627 |
|
|
CoreAPB_0_APBmslave0_PRDATA(5) =>
|
| 7628 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[5]\,
|
| 7629 |
|
|
CoreAPB_0_APBmslave0_PRDATA(4) =>
|
| 7630 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[4]\,
|
| 7631 |
|
|
CoreAPB_0_APBmslave0_PRDATA(3) =>
|
| 7632 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[3]\,
|
| 7633 |
|
|
CoreAPB_0_APBmslave0_PRDATA(2) =>
|
| 7634 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[2]\,
|
| 7635 |
|
|
CoreAPB_0_APBmslave0_PRDATA(1) =>
|
| 7636 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[1]\,
|
| 7637 |
|
|
CoreAPB_0_APBmslave0_PRDATA(0) =>
|
| 7638 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[0]\,
|
| 7639 |
|
|
AHBMASTER_FIC_0_AHBmaster_HTRANS_0 =>
|
| 7640 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HTRANS[1]\,
|
| 7641 |
|
|
arbRegSMCurrentState_RNICAHF7_0 =>
|
| 7642 |
|
|
\arbRegSMCurrentState_RNICAHF7[0]\,
|
| 7643 |
|
|
arbRegSMCurrentState_i_0_3 =>
|
| 7644 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_i_0[15]\,
|
| 7645 |
|
|
arbRegSMCurrentState_i_0_0 =>
|
| 7646 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_i_0[12]\,
|
| 7647 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(7) =>
|
| 7648 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[7]\,
|
| 7649 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(6) =>
|
| 7650 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[6]\,
|
| 7651 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(5) =>
|
| 7652 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[5]\,
|
| 7653 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(4) =>
|
| 7654 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[4]\,
|
| 7655 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(3) =>
|
| 7656 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[3]\,
|
| 7657 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(2) =>
|
| 7658 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[2]\,
|
| 7659 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(1) =>
|
| 7660 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[1]\,
|
| 7661 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWDATA(0) =>
|
| 7662 |
|
|
\AHBMASTER_FIC_0_AHBmaster_HWDATA[0]\,
|
| 7663 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(7) =>
|
| 7664 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[7]\,
|
| 7665 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(6) =>
|
| 7666 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[6]\,
|
| 7667 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(5) =>
|
| 7668 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[5]\,
|
| 7669 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(4) =>
|
| 7670 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[4]\,
|
| 7671 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(3) =>
|
| 7672 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[3]\,
|
| 7673 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(2) =>
|
| 7674 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[2]\,
|
| 7675 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(1) =>
|
| 7676 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[1]\,
|
| 7677 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(0) =>
|
| 7678 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[0]\,
|
| 7679 |
|
|
defSlaveSMCurrentState =>
|
| 7680 |
|
|
\CoreAHBLite_0.matrix4x16.masterstage_0.default_slave_sm.defSlaveSMCurrentState\,
|
| 7681 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWRITE =>
|
| 7682 |
|
|
AHBMASTER_FIC_0_AHBmaster_HWRITE, HRESETn_c => HRESETn_c,
|
| 7683 |
|
|
HCLK_c => HCLK_c, N_163 => N_163,
|
| 7684 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY =>
|
| 7685 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY, N_254 => N_254, N_395
|
| 7686 |
|
|
=> N_395, N_265 => N_265, N_339_c => N_339_c,
|
| 7687 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_0 =>
|
| 7688 |
|
|
\CoreAHBLite_0.matrix4x16.masterstage_0.PREVDATASLAVEREADY_iv_i_0_i_o4_0\,
|
| 7689 |
|
|
PREVDATASLAVEREADY_iv_i_0_i_o4_1 =>
|
| 7690 |
|
|
\CoreAHBLite_0.matrix4x16.masterstage_0.PREVDATASLAVEREADY_iv_i_0_i_o4_1\,
|
| 7691 |
|
|
N_392 => N_392, N_391 => N_391, PRDATA_0_sqmuxa_0_a2_13
|
| 7692 |
|
|
=> \CoreAPB_0.COREAPB_oi0.PRDATA_0_sqmuxa_0_a2_13\,
|
| 7693 |
|
|
PRDATA_0_sqmuxa_0_a2_12 =>
|
| 7694 |
|
|
\CoreAPB_0.COREAPB_oi0.PRDATA_0_sqmuxa_0_a2_12\, N_327
|
| 7695 |
|
|
=> N_327, N_340 => N_340, N_330 => N_330, N_397 => N_397,
|
| 7696 |
|
|
N_398 => N_398, N_171 =>
|
| 7697 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.N_171\,
|
| 7698 |
|
|
N_263 => N_263, N_367 => N_367, un1_N_11_mux_i_5_a1_1 =>
|
| 7699 |
|
|
\CoreAHB2APB_0.un1_N_11_mux_i_5_a1_1\,
|
| 7700 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx =>
|
| 7701 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx, N_363 => N_363,
|
| 7702 |
|
|
HADDR_24_0_a3_i_out =>
|
| 7703 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.HADDR_24_0_a3_i_out\,
|
| 7704 |
|
|
un4_m5_0_a3_2 => \CoreAHB2APB_0.un4_m5_0_a3_2\, N_128 =>
|
| 7705 |
|
|
N_128, N_124 => N_124, N_120 => N_120, N_22 => N_22, N_20
|
| 7706 |
|
|
=> N_20, N_135 => N_135, N_18 => N_18, N_326 => N_326,
|
| 7707 |
|
|
N_323 => N_323, HTRANS_0_a3_i_a2_3_0 =>
|
| 7708 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.HTRANS_0_a3_i_a2_3_0\,
|
| 7709 |
|
|
HTRANS_0_a3_i_a2_4_0 =>
|
| 7710 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.HTRANS_0_a3_i_a2_4_0\,
|
| 7711 |
|
|
N_365 => N_365, N_364 => N_364, un1_m1_e_0_0 =>
|
| 7712 |
|
|
\CoreAHB2APB_0.un1_m1_e_0_0\, un4_m5_0_a3_1 =>
|
| 7713 |
|
|
\CoreAHB2APB_0.un4_m5_0_a3_1\);
|
| 7714 |
|
|
|
| 7715 |
|
|
\ADDR_pad[3]\ : INBUF
|
| 7716 |
|
|
port map(PAD => ADDR(3), Y => \ADDR_c[3]\);
|
| 7717 |
|
|
|
| 7718 |
|
|
\DATAOUT_pad[7]\ : OUTBUF
|
| 7719 |
|
|
port map(D => \DATAOUT_c[7]\, PAD => DATAOUT(7));
|
| 7720 |
|
|
|
| 7721 |
|
|
\DATAOUT_pad[1]\ : OUTBUF
|
| 7722 |
|
|
port map(D => \DATAOUT_c[1]\, PAD => DATAOUT(1));
|
| 7723 |
|
|
|
| 7724 |
|
|
\DATAOUT_pad[15]\ : OUTBUF
|
| 7725 |
|
|
port map(D => \GND\, PAD => DATAOUT(15));
|
| 7726 |
|
|
|
| 7727 |
|
|
\DATAOUT_pad[21]\ : OUTBUF
|
| 7728 |
|
|
port map(D => \GND\, PAD => DATAOUT(21));
|
| 7729 |
|
|
|
| 7730 |
|
|
\DATAOUT_pad[20]\ : OUTBUF
|
| 7731 |
|
|
port map(D => \GND\, PAD => DATAOUT(20));
|
| 7732 |
|
|
|
| 7733 |
|
|
GND_i : GND
|
| 7734 |
|
|
port map(Y => \GND\);
|
| 7735 |
|
|
|
| 7736 |
|
|
\DATAOUT_pad[29]\ : OUTBUF
|
| 7737 |
|
|
port map(D => \GND\, PAD => DATAOUT(29));
|
| 7738 |
|
|
|
| 7739 |
|
|
\DATAOUT_pad[24]\ : OUTBUF
|
| 7740 |
|
|
port map(D => \GND\, PAD => DATAOUT(24));
|
| 7741 |
|
|
|
| 7742 |
|
|
\DATAIN_pad[1]\ : INBUF
|
| 7743 |
|
|
port map(PAD => DATAIN(1), Y => \DATAIN_c[1]\);
|
| 7744 |
|
|
|
| 7745 |
|
|
\DATAOUT_pad[26]\ : OUTBUF
|
| 7746 |
|
|
port map(D => \GND\, PAD => DATAOUT(26));
|
| 7747 |
|
|
|
| 7748 |
|
|
\DATAOUT_pad[17]\ : OUTBUF
|
| 7749 |
|
|
port map(D => \GND\, PAD => DATAOUT(17));
|
| 7750 |
|
|
|
| 7751 |
|
|
\ADDR_pad[26]\ : INBUF
|
| 7752 |
|
|
port map(PAD => ADDR(26), Y => \ADDR_c[26]\);
|
| 7753 |
|
|
|
| 7754 |
|
|
\ADDR_pad[4]\ : INBUF
|
| 7755 |
|
|
port map(PAD => ADDR(4), Y => \ADDR_c[4]\);
|
| 7756 |
|
|
|
| 7757 |
|
|
LREAD_pad : INBUF
|
| 7758 |
|
|
port map(PAD => LREAD, Y => LREAD_c);
|
| 7759 |
|
|
|
| 7760 |
|
|
CoreUARTapb_0 : top_CoreUARTapb_0_CoreUARTapb
|
| 7761 |
|
|
port map(CoreAPB_0_APBmslave0_PRDATA(7) =>
|
| 7762 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[7]\,
|
| 7763 |
|
|
CoreAPB_0_APBmslave0_PRDATA(6) =>
|
| 7764 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[6]\,
|
| 7765 |
|
|
CoreAPB_0_APBmslave0_PRDATA(5) =>
|
| 7766 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[5]\,
|
| 7767 |
|
|
CoreAPB_0_APBmslave0_PRDATA(4) =>
|
| 7768 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[4]\,
|
| 7769 |
|
|
CoreAPB_0_APBmslave0_PRDATA(3) =>
|
| 7770 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[3]\,
|
| 7771 |
|
|
CoreAPB_0_APBmslave0_PRDATA(2) =>
|
| 7772 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[2]\,
|
| 7773 |
|
|
CoreAPB_0_APBmslave0_PRDATA(1) =>
|
| 7774 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[1]\,
|
| 7775 |
|
|
CoreAPB_0_APBmslave0_PRDATA(0) =>
|
| 7776 |
|
|
\CoreAPB_0_APBmslave0_PRDATA[0]\,
|
| 7777 |
|
|
CoreAPB_0_APBmslave0_PWDATA(7) =>
|
| 7778 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[7]\,
|
| 7779 |
|
|
CoreAPB_0_APBmslave0_PWDATA(6) =>
|
| 7780 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[6]\,
|
| 7781 |
|
|
CoreAPB_0_APBmslave0_PWDATA(5) =>
|
| 7782 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[5]\,
|
| 7783 |
|
|
CoreAPB_0_APBmslave0_PWDATA(4) =>
|
| 7784 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[4]\,
|
| 7785 |
|
|
CoreAPB_0_APBmslave0_PWDATA(3) =>
|
| 7786 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[3]\,
|
| 7787 |
|
|
CoreAPB_0_APBmslave0_PWDATA(2) =>
|
| 7788 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[2]\,
|
| 7789 |
|
|
CoreAPB_0_APBmslave0_PWDATA(1) =>
|
| 7790 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[1]\,
|
| 7791 |
|
|
CoreAPB_0_APBmslave0_PWDATA(0) =>
|
| 7792 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[0]\,
|
| 7793 |
|
|
CoreAPB_0_APBmslave0_PADDR(4) =>
|
| 7794 |
|
|
\CoreAPB_0_APBmslave0_PADDR[4]\,
|
| 7795 |
|
|
CoreAPB_0_APBmslave0_PADDR(3) =>
|
| 7796 |
|
|
\CoreAPB_0_APBmslave0_PADDR[3]\,
|
| 7797 |
|
|
CoreAPB_0_APBmslave0_PADDR(2) =>
|
| 7798 |
|
|
\CoreAPB_0_APBmslave0_PADDR[2]\, TX_c => TX_c, HRESETn_c
|
| 7799 |
|
|
=> HRESETn_c, HCLK_c => HCLK_c,
|
| 7800 |
|
|
CoreAPB_0_APBmslave0_PENABLE =>
|
| 7801 |
|
|
CoreAPB_0_APBmslave0_PENABLE, CoreAPB_0_APBmslave0_PWRITE
|
| 7802 |
|
|
=> CoreAPB_0_APBmslave0_PWRITE,
|
| 7803 |
|
|
CoreAPB_0_APBmslave0_PSELx => CoreAPB_0_APBmslave0_PSELx);
|
| 7804 |
|
|
|
| 7805 |
|
|
\ADDR_pad[29]\ : INBUF
|
| 7806 |
|
|
port map(PAD => ADDR(29), Y => \ADDR_c[29]\);
|
| 7807 |
|
|
|
| 7808 |
|
|
\DATAIN_pad[6]\ : INBUF
|
| 7809 |
|
|
port map(PAD => DATAIN(6), Y => \DATAIN_c[6]\);
|
| 7810 |
|
|
|
| 7811 |
|
|
ahb_busy_pad : OUTBUF
|
| 7812 |
|
|
port map(D => ahb_busy_c, PAD => ahb_busy);
|
| 7813 |
|
|
|
| 7814 |
|
|
\DATAOUT_pad[31]\ : OUTBUF
|
| 7815 |
|
|
port map(D => \GND\, PAD => DATAOUT(31));
|
| 7816 |
|
|
|
| 7817 |
|
|
\DATAOUT_pad[30]\ : OUTBUF
|
| 7818 |
|
|
port map(D => \GND\, PAD => DATAOUT(30));
|
| 7819 |
|
|
|
| 7820 |
|
|
\DATAIN_pad[3]\ : INBUF
|
| 7821 |
|
|
port map(PAD => DATAIN(3), Y => \DATAIN_c[3]\);
|
| 7822 |
|
|
|
| 7823 |
|
|
\ADDR_pad[24]\ : INBUF
|
| 7824 |
|
|
port map(PAD => ADDR(24), Y => \ADDR_c[24]\);
|
| 7825 |
|
|
|
| 7826 |
|
|
\RESP_err_pad[1]\ : OUTBUF
|
| 7827 |
|
|
port map(D => \GND\, PAD => RESP_err(1));
|
| 7828 |
|
|
|
| 7829 |
|
|
\ADDR_pad[25]\ : INBUF
|
| 7830 |
|
|
port map(PAD => ADDR(25), Y => \ADDR_c[25]\);
|
| 7831 |
|
|
|
| 7832 |
|
|
\DATAOUT_pad[9]\ : OUTBUF
|
| 7833 |
|
|
port map(D => \GND\, PAD => DATAOUT(9));
|
| 7834 |
|
|
|
| 7835 |
|
|
\DATAOUT_pad[28]\ : OUTBUF
|
| 7836 |
|
|
port map(D => \GND\, PAD => DATAOUT(28));
|
| 7837 |
|
|
|
| 7838 |
|
|
LWRITE_pad : INBUF
|
| 7839 |
|
|
port map(PAD => LWRITE, Y => LWRITE_c);
|
| 7840 |
|
|
|
| 7841 |
|
|
\DATAOUT_pad[3]\ : OUTBUF
|
| 7842 |
|
|
port map(D => \DATAOUT_c[3]\, PAD => DATAOUT(3));
|
| 7843 |
|
|
|
| 7844 |
|
|
\DATAOUT_pad[22]\ : OUTBUF
|
| 7845 |
|
|
port map(D => \GND\, PAD => DATAOUT(22));
|
| 7846 |
|
|
|
| 7847 |
|
|
\ADDR_pad[27]\ : INBUF
|
| 7848 |
|
|
port map(PAD => ADDR(27), Y => \ADDR_c[27]\);
|
| 7849 |
|
|
|
| 7850 |
|
|
\DATAOUT_pad[6]\ : OUTBUF
|
| 7851 |
|
|
port map(D => \DATAOUT_c[6]\, PAD => DATAOUT(6));
|
| 7852 |
|
|
|
| 7853 |
|
|
\DATAOUT_pad[11]\ : OUTBUF
|
| 7854 |
|
|
port map(D => \GND\, PAD => DATAOUT(11));
|
| 7855 |
|
|
|
| 7856 |
|
|
\DATAOUT_pad[10]\ : OUTBUF
|
| 7857 |
|
|
port map(D => \GND\, PAD => DATAOUT(10));
|
| 7858 |
|
|
|
| 7859 |
|
|
\DATAOUT_pad[4]\ : OUTBUF
|
| 7860 |
|
|
port map(D => \DATAOUT_c[4]\, PAD => DATAOUT(4));
|
| 7861 |
|
|
|
| 7862 |
|
|
CoreAHB2APB_0 : CoreAHB2APB
|
| 7863 |
|
|
port map(CoreAHBLite_0_AHBmslave0_HWDATA(7) =>
|
| 7864 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[7]\,
|
| 7865 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(6) =>
|
| 7866 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[6]\,
|
| 7867 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(5) =>
|
| 7868 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[5]\,
|
| 7869 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(4) =>
|
| 7870 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[4]\,
|
| 7871 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(3) =>
|
| 7872 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[3]\,
|
| 7873 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(2) =>
|
| 7874 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[2]\,
|
| 7875 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(1) =>
|
| 7876 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[1]\,
|
| 7877 |
|
|
CoreAHBLite_0_AHBmslave0_HWDATA(0) =>
|
| 7878 |
|
|
\CoreAHBLite_0_AHBmslave0_HWDATA[0]\,
|
| 7879 |
|
|
CoreAPB_0_APBmslave0_PWDATA(7) =>
|
| 7880 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[7]\,
|
| 7881 |
|
|
CoreAPB_0_APBmslave0_PWDATA(6) =>
|
| 7882 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[6]\,
|
| 7883 |
|
|
CoreAPB_0_APBmslave0_PWDATA(5) =>
|
| 7884 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[5]\,
|
| 7885 |
|
|
CoreAPB_0_APBmslave0_PWDATA(4) =>
|
| 7886 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[4]\,
|
| 7887 |
|
|
CoreAPB_0_APBmslave0_PWDATA(3) =>
|
| 7888 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[3]\,
|
| 7889 |
|
|
CoreAPB_0_APBmslave0_PWDATA(2) =>
|
| 7890 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[2]\,
|
| 7891 |
|
|
CoreAPB_0_APBmslave0_PWDATA(1) =>
|
| 7892 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[1]\,
|
| 7893 |
|
|
CoreAPB_0_APBmslave0_PWDATA(0) =>
|
| 7894 |
|
|
\CoreAPB_0_APBmslave0_PWDATA[0]\,
|
| 7895 |
|
|
CoreAPB_0_APBmslave0_PADDR(4) =>
|
| 7896 |
|
|
\CoreAPB_0_APBmslave0_PADDR[4]\,
|
| 7897 |
|
|
CoreAPB_0_APBmslave0_PADDR(3) =>
|
| 7898 |
|
|
\CoreAPB_0_APBmslave0_PADDR[3]\,
|
| 7899 |
|
|
CoreAPB_0_APBmslave0_PADDR(2) =>
|
| 7900 |
|
|
\CoreAPB_0_APBmslave0_PADDR[2]\,
|
| 7901 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(15) =>
|
| 7902 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[15]\,
|
| 7903 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(14) =>
|
| 7904 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[14]\,
|
| 7905 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(13) =>
|
| 7906 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[13]\,
|
| 7907 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(12) =>
|
| 7908 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[12]\,
|
| 7909 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(11) =>
|
| 7910 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[11]\,
|
| 7911 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(10) =>
|
| 7912 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[10]\,
|
| 7913 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(9) =>
|
| 7914 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[9]\,
|
| 7915 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(8) =>
|
| 7916 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[8]\,
|
| 7917 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(7) =>
|
| 7918 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[7]\,
|
| 7919 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(6) =>
|
| 7920 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[6]\,
|
| 7921 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(5) =>
|
| 7922 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[5]\,
|
| 7923 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(4) =>
|
| 7924 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[4]\,
|
| 7925 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(3) =>
|
| 7926 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[3]\,
|
| 7927 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(2) =>
|
| 7928 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[2]\,
|
| 7929 |
|
|
CoreAHB2APB_0_APBmaster_PSELx(1) =>
|
| 7930 |
|
|
\CoreAHB2APB_0_APBmaster_PSELx[1]\,
|
| 7931 |
|
|
arbRegSMCurrentState_i_0_0 =>
|
| 7932 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_i_0[12]\,
|
| 7933 |
|
|
arbRegSMCurrentState_i_0_3 =>
|
| 7934 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_i_0[15]\,
|
| 7935 |
|
|
xhdl1222_0 => \CoreAHBLite_0.matrix4x16.xhdl1222[0]\,
|
| 7936 |
|
|
masterAddrInProg_i_1_0 =>
|
| 7937 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.masterAddrInProg_i_1[0]\,
|
| 7938 |
|
|
arbRegSMCurrentState_RNICAHF7_0 =>
|
| 7939 |
|
|
\arbRegSMCurrentState_RNICAHF7[0]\,
|
| 7940 |
|
|
CoreAPB_0_APBmslave0_PWRITE =>
|
| 7941 |
|
|
CoreAPB_0_APBmslave0_PWRITE, CoreAPB_0_APBmslave0_PSELx
|
| 7942 |
|
|
=> CoreAPB_0_APBmslave0_PSELx, HRESETn_c => HRESETn_c,
|
| 7943 |
|
|
HCLK_c => HCLK_c, CoreAPB_0_APBmslave0_PENABLE =>
|
| 7944 |
|
|
CoreAPB_0_APBmslave0_PENABLE, N_124_0 => N_124, N_128_0
|
| 7945 |
|
|
=> N_128, N_22 => N_22, N_20 => N_20, N_18 => N_18,
|
| 7946 |
|
|
N_395 => N_395, N_363 => N_363, N_364 => N_364,
|
| 7947 |
|
|
HTRANS_0_a3_i_a2_3_0 =>
|
| 7948 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.HTRANS_0_a3_i_a2_3_0\,
|
| 7949 |
|
|
N_265 => N_265, N_392 => N_392, N_135 => N_135, N_367 =>
|
| 7950 |
|
|
N_367, defSlaveSMCurrentState =>
|
| 7951 |
|
|
\CoreAHBLite_0.matrix4x16.masterstage_0.default_slave_sm.defSlaveSMCurrentState\,
|
| 7952 |
|
|
N_391 => N_391, HTRANS_0_a3_i_a2_4_0 =>
|
| 7953 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.HTRANS_0_a3_i_a2_4_0\,
|
| 7954 |
|
|
N_398 => N_398, un1_N_11_mux_i_5_a1_1 =>
|
| 7955 |
|
|
\CoreAHB2APB_0.un1_N_11_mux_i_5_a1_1\, N_327 => N_327,
|
| 7956 |
|
|
un4_m5_0_a3_1 => \CoreAHB2APB_0.un4_m5_0_a3_1\,
|
| 7957 |
|
|
un4_m5_0_a3_2 => \CoreAHB2APB_0.un4_m5_0_a3_2\, N_171 =>
|
| 7958 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.N_171\,
|
| 7959 |
|
|
N_330 => N_330, N_397 => N_397, N_326 => N_326,
|
| 7960 |
|
|
un1_m1_e_0_0 => \CoreAHB2APB_0.un1_m1_e_0_0\,
|
| 7961 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY =>
|
| 7962 |
|
|
CoreAHBLite_0_AHBmslave0_HREADY,
|
| 7963 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx =>
|
| 7964 |
|
|
CoreAHBLite_0_AHBmslave0_HSELx, HADDR_24_0_a3_i_out =>
|
| 7965 |
|
|
\CoreAHBLite_0.matrix4x16.slavestage_0.HADDR_24_0_a3_i_out\,
|
| 7966 |
|
|
N_263 => N_263, N_323 => N_323, N_365 => N_365, N_254 =>
|
| 7967 |
|
|
N_254, N_120 => N_120);
|
| 7968 |
|
|
|
| 7969 |
|
|
\ADDR_pad[31]\ : INBUF
|
| 7970 |
|
|
port map(PAD => ADDR(31), Y => \ADDR_c[31]\);
|
| 7971 |
|
|
|
| 7972 |
|
|
\ADDR_pad[30]\ : INBUF
|
| 7973 |
|
|
port map(PAD => ADDR(30), Y => \ADDR_c[30]\);
|
| 7974 |
|
|
|
| 7975 |
|
|
\DATAOUT_pad[5]\ : OUTBUF
|
| 7976 |
|
|
port map(D => \DATAOUT_c[5]\, PAD => DATAOUT(5));
|
| 7977 |
|
|
|
| 7978 |
|
|
\DATAOUT_pad[19]\ : OUTBUF
|
| 7979 |
|
|
port map(D => \GND\, PAD => DATAOUT(19));
|
| 7980 |
|
|
|
| 7981 |
|
|
HRESETn_pad : CLKBUF
|
| 7982 |
|
|
port map(PAD => HRESETn, Y => HRESETn_c);
|
| 7983 |
|
|
|
| 7984 |
|
|
\DATAOUT_pad[14]\ : OUTBUF
|
| 7985 |
|
|
port map(D => \GND\, PAD => DATAOUT(14));
|
| 7986 |
|
|
|
| 7987 |
|
|
\DATAOUT_pad[23]\ : OUTBUF
|
| 7988 |
|
|
port map(D => \GND\, PAD => DATAOUT(23));
|
| 7989 |
|
|
|
| 7990 |
|
|
|
| 7991 |
|
|
end DEF_ARCH;
|
