| 1 |
3 |
uson |
KEY LIBERO "11.8"
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| 2 |
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KEY CAPTURE "11.8.3.6"
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| 3 |
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KEY DEFAULT_IMPORT_LOC "D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_new\AHB_master_fabric\component\work\Top"
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| 4 |
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KEY DEFAULT_OPEN_LOC ""
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| 5 |
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KEY ProjectID "0"
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| 6 |
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KEY HDLTechnology "VHDL"
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| 7 |
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KEY VERILOGMODE "VERILOG2001"
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| 8 |
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KEY VHDLMODE "VHDL2008"
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| 9 |
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KEY UseConstraintFlowTechnology "FALSE"
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| 10 |
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KEY VendorTechnology_Family "ProASIC3"
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| 11 |
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KEY VendorTechnology_Die "UM4X4M1N"
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| 12 |
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KEY VendorTechnology_Package "vq100"
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| 13 |
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KEY VendorTechnology_Speed "STD"
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| 14 |
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KEY VendorTechnology_DieVoltage "1.5"
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| 15 |
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KEY VendorTechnology_PART_RANGE "IND"
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| 16 |
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KEY VendorTechnology_DSW_VCCA_VOLTAGE_RAMP_RATE ""
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| 17 |
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KEY VendorTechnology_IO_DEFT_STD "LVTTL"
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| 18 |
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KEY VendorTechnology_OPCONR ""
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| 19 |
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KEY VendorTechnology_PLL_SUPPLY ""
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| 20 |
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KEY VendorTechnology_RAD_EXPOSURE ""
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| 21 |
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KEY VendorTechnology_RESERVEMIGRATIONPINS "1"
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| 22 |
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KEY VendorTechnology_RESTRICTPROBEPINS "1"
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| 23 |
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KEY VendorTechnology_RESTRICTSPIPINS "0"
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| 24 |
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KEY VendorTechnology_SYSTEM_CONTROLLER_SUSPEND_MODE ""
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| 25 |
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KEY VendorTechnology_TARGETDEVICESFORMIGRATION "UM4X4M1N"
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| 26 |
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KEY VendorTechnology_TEMPR "IND"
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| 27 |
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KEY VendorTechnology_UNUSED_MSS_IO_RESISTOR_PULL "None"
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| 28 |
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KEY VendorTechnology_VCCI_1.5_VOLTR "COM"
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| 29 |
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KEY VendorTechnology_VCCI_1.8_VOLTR "COM"
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| 30 |
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KEY VendorTechnology_VCCI_2.5_VOLTR "COM"
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| 31 |
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KEY VendorTechnology_VCCI_3.3_VOLTR "COM"
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| 32 |
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KEY VendorTechnology_VOLTR "IND"
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| 33 |
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KEY ProjectLocation "C:\Actelprj\test79_AHBmaster"
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| 34 |
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KEY ProjectDescription ""
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| 35 |
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KEY Pa4PeripheralNewSeq "GOOD"
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| 36 |
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KEY SimulationType "VHDL"
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| 37 |
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KEY Vendor "Actel"
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| 38 |
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KEY ActiveRoot "top::work"
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| 39 |
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LIST REVISIONS
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| 40 |
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VALUE="Impl1",NUM=1
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| 41 |
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CURREV=1
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| 42 |
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ENDLIST
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| 43 |
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LIST LIBRARIES
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| 44 |
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COREAHBLITE_LIB
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| 45 |
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COREUARTAPB_LIB
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| 46 |
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ENDLIST
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| 47 |
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LIST LIBRARY_COREAHBLITE_LIB
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| 48 |
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ALIAS=..\component\Actel\DirectCore\CoreAHBLite\5.3.101\mti\user_vhdl\COREAHBLITE_LIB
|
| 49 |
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COMPILE_OPTION=REFRESH_AND_COMPILE
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| 50 |
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CUSTOMPATH=false
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| 51 |
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ENDLIST
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| 52 |
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LIST LIBRARY_COREUARTAPB_LIB
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| 53 |
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ALIAS=COREUARTAPB_LIB
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| 54 |
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COMPILE_OPTION=COMPILE
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| 55 |
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CUSTOMPATH=false
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| 56 |
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ENDLIST
|
| 57 |
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LIST FileManager
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| 58 |
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VALUE "\component\Actel\DirectCore\CoreAHB2APB\1.1.101\CoreAHB2APB.cxf,actgen_cxf"
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| 59 |
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STATE="utd"
|
| 60 |
|
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TIME="1527947576"
|
| 61 |
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SIZE="479"
|
| 62 |
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PARENT="\component\work\top\top.cxf"
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| 63 |
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ENDFILE
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| 64 |
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VALUE "\component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd,hdl"
|
| 65 |
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STATE="utd"
|
| 66 |
|
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TIME="1527947216"
|
| 67 |
|
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SIZE="25936"
|
| 68 |
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PARENT="\component\Actel\DirectCore\CoreAHB2APB\1.1.101\CoreAHB2APB.cxf"
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| 69 |
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IS_READONLY="TRUE"
|
| 70 |
|
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ENDFILE
|
| 71 |
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VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf,actgen_cxf"
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| 72 |
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STATE="utd"
|
| 73 |
|
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TIME="1527947577"
|
| 74 |
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SIZE="4352"
|
| 75 |
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PARENT="\component\work\top\top.cxf"
|
| 76 |
|
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ENDFILE
|
| 77 |
|
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VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\mti\scripts\wave_user.do,do"
|
| 78 |
|
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STATE="utd"
|
| 79 |
|
|
TIME="1527947216"
|
| 80 |
|
|
SIZE="912"
|
| 81 |
|
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PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 82 |
|
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IS_READONLY="TRUE"
|
| 83 |
|
|
ENDFILE
|
| 84 |
|
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VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
|
| 85 |
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STATE="utd"
|
| 86 |
|
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TIME="1527947216"
|
| 87 |
|
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SIZE="8290"
|
| 88 |
|
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LIBRARY="COREAHBLITE_LIB"
|
| 89 |
|
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PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 90 |
|
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PARENT="\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
|
| 91 |
|
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IS_READONLY="TRUE"
|
| 92 |
|
|
ENDFILE
|
| 93 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
|
| 94 |
|
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STATE="utd"
|
| 95 |
|
|
TIME="1527947216"
|
| 96 |
|
|
SIZE="2348"
|
| 97 |
|
|
LIBRARY="COREAHBLITE_LIB"
|
| 98 |
|
|
PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 99 |
|
|
PARENT="\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
|
| 100 |
|
|
IS_READONLY="TRUE"
|
| 101 |
|
|
ENDFILE
|
| 102 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
|
| 103 |
|
|
STATE="utd"
|
| 104 |
|
|
TIME="1527947216"
|
| 105 |
|
|
SIZE="22169"
|
| 106 |
|
|
LIBRARY="COREAHBLITE_LIB"
|
| 107 |
|
|
PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 108 |
|
|
PARENT="\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
|
| 109 |
|
|
IS_READONLY="TRUE"
|
| 110 |
|
|
ENDFILE
|
| 111 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
|
| 112 |
|
|
STATE="utd"
|
| 113 |
|
|
TIME="1527947216"
|
| 114 |
|
|
SIZE="82848"
|
| 115 |
|
|
LIBRARY="COREAHBLITE_LIB"
|
| 116 |
|
|
PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 117 |
|
|
PARENT="\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
|
| 118 |
|
|
IS_READONLY="TRUE"
|
| 119 |
|
|
ENDFILE
|
| 120 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
|
| 121 |
|
|
STATE="utd"
|
| 122 |
|
|
TIME="1527947216"
|
| 123 |
|
|
SIZE="45707"
|
| 124 |
|
|
LIBRARY="COREAHBLITE_LIB"
|
| 125 |
|
|
PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 126 |
|
|
PARENT="\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
|
| 127 |
|
|
IS_READONLY="TRUE"
|
| 128 |
|
|
ENDFILE
|
| 129 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
|
| 130 |
|
|
STATE="utd"
|
| 131 |
|
|
TIME="1527947216"
|
| 132 |
|
|
SIZE="12780"
|
| 133 |
|
|
LIBRARY="COREAHBLITE_LIB"
|
| 134 |
|
|
PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 135 |
|
|
PARENT="\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
|
| 136 |
|
|
IS_READONLY="TRUE"
|
| 137 |
|
|
ENDFILE
|
| 138 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
|
| 139 |
|
|
STATE="utd"
|
| 140 |
|
|
TIME="1527947216"
|
| 141 |
|
|
SIZE="23829"
|
| 142 |
|
|
LIBRARY="COREAHBLITE_LIB"
|
| 143 |
|
|
PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 144 |
|
|
PARENT="\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
|
| 145 |
|
|
IS_READONLY="TRUE"
|
| 146 |
|
|
ENDFILE
|
| 147 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_addrdec.vhd,hdl"
|
| 148 |
|
|
STATE="utd"
|
| 149 |
|
|
TIME="1527947216"
|
| 150 |
|
|
SIZE="11215"
|
| 151 |
|
|
LIBRARY="COREAHBLITE_LIB"
|
| 152 |
|
|
PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 153 |
|
|
IS_READONLY="TRUE"
|
| 154 |
|
|
ENDFILE
|
| 155 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_defaultslavesm.vhd,hdl"
|
| 156 |
|
|
STATE="utd"
|
| 157 |
|
|
TIME="1527947216"
|
| 158 |
|
|
SIZE="2760"
|
| 159 |
|
|
LIBRARY="COREAHBLITE_LIB"
|
| 160 |
|
|
PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 161 |
|
|
IS_READONLY="TRUE"
|
| 162 |
|
|
ENDFILE
|
| 163 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd,hdl"
|
| 164 |
|
|
STATE="utd"
|
| 165 |
|
|
TIME="1527947216"
|
| 166 |
|
|
SIZE="30586"
|
| 167 |
|
|
LIBRARY="COREAHBLITE_LIB"
|
| 168 |
|
|
PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 169 |
|
|
IS_READONLY="TRUE"
|
| 170 |
|
|
ENDFILE
|
| 171 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd,hdl"
|
| 172 |
|
|
STATE="utd"
|
| 173 |
|
|
TIME="1527947216"
|
| 174 |
|
|
SIZE="426134"
|
| 175 |
|
|
LIBRARY="COREAHBLITE_LIB"
|
| 176 |
|
|
PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 177 |
|
|
IS_READONLY="TRUE"
|
| 178 |
|
|
ENDFILE
|
| 179 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_pkg.vhd,hdl"
|
| 180 |
|
|
STATE="utd"
|
| 181 |
|
|
TIME="1527947216"
|
| 182 |
|
|
SIZE="425"
|
| 183 |
|
|
LIBRARY="COREAHBLITE_LIB"
|
| 184 |
|
|
PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 185 |
|
|
IS_READONLY="TRUE"
|
| 186 |
|
|
ENDFILE
|
| 187 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd,hdl"
|
| 188 |
|
|
STATE="utd"
|
| 189 |
|
|
TIME="1527947216"
|
| 190 |
|
|
SIZE="17249"
|
| 191 |
|
|
LIBRARY="COREAHBLITE_LIB"
|
| 192 |
|
|
PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 193 |
|
|
IS_READONLY="TRUE"
|
| 194 |
|
|
ENDFILE
|
| 195 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavestage.vhd,hdl"
|
| 196 |
|
|
STATE="utd"
|
| 197 |
|
|
TIME="1527947216"
|
| 198 |
|
|
SIZE="12256"
|
| 199 |
|
|
LIBRARY="COREAHBLITE_LIB"
|
| 200 |
|
|
PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 201 |
|
|
IS_READONLY="TRUE"
|
| 202 |
|
|
ENDFILE
|
| 203 |
|
|
VALUE "\component\Actel\DirectCore\CoreAPB\1.1.101\CoreAPB.cxf,actgen_cxf"
|
| 204 |
|
|
STATE="utd"
|
| 205 |
|
|
TIME="1527947577"
|
| 206 |
|
|
SIZE="568"
|
| 207 |
|
|
PARENT="\component\work\top\top.cxf"
|
| 208 |
|
|
ENDFILE
|
| 209 |
|
|
VALUE "\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd,hdl"
|
| 210 |
|
|
STATE="utd"
|
| 211 |
|
|
TIME="1527947216"
|
| 212 |
|
|
SIZE="9093"
|
| 213 |
|
|
PARENT="\component\Actel\DirectCore\CoreAPB\1.1.101\CoreAPB.cxf"
|
| 214 |
|
|
IS_READONLY="TRUE"
|
| 215 |
|
|
ENDFILE
|
| 216 |
|
|
VALUE "\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\MuxP2B.vhd,hdl"
|
| 217 |
|
|
STATE="utd"
|
| 218 |
|
|
TIME="1527947216"
|
| 219 |
|
|
SIZE="3954"
|
| 220 |
|
|
PARENT="\component\Actel\DirectCore\CoreAPB\1.1.101\CoreAPB.cxf"
|
| 221 |
|
|
IS_READONLY="TRUE"
|
| 222 |
|
|
ENDFILE
|
| 223 |
|
|
VALUE "\component\Actel\DirectCore\CoreUARTapb\5.6.102\CoreUARTapb.cxf,actgen_cxf"
|
| 224 |
|
|
STATE="utd"
|
| 225 |
|
|
TIME="1527947577"
|
| 226 |
|
|
SIZE="779"
|
| 227 |
|
|
PARENT="\component\work\top\top.cxf"
|
| 228 |
|
|
ENDFILE
|
| 229 |
|
|
VALUE "\component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf,actgen_cxf"
|
| 230 |
|
|
STATE="utd"
|
| 231 |
|
|
TIME="1527947577"
|
| 232 |
|
|
SIZE="437"
|
| 233 |
|
|
ENDFILE
|
| 234 |
|
|
VALUE "\component\work\DESIGN_IO\DESIGN_IO.cxf,actgen_cxf"
|
| 235 |
|
|
STATE="utd"
|
| 236 |
|
|
TIME="1527947584"
|
| 237 |
|
|
SIZE="413"
|
| 238 |
|
|
ENDFILE
|
| 239 |
|
|
VALUE "\component\work\tb_top\tb_top.cxf,actgen_cxf"
|
| 240 |
|
|
STATE="utd"
|
| 241 |
|
|
TIME="1527947563"
|
| 242 |
|
|
SIZE="2058"
|
| 243 |
|
|
ENDFILE
|
| 244 |
|
|
VALUE "\component\work\tb_top\tb_top.vhd,tb_hdl"
|
| 245 |
|
|
STATE="utd"
|
| 246 |
|
|
TIME="1527947563"
|
| 247 |
|
|
SIZE="4599"
|
| 248 |
|
|
PARENT="\component\work\tb_top\tb_top.cxf"
|
| 249 |
|
|
IS_READONLY="TRUE"
|
| 250 |
|
|
ENDFILE
|
| 251 |
|
|
VALUE "\component\work\top\CoreAHBLite_0\coreparameters.vhd,tb_hdl"
|
| 252 |
|
|
STATE="utd"
|
| 253 |
|
|
TIME="1527947577"
|
| 254 |
|
|
SIZE="4439"
|
| 255 |
|
|
LIBRARY="COREAHBLITE_LIB"
|
| 256 |
|
|
PARENT="\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
|
| 257 |
|
|
IS_READONLY="TRUE"
|
| 258 |
|
|
ENDFILE
|
| 259 |
|
|
VALUE "\component\work\top\CoreAHBLite_0\rtl\vhdl\core\components.vhd,hdl"
|
| 260 |
|
|
STATE="utd"
|
| 261 |
|
|
TIME="1527947577"
|
| 262 |
|
|
SIZE="18847"
|
| 263 |
|
|
LIBRARY="COREAHBLITE_LIB"
|
| 264 |
|
|
PARENT="\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
|
| 265 |
|
|
IS_READONLY="TRUE"
|
| 266 |
|
|
ENDFILE
|
| 267 |
|
|
VALUE "\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd,hdl"
|
| 268 |
|
|
STATE="utd"
|
| 269 |
|
|
TIME="1527947577"
|
| 270 |
|
|
SIZE="62342"
|
| 271 |
|
|
LIBRARY="COREAHBLITE_LIB"
|
| 272 |
|
|
PARENT="\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
|
| 273 |
|
|
IS_READONLY="TRUE"
|
| 274 |
|
|
ENDFILE
|
| 275 |
|
|
VALUE "\component\work\top\CoreAHBLite_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
|
| 276 |
|
|
STATE="utd"
|
| 277 |
|
|
TIME="1527947577"
|
| 278 |
|
|
SIZE="68328"
|
| 279 |
|
|
LIBRARY="COREAHBLITE_LIB"
|
| 280 |
|
|
PARENT="\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
|
| 281 |
|
|
MODULE_UNDER_TEST="testbench"
|
| 282 |
|
|
SIMULATION_TIME="-all"
|
| 283 |
|
|
IS_READONLY="TRUE"
|
| 284 |
|
|
ENDFILE
|
| 285 |
|
|
VALUE "\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf,actgen_cxf"
|
| 286 |
|
|
STATE="utd"
|
| 287 |
|
|
TIME="1527947577"
|
| 288 |
|
|
SIZE="2631"
|
| 289 |
|
|
PARENT="\component\work\top\top.cxf"
|
| 290 |
|
|
ENDFILE
|
| 291 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\coreparameters.vhd,tb_hdl"
|
| 292 |
|
|
STATE="utd"
|
| 293 |
|
|
TIME="1527947577"
|
| 294 |
|
|
SIZE="970"
|
| 295 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 296 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 297 |
|
|
IS_READONLY="TRUE"
|
| 298 |
|
|
ENDFILE
|
| 299 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\mti\scripts\bfmtovec_compile.do,do"
|
| 300 |
|
|
STATE="utd"
|
| 301 |
|
|
TIME="1527947577"
|
| 302 |
|
|
SIZE="1011"
|
| 303 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 304 |
|
|
IS_READONLY="TRUE"
|
| 305 |
|
|
ENDFILE
|
| 306 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\mti\scripts\wave_vhdl_amba.do,do"
|
| 307 |
|
|
STATE="utd"
|
| 308 |
|
|
TIME="1527947577"
|
| 309 |
|
|
SIZE="1933"
|
| 310 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 311 |
|
|
IS_READONLY="TRUE"
|
| 312 |
|
|
ENDFILE
|
| 313 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
|
| 314 |
|
|
STATE="utd"
|
| 315 |
|
|
TIME="1527947577"
|
| 316 |
|
|
SIZE="8379"
|
| 317 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 318 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 319 |
|
|
IS_READONLY="TRUE"
|
| 320 |
|
|
ENDFILE
|
| 321 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahblapb.vhd,tb_hdl"
|
| 322 |
|
|
STATE="utd"
|
| 323 |
|
|
TIME="1527947577"
|
| 324 |
|
|
SIZE="11124"
|
| 325 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 326 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 327 |
|
|
IS_READONLY="TRUE"
|
| 328 |
|
|
ENDFILE
|
| 329 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
|
| 330 |
|
|
STATE="utd"
|
| 331 |
|
|
TIME="1527947577"
|
| 332 |
|
|
SIZE="2437"
|
| 333 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 334 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 335 |
|
|
IS_READONLY="TRUE"
|
| 336 |
|
|
ENDFILE
|
| 337 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
|
| 338 |
|
|
STATE="utd"
|
| 339 |
|
|
TIME="1527947577"
|
| 340 |
|
|
SIZE="22276"
|
| 341 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 342 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 343 |
|
|
IS_READONLY="TRUE"
|
| 344 |
|
|
ENDFILE
|
| 345 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd,tb_hdl"
|
| 346 |
|
|
STATE="utd"
|
| 347 |
|
|
TIME="1527947577"
|
| 348 |
|
|
SIZE="4080"
|
| 349 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 350 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 351 |
|
|
IS_READONLY="TRUE"
|
| 352 |
|
|
ENDFILE
|
| 353 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apb.vhd,tb_hdl"
|
| 354 |
|
|
STATE="utd"
|
| 355 |
|
|
TIME="1527947577"
|
| 356 |
|
|
SIZE="9647"
|
| 357 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 358 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 359 |
|
|
IS_READONLY="TRUE"
|
| 360 |
|
|
ENDFILE
|
| 361 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslave.vhd,tb_hdl"
|
| 362 |
|
|
STATE="utd"
|
| 363 |
|
|
TIME="1527947577"
|
| 364 |
|
|
SIZE="2163"
|
| 365 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 366 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 367 |
|
|
IS_READONLY="TRUE"
|
| 368 |
|
|
ENDFILE
|
| 369 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd,tb_hdl"
|
| 370 |
|
|
STATE="utd"
|
| 371 |
|
|
TIME="1527947577"
|
| 372 |
|
|
SIZE="12526"
|
| 373 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 374 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 375 |
|
|
IS_READONLY="TRUE"
|
| 376 |
|
|
ENDFILE
|
| 377 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbtoapb.vhd,tb_hdl"
|
| 378 |
|
|
STATE="utd"
|
| 379 |
|
|
TIME="1527947577"
|
| 380 |
|
|
SIZE="4078"
|
| 381 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 382 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 383 |
|
|
IS_READONLY="TRUE"
|
| 384 |
|
|
ENDFILE
|
| 385 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
|
| 386 |
|
|
STATE="utd"
|
| 387 |
|
|
TIME="1527947577"
|
| 388 |
|
|
SIZE="82918"
|
| 389 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 390 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 391 |
|
|
IS_READONLY="TRUE"
|
| 392 |
|
|
ENDFILE
|
| 393 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
|
| 394 |
|
|
STATE="utd"
|
| 395 |
|
|
TIME="1527947577"
|
| 396 |
|
|
SIZE="45926"
|
| 397 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 398 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 399 |
|
|
IS_READONLY="TRUE"
|
| 400 |
|
|
ENDFILE
|
| 401 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
|
| 402 |
|
|
STATE="utd"
|
| 403 |
|
|
TIME="1527947577"
|
| 404 |
|
|
SIZE="12888"
|
| 405 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 406 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 407 |
|
|
IS_READONLY="TRUE"
|
| 408 |
|
|
ENDFILE
|
| 409 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
|
| 410 |
|
|
STATE="utd"
|
| 411 |
|
|
TIME="1527947577"
|
| 412 |
|
|
SIZE="23848"
|
| 413 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 414 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 415 |
|
|
IS_READONLY="TRUE"
|
| 416 |
|
|
ENDFILE
|
| 417 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd,hdl"
|
| 418 |
|
|
STATE="utd"
|
| 419 |
|
|
TIME="1527947577"
|
| 420 |
|
|
SIZE="12888"
|
| 421 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 422 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 423 |
|
|
IS_READONLY="TRUE"
|
| 424 |
|
|
ENDFILE
|
| 425 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\core\components.vhd,hdl"
|
| 426 |
|
|
STATE="utd"
|
| 427 |
|
|
TIME="1527947577"
|
| 428 |
|
|
SIZE="2707"
|
| 429 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 430 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 431 |
|
|
IS_READONLY="TRUE"
|
| 432 |
|
|
ENDFILE
|
| 433 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd,hdl"
|
| 434 |
|
|
STATE="utd"
|
| 435 |
|
|
TIME="1527947577"
|
| 436 |
|
|
SIZE="22268"
|
| 437 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 438 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 439 |
|
|
IS_READONLY="TRUE"
|
| 440 |
|
|
ENDFILE
|
| 441 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd,hdl"
|
| 442 |
|
|
STATE="utd"
|
| 443 |
|
|
TIME="1527947577"
|
| 444 |
|
|
SIZE="17722"
|
| 445 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 446 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 447 |
|
|
IS_READONLY="TRUE"
|
| 448 |
|
|
ENDFILE
|
| 449 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\core\coreuart_pkg.vhd,hdl"
|
| 450 |
|
|
STATE="utd"
|
| 451 |
|
|
TIME="1527947577"
|
| 452 |
|
|
SIZE="487"
|
| 453 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 454 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 455 |
|
|
IS_READONLY="TRUE"
|
| 456 |
|
|
ENDFILE
|
| 457 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\core\fifo_256x8_pa3.vhd,hdl"
|
| 458 |
|
|
STATE="utd"
|
| 459 |
|
|
TIME="1527947577"
|
| 460 |
|
|
SIZE="8434"
|
| 461 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 462 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 463 |
|
|
IS_READONLY="TRUE"
|
| 464 |
|
|
ENDFILE
|
| 465 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd,hdl"
|
| 466 |
|
|
STATE="utd"
|
| 467 |
|
|
TIME="1527947577"
|
| 468 |
|
|
SIZE="21552"
|
| 469 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 470 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 471 |
|
|
IS_READONLY="TRUE"
|
| 472 |
|
|
ENDFILE
|
| 473 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd,hdl"
|
| 474 |
|
|
STATE="utd"
|
| 475 |
|
|
TIME="1527947577"
|
| 476 |
|
|
SIZE="11195"
|
| 477 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 478 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 479 |
|
|
IS_READONLY="TRUE"
|
| 480 |
|
|
ENDFILE
|
| 481 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
|
| 482 |
|
|
STATE="utd"
|
| 483 |
|
|
TIME="1527947577"
|
| 484 |
|
|
SIZE="12626"
|
| 485 |
|
|
LIBRARY="COREUARTAPB_LIB"
|
| 486 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 487 |
|
|
MODULE_UNDER_TEST="testbench"
|
| 488 |
|
|
SIMULATION_TIME="-all"
|
| 489 |
|
|
IS_READONLY="TRUE"
|
| 490 |
|
|
ENDFILE
|
| 491 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf,actgen_cxf"
|
| 492 |
|
|
STATE="utd"
|
| 493 |
|
|
TIME="1527947577"
|
| 494 |
|
|
SIZE="5832"
|
| 495 |
|
|
PARENT="\component\work\top\top.cxf"
|
| 496 |
|
|
ENDFILE
|
| 497 |
|
|
VALUE "\component\work\top\top.cxf,actgen_cxf"
|
| 498 |
|
|
STATE="utd"
|
| 499 |
|
|
TIME="1527947584"
|
| 500 |
|
|
SIZE="4888"
|
| 501 |
|
|
ENDFILE
|
| 502 |
|
|
VALUE "\component\work\top\top.vhd,hdl"
|
| 503 |
|
|
STATE="utd"
|
| 504 |
|
|
TIME="1527947577"
|
| 505 |
|
|
SIZE="61971"
|
| 506 |
|
|
PARENT="\component\work\top\top.cxf"
|
| 507 |
|
|
IS_READONLY="TRUE"
|
| 508 |
|
|
ENDFILE
|
| 509 |
|
|
VALUE "\designer\impl1\AHBMASTER_FIC.ide_des,ide_des"
|
| 510 |
|
|
STATE="utd"
|
| 511 |
|
|
TIME="1527781363"
|
| 512 |
|
|
SIZE="193"
|
| 513 |
|
|
ENDFILE
|
| 514 |
|
|
VALUE "\designer\impl1\top.ide_des,ide_des"
|
| 515 |
|
|
STATE="utd"
|
| 516 |
|
|
TIME="1527947605"
|
| 517 |
|
|
SIZE="183"
|
| 518 |
|
|
ENDFILE
|
| 519 |
|
|
VALUE "\hdl\AHBMASTER_FIC.vhd,hdl"
|
| 520 |
|
|
STATE="utd"
|
| 521 |
|
|
TIME="1527947376"
|
| 522 |
|
|
SIZE="6787"
|
| 523 |
|
|
ENDFILE
|
| 524 |
|
|
VALUE "\simulation\bfmtovec_compile.tcl,sim"
|
| 525 |
|
|
STATE="utd"
|
| 526 |
|
|
TIME="1527947216"
|
| 527 |
|
|
SIZE="1462"
|
| 528 |
|
|
PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 529 |
|
|
ENDFILE
|
| 530 |
|
|
VALUE "\simulation\coreahblite_usertb_ahb_master0.bfm,sim"
|
| 531 |
|
|
STATE="utd"
|
| 532 |
|
|
TIME="1527947216"
|
| 533 |
|
|
SIZE="25928"
|
| 534 |
|
|
PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 535 |
|
|
ENDFILE
|
| 536 |
|
|
VALUE "\simulation\coreahblite_usertb_ahb_master1.bfm,sim"
|
| 537 |
|
|
STATE="utd"
|
| 538 |
|
|
TIME="1527947216"
|
| 539 |
|
|
SIZE="6200"
|
| 540 |
|
|
PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 541 |
|
|
ENDFILE
|
| 542 |
|
|
VALUE "\simulation\coreahblite_usertb_ahb_master2.bfm,sim"
|
| 543 |
|
|
STATE="utd"
|
| 544 |
|
|
TIME="1527947216"
|
| 545 |
|
|
SIZE="6200"
|
| 546 |
|
|
PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 547 |
|
|
ENDFILE
|
| 548 |
|
|
VALUE "\simulation\coreahblite_usertb_ahb_master3.bfm,sim"
|
| 549 |
|
|
STATE="utd"
|
| 550 |
|
|
TIME="1527947216"
|
| 551 |
|
|
SIZE="6200"
|
| 552 |
|
|
PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 553 |
|
|
ENDFILE
|
| 554 |
|
|
VALUE "\simulation\coreahblite_usertb_include.bfm,sim"
|
| 555 |
|
|
STATE="utd"
|
| 556 |
|
|
TIME="1527947216"
|
| 557 |
|
|
SIZE="12178"
|
| 558 |
|
|
PARENT="\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
|
| 559 |
|
|
ENDFILE
|
| 560 |
|
|
VALUE "\simulation\coreuart_usertb_apb_master.bfm,sim"
|
| 561 |
|
|
STATE="utd"
|
| 562 |
|
|
TIME="1527947217"
|
| 563 |
|
|
SIZE="2906"
|
| 564 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 565 |
|
|
ENDFILE
|
| 566 |
|
|
VALUE "\simulation\coreuart_usertb_include.bfm,sim"
|
| 567 |
|
|
STATE="utd"
|
| 568 |
|
|
TIME="1527947217"
|
| 569 |
|
|
SIZE="13597"
|
| 570 |
|
|
PARENT="\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
|
| 571 |
|
|
ENDFILE
|
| 572 |
|
|
VALUE "\simulation\run.do,do"
|
| 573 |
|
|
STATE="utd"
|
| 574 |
|
|
TIME="1527947638"
|
| 575 |
|
|
SIZE="1831"
|
| 576 |
|
|
ENDFILE
|
| 577 |
|
|
VALUE "\simulation\subsystem.bfm,sim"
|
| 578 |
|
|
STATE="utd"
|
| 579 |
|
|
TIME="1527947577"
|
| 580 |
|
|
SIZE="793"
|
| 581 |
|
|
PARENT="\component\work\top\top.cxf"
|
| 582 |
|
|
ENDFILE
|
| 583 |
|
|
VALUE "\simulation\tb_top_postsynth_simulation.log,log"
|
| 584 |
|
|
STATE="utd"
|
| 585 |
|
|
TIME="1527947753"
|
| 586 |
|
|
SIZE="13308"
|
| 587 |
|
|
ENDFILE
|
| 588 |
|
|
VALUE "\stimulus\tb_clk.vhd,tb_hdl"
|
| 589 |
|
|
STATE="utd"
|
| 590 |
|
|
TIME="1527947528"
|
| 591 |
|
|
SIZE="1316"
|
| 592 |
|
|
ENDFILE
|
| 593 |
|
|
VALUE "\synthesis\AHBMASTER_FIC.edn,syn_edn"
|
| 594 |
|
|
STATE="utd"
|
| 595 |
|
|
TIME="1527947400"
|
| 596 |
|
|
SIZE="207006"
|
| 597 |
|
|
ENDFILE
|
| 598 |
|
|
VALUE "\synthesis\AHBMASTER_FIC.so,so"
|
| 599 |
|
|
STATE="utd"
|
| 600 |
|
|
TIME="1527947400"
|
| 601 |
|
|
SIZE="224"
|
| 602 |
|
|
ENDFILE
|
| 603 |
|
|
VALUE "\synthesis\AHBMASTER_FIC_sdc.sdc,syn_sdc"
|
| 604 |
|
|
STATE="utd"
|
| 605 |
|
|
TIME="1527947400"
|
| 606 |
|
|
SIZE="404"
|
| 607 |
|
|
ENDFILE
|
| 608 |
|
|
VALUE "\synthesis\AHBMASTER_FIC_syn.prj,prj"
|
| 609 |
|
|
STATE="utd"
|
| 610 |
|
|
TIME="1527947401"
|
| 611 |
|
|
SIZE="1660"
|
| 612 |
|
|
ENDFILE
|
| 613 |
|
|
VALUE "\synthesis\synwork\layer0.so,so"
|
| 614 |
|
|
STATE="utd"
|
| 615 |
|
|
TIME="1527947243"
|
| 616 |
|
|
SIZE="159"
|
| 617 |
|
|
ENDFILE
|
| 618 |
|
|
VALUE "\synthesis\top.edn,syn_edn"
|
| 619 |
|
|
STATE="utd"
|
| 620 |
|
|
TIME="1527947601"
|
| 621 |
|
|
SIZE="586319"
|
| 622 |
|
|
ENDFILE
|
| 623 |
|
|
VALUE "\synthesis\top.so,so"
|
| 624 |
|
|
STATE="utd"
|
| 625 |
|
|
TIME="1527947601"
|
| 626 |
|
|
SIZE="204"
|
| 627 |
|
|
ENDFILE
|
| 628 |
|
|
VALUE "\synthesis\top.vhd,syn_hdl"
|
| 629 |
|
|
STATE="utd"
|
| 630 |
|
|
TIME="1527947637"
|
| 631 |
|
|
SIZE="309167"
|
| 632 |
|
|
ENDFILE
|
| 633 |
|
|
VALUE "\synthesis\top_sdc.sdc,syn_sdc"
|
| 634 |
|
|
STATE="utd"
|
| 635 |
|
|
TIME="1527947601"
|
| 636 |
|
|
SIZE="394"
|
| 637 |
|
|
ENDFILE
|
| 638 |
|
|
VALUE "\synthesis\top_syn.prj,prj"
|
| 639 |
|
|
STATE="utd"
|
| 640 |
|
|
TIME="1527947601"
|
| 641 |
|
|
SIZE="4525"
|
| 642 |
|
|
ENDFILE
|
| 643 |
|
|
ENDLIST
|
| 644 |
|
|
LIST UsedFile
|
| 645 |
|
|
ENDLIST
|
| 646 |
|
|
LIST NewModulesInfo
|
| 647 |
|
|
LIST "AHBMASTER_FIC::work"
|
| 648 |
|
|
FILE "\hdl\AHBMASTER_FIC.vhd,hdl"
|
| 649 |
|
|
LIST ProjectState5.1
|
| 650 |
|
|
LIST Impl1
|
| 651 |
|
|
LiberoState=Post_Synthesis
|
| 652 |
|
|
ideSYNTHESIS(\synthesis\AHBMASTER_FIC.edn,syn_edn)=StateSuccess
|
| 653 |
|
|
LIST FlowOptions
|
| 654 |
|
|
UsePhySynth=FALSE
|
| 655 |
|
|
UseSynth=TRUE
|
| 656 |
|
|
UseFhbAutoInst=FALSE
|
| 657 |
|
|
ENDLIST
|
| 658 |
|
|
Used_File_List
|
| 659 |
|
|
ENDUsed_File_List
|
| 660 |
|
|
ENDLIST
|
| 661 |
|
|
ENDLIST
|
| 662 |
|
|
ENDLIST
|
| 663 |
|
|
LIST "top::work"
|
| 664 |
|
|
FILE "\component\work\top\top.vhd,hdl"
|
| 665 |
|
|
LIST Other_Association
|
| 666 |
|
|
VALUE "\simulation\subsystem.bfm,sim"
|
| 667 |
|
|
ENDLIST
|
| 668 |
|
|
LIST AssociatedStimulus
|
| 669 |
|
|
VALUE "\stimulus\tb_clk.vhd,tb_hdl"
|
| 670 |
|
|
VALUE "\component\work\tb_top\tb_top.vhd,tb_hdl"
|
| 671 |
|
|
ENDLIST
|
| 672 |
|
|
LIST ProjectState5.1
|
| 673 |
|
|
LIST Impl1
|
| 674 |
|
|
LiberoState=Post_Synthesis
|
| 675 |
|
|
ideSYNTHESIS(\synthesis\top.edn,syn_edn)=StateSuccess
|
| 676 |
|
|
ideSTIMULUS=StateSuccess
|
| 677 |
|
|
LIST FlowOptions
|
| 678 |
|
|
UsePhySynth=FALSE
|
| 679 |
|
|
UseSynth=TRUE
|
| 680 |
|
|
UseFhbAutoInst=FALSE
|
| 681 |
|
|
ENDLIST
|
| 682 |
|
|
Used_File_List
|
| 683 |
|
|
ENDUsed_File_List
|
| 684 |
|
|
ENDLIST
|
| 685 |
|
|
ENDLIST
|
| 686 |
|
|
ENDLIST
|
| 687 |
|
|
LIST "top_CoreAHBLite_0_CoreAHBLite::COREAHBLITE_LIB::top_CoreAHBLite_0_components"
|
| 688 |
|
|
FILE "\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd,hdl"
|
| 689 |
|
|
LIST Other_Association
|
| 690 |
|
|
VALUE "\component\work\top\CoreAHBLite_0\coreparameters.vhd,tb_hdl"
|
| 691 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
|
| 692 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
|
| 693 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
|
| 694 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
|
| 695 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
|
| 696 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
|
| 697 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
|
| 698 |
|
|
VALUE "\component\work\top\CoreAHBLite_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
|
| 699 |
|
|
ENDLIST
|
| 700 |
|
|
LIST AssociatedStimulus
|
| 701 |
|
|
VALUE "\component\work\top\CoreAHBLite_0\coreparameters.vhd,tb_hdl"
|
| 702 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
|
| 703 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
|
| 704 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
|
| 705 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
|
| 706 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
|
| 707 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
|
| 708 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
|
| 709 |
|
|
VALUE "\component\work\top\CoreAHBLite_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
|
| 710 |
|
|
ENDLIST
|
| 711 |
|
|
LIST ProjectState5.1
|
| 712 |
|
|
LIST Impl1
|
| 713 |
|
|
ideSTIMULUS=StateSuccess
|
| 714 |
|
|
LIST FlowOptions
|
| 715 |
|
|
UsePhySynth=FALSE
|
| 716 |
|
|
UseSynth=TRUE
|
| 717 |
|
|
UseFhbAutoInst=FALSE
|
| 718 |
|
|
ENDLIST
|
| 719 |
|
|
Used_File_List
|
| 720 |
|
|
ENDUsed_File_List
|
| 721 |
|
|
ENDLIST
|
| 722 |
|
|
ENDLIST
|
| 723 |
|
|
ENDLIST
|
| 724 |
|
|
LIST "top_CoreUARTapb_0_CoreUARTapb::COREUARTAPB_LIB::top_CoreUARTapb_0_components"
|
| 725 |
|
|
FILE "\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd,hdl"
|
| 726 |
|
|
LIST Other_Association
|
| 727 |
|
|
VALUE "\simulation\coreuart_usertb_apb_master.bfm,sim"
|
| 728 |
|
|
VALUE "\simulation\coreuart_usertb_include.bfm,sim"
|
| 729 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\coreparameters.vhd,tb_hdl"
|
| 730 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
|
| 731 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
|
| 732 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
|
| 733 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
|
| 734 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahblapb.vhd,tb_hdl"
|
| 735 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
|
| 736 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
|
| 737 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd,tb_hdl"
|
| 738 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apb.vhd,tb_hdl"
|
| 739 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslave.vhd,tb_hdl"
|
| 740 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd,tb_hdl"
|
| 741 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbtoapb.vhd,tb_hdl"
|
| 742 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
|
| 743 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
|
| 744 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\mti\scripts\bfmtovec_compile.do,do"
|
| 745 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\mti\scripts\wave_vhdl_amba.do,do"
|
| 746 |
|
|
ENDLIST
|
| 747 |
|
|
LIST AssociatedStimulus
|
| 748 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\coreparameters.vhd,tb_hdl"
|
| 749 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
|
| 750 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
|
| 751 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
|
| 752 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
|
| 753 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahblapb.vhd,tb_hdl"
|
| 754 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
|
| 755 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
|
| 756 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd,tb_hdl"
|
| 757 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apb.vhd,tb_hdl"
|
| 758 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslave.vhd,tb_hdl"
|
| 759 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd,tb_hdl"
|
| 760 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbtoapb.vhd,tb_hdl"
|
| 761 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
|
| 762 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
|
| 763 |
|
|
ENDLIST
|
| 764 |
|
|
LIST ProjectState5.1
|
| 765 |
|
|
LIST Impl1
|
| 766 |
|
|
ideSTIMULUS=StateSuccess
|
| 767 |
|
|
LIST FlowOptions
|
| 768 |
|
|
UsePhySynth=FALSE
|
| 769 |
|
|
UseSynth=TRUE
|
| 770 |
|
|
UseFhbAutoInst=FALSE
|
| 771 |
|
|
ENDLIST
|
| 772 |
|
|
Used_File_List
|
| 773 |
|
|
ENDUsed_File_List
|
| 774 |
|
|
ENDLIST
|
| 775 |
|
|
ENDLIST
|
| 776 |
|
|
ENDLIST
|
| 777 |
|
|
ENDLIST
|
| 778 |
|
|
LIST AssociatedStimulus
|
| 779 |
|
|
LIST top
|
| 780 |
|
|
VALUE "\stimulus\tb_clk.vhd,tb_hdl"
|
| 781 |
|
|
VALUE "\component\work\tb_top\tb_top.vhd,tb_hdl"
|
| 782 |
|
|
ENDLIST
|
| 783 |
|
|
LIST top_CoreAHBLite_0_CoreAHBLite
|
| 784 |
|
|
VALUE "\component\work\top\CoreAHBLite_0\coreparameters.vhd,tb_hdl"
|
| 785 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
|
| 786 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
|
| 787 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
|
| 788 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
|
| 789 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
|
| 790 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
|
| 791 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
|
| 792 |
|
|
VALUE "\component\work\top\CoreAHBLite_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
|
| 793 |
|
|
ENDLIST
|
| 794 |
|
|
LIST top_CoreUARTapb_0_CoreUARTapb
|
| 795 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\coreparameters.vhd,tb_hdl"
|
| 796 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
|
| 797 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
|
| 798 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
|
| 799 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
|
| 800 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahblapb.vhd,tb_hdl"
|
| 801 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
|
| 802 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
|
| 803 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd,tb_hdl"
|
| 804 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apb.vhd,tb_hdl"
|
| 805 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslave.vhd,tb_hdl"
|
| 806 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd,tb_hdl"
|
| 807 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbtoapb.vhd,tb_hdl"
|
| 808 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
|
| 809 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
|
| 810 |
|
|
ENDLIST
|
| 811 |
|
|
ENDLIST
|
| 812 |
|
|
LIST Other_Association
|
| 813 |
|
|
LIST top
|
| 814 |
|
|
VALUE "\simulation\subsystem.bfm,sim"
|
| 815 |
|
|
ENDLIST
|
| 816 |
|
|
LIST top_CoreAHBLite_0_CoreAHBLite
|
| 817 |
|
|
VALUE "\component\work\top\CoreAHBLite_0\coreparameters.vhd,tb_hdl"
|
| 818 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
|
| 819 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
|
| 820 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
|
| 821 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
|
| 822 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
|
| 823 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
|
| 824 |
|
|
VALUE "\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
|
| 825 |
|
|
VALUE "\component\work\top\CoreAHBLite_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
|
| 826 |
|
|
ENDLIST
|
| 827 |
|
|
LIST top_CoreUARTapb_0_CoreUARTapb
|
| 828 |
|
|
VALUE "\simulation\coreuart_usertb_apb_master.bfm,sim"
|
| 829 |
|
|
VALUE "\simulation\coreuart_usertb_include.bfm,sim"
|
| 830 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\coreparameters.vhd,tb_hdl"
|
| 831 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
|
| 832 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
|
| 833 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
|
| 834 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
|
| 835 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahblapb.vhd,tb_hdl"
|
| 836 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
|
| 837 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
|
| 838 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd,tb_hdl"
|
| 839 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apb.vhd,tb_hdl"
|
| 840 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslave.vhd,tb_hdl"
|
| 841 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd,tb_hdl"
|
| 842 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbtoapb.vhd,tb_hdl"
|
| 843 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
|
| 844 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
|
| 845 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\mti\scripts\bfmtovec_compile.do,do"
|
| 846 |
|
|
VALUE "\component\work\top\CoreUARTapb_0\mti\scripts\wave_vhdl_amba.do,do"
|
| 847 |
|
|
ENDLIST
|
| 848 |
|
|
ENDLIST
|
| 849 |
|
|
LIST SimulationOptions
|
| 850 |
|
|
UseAutomaticDoFile=true
|
| 851 |
|
|
IncludeWaveDo=false
|
| 852 |
|
|
Type=max
|
| 853 |
|
|
RunTime=1000ns
|
| 854 |
|
|
Resolution=1ps
|
| 855 |
|
|
VsimOpt=
|
| 856 |
|
|
EntityName=tb_top
|
| 857 |
|
|
TopInstanceName=_0
|
| 858 |
|
|
DoFileName=
|
| 859 |
|
|
DoFileName2=wave.do
|
| 860 |
|
|
DoFileParams=
|
| 861 |
|
|
DisplayDUTWave=false
|
| 862 |
|
|
LogAllSignals=false
|
| 863 |
|
|
DisablePulseFiltering=false
|
| 864 |
|
|
DumpVCD=false
|
| 865 |
|
|
VCDFileName=power.vcd
|
| 866 |
|
|
VHDL2008=false
|
| 867 |
|
|
Verilog2001=false
|
| 868 |
|
|
SystemVerilog=false
|
| 869 |
|
|
TimeUnit=1
|
| 870 |
|
|
TimeUnitBase=ns
|
| 871 |
|
|
Precision=100
|
| 872 |
|
|
PrecisionBase=ps
|
| 873 |
|
|
ENDLIST
|
| 874 |
|
|
LIST ModelSimLibPath
|
| 875 |
|
|
UseCustomPath=FALSE
|
| 876 |
|
|
LibraryPath=
|
| 877 |
|
|
ENDLIST
|
| 878 |
|
|
LIST GlobalFlowOptions
|
| 879 |
|
|
GenerateHDLAfterSynthesis=FALSE
|
| 880 |
|
|
GenerateHDLAfterPhySynthesis=FALSE
|
| 881 |
|
|
RunDRCAfterSynthesis=FALSE
|
| 882 |
|
|
AutoCheckConstraints=TRUE
|
| 883 |
|
|
UpdateModelSimIni=TRUE
|
| 884 |
|
|
NoIOMode=FALSE
|
| 885 |
|
|
PeriInitStandalone=FALSE
|
| 886 |
|
|
EnableViewDraw=FALSE
|
| 887 |
|
|
UpdateViewDrawIni=TRUE
|
| 888 |
|
|
GenerateHDLFromSchematic=TRUE
|
| 889 |
|
|
VmNetlistFlowOn=FALSE
|
| 890 |
|
|
EnableDesignSeparationOn=FALSE
|
| 891 |
|
|
EnableSETMitigationOn=FALSE
|
| 892 |
|
|
DisplayFanoutLimit=10
|
| 893 |
|
|
AbortFlowOnPDCErrorsOn=TRUE
|
| 894 |
|
|
AbortFlowOnSDCErrorsOn=TRUE
|
| 895 |
|
|
InstantiateInSmartDesign=TRUE
|
| 896 |
|
|
FlashProInputFile=pdb
|
| 897 |
|
|
SmartGenCompileReport=T
|
| 898 |
|
|
ENDLIST
|
| 899 |
|
|
LIST PhySynthesisOptions
|
| 900 |
|
|
ENDLIST
|
| 901 |
|
|
LIST Profiles
|
| 902 |
|
|
NAME="SoftConsole"
|
| 903 |
|
|
FUNCTION="SoftwareIDE"
|
| 904 |
|
|
TOOL="SoftConsole"
|
| 905 |
|
|
LOCATION="eclipse.exe"
|
| 906 |
|
|
PARAM=""
|
| 907 |
|
|
BATCH=0
|
| 908 |
|
|
LICENSE=""
|
| 909 |
|
|
IS32BIT="1"
|
| 910 |
|
|
EndProfile
|
| 911 |
|
|
NAME="Synplify Pro ME"
|
| 912 |
|
|
FUNCTION="Synthesis"
|
| 913 |
|
|
TOOL="Synplify Pro ME"
|
| 914 |
|
|
LOCATION="C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\bin\synplify_pro.exe"
|
| 915 |
|
|
PARAM=""
|
| 916 |
|
|
BATCH=0
|
| 917 |
|
|
LICENSE=""
|
| 918 |
|
|
IS32BIT="1"
|
| 919 |
|
|
EndProfile
|
| 920 |
|
|
NAME="ModelSim ME"
|
| 921 |
|
|
FUNCTION="Simulation"
|
| 922 |
|
|
TOOL="ModelSim"
|
| 923 |
|
|
LOCATION="C:\Microsemi\Libero_SoC_v11.8\Modelsim\win32acoem\modelsim.exe"
|
| 924 |
|
|
PARAM=""
|
| 925 |
|
|
BATCH=0
|
| 926 |
|
|
LICENSE=""
|
| 927 |
|
|
IS32BIT="1"
|
| 928 |
|
|
EndProfile
|
| 929 |
|
|
NAME="FPExpress"
|
| 930 |
|
|
FUNCTION="Program"
|
| 931 |
|
|
TOOL="FlashPro"
|
| 932 |
|
|
LOCATION="C:\Microsemi\Libero_SoC_v11.8\Designer\bin\FPExpress.exe"
|
| 933 |
|
|
PARAM=""
|
| 934 |
|
|
BATCH=0
|
| 935 |
|
|
LICENSE=""
|
| 936 |
|
|
IS32BIT="1"
|
| 937 |
|
|
EndProfile
|
| 938 |
|
|
NAME="Identify Debugger"
|
| 939 |
|
|
FUNCTION="IdentifyDebugger"
|
| 940 |
|
|
TOOL="Identify Debugger"
|
| 941 |
|
|
LOCATION="C:\Microsemi\Libero_SoC_v11.8\Identify\bin\identify_debugger.exe"
|
| 942 |
|
|
PARAM=""
|
| 943 |
|
|
BATCH=0
|
| 944 |
|
|
LICENSE=""
|
| 945 |
|
|
IS32BIT="1"
|
| 946 |
|
|
EndProfile
|
| 947 |
|
|
ENDLIST
|
| 948 |
|
|
LIST ProjectState5.1
|
| 949 |
|
|
LIST "AHBMASTER_FIC::work"
|
| 950 |
|
|
LIST Impl1
|
| 951 |
|
|
LiberoState=Post_Synthesis
|
| 952 |
|
|
ideSYNTHESIS(\synthesis\AHBMASTER_FIC.edn,syn_edn)=StateSuccess
|
| 953 |
|
|
LIST FlowOptions
|
| 954 |
|
|
UsePhySynth=FALSE
|
| 955 |
|
|
UseSynth=TRUE
|
| 956 |
|
|
UseFhbAutoInst=FALSE
|
| 957 |
|
|
ENDLIST
|
| 958 |
|
|
Used_File_List
|
| 959 |
|
|
ENDUsed_File_List
|
| 960 |
|
|
ENDLIST
|
| 961 |
|
|
ENDLIST
|
| 962 |
|
|
LIST "top::work"
|
| 963 |
|
|
LIST Impl1
|
| 964 |
|
|
LiberoState=Post_Synthesis
|
| 965 |
|
|
ideSYNTHESIS(\synthesis\top.edn,syn_edn)=StateSuccess
|
| 966 |
|
|
ideSTIMULUS=StateSuccess
|
| 967 |
|
|
LIST FlowOptions
|
| 968 |
|
|
UsePhySynth=FALSE
|
| 969 |
|
|
UseSynth=TRUE
|
| 970 |
|
|
UseFhbAutoInst=FALSE
|
| 971 |
|
|
ENDLIST
|
| 972 |
|
|
Used_File_List
|
| 973 |
|
|
ENDUsed_File_List
|
| 974 |
|
|
ENDLIST
|
| 975 |
|
|
ENDLIST
|
| 976 |
|
|
LIST "top_CoreAHBLite_0_CoreAHBLite::COREAHBLITE_LIB::top_CoreAHBLite_0_components"
|
| 977 |
|
|
LIST Impl1
|
| 978 |
|
|
ideSTIMULUS=StateSuccess
|
| 979 |
|
|
LIST FlowOptions
|
| 980 |
|
|
UsePhySynth=FALSE
|
| 981 |
|
|
UseSynth=TRUE
|
| 982 |
|
|
UseFhbAutoInst=FALSE
|
| 983 |
|
|
ENDLIST
|
| 984 |
|
|
Used_File_List
|
| 985 |
|
|
ENDUsed_File_List
|
| 986 |
|
|
ENDLIST
|
| 987 |
|
|
ENDLIST
|
| 988 |
|
|
LIST "top_CoreUARTapb_0_CoreUARTapb::COREUARTAPB_LIB::top_CoreUARTapb_0_components"
|
| 989 |
|
|
LIST Impl1
|
| 990 |
|
|
ideSTIMULUS=StateSuccess
|
| 991 |
|
|
LIST FlowOptions
|
| 992 |
|
|
UsePhySynth=FALSE
|
| 993 |
|
|
UseSynth=TRUE
|
| 994 |
|
|
UseFhbAutoInst=FALSE
|
| 995 |
|
|
ENDLIST
|
| 996 |
|
|
Used_File_List
|
| 997 |
|
|
ENDUsed_File_List
|
| 998 |
|
|
ENDLIST
|
| 999 |
|
|
ENDLIST
|
| 1000 |
|
|
ENDLIST
|
| 1001 |
|
|
LIST ExcludePackageForSimulation
|
| 1002 |
|
|
ENDLIST
|
| 1003 |
|
|
LIST ExcludePackageForSynthesis
|
| 1004 |
|
|
ENDLIST
|
| 1005 |
|
|
LIST IncludeModuleForSimulation
|
| 1006 |
|
|
ENDLIST
|
| 1007 |
|
|
LIST CDBOrder
|
| 1008 |
|
|
ENDLIST
|
| 1009 |
|
|
LIST UserCustomizedFileList
|
| 1010 |
|
|
ENDLIST
|
| 1011 |
|
|
LIST OpenedFileList
|
| 1012 |
|
|
ORIENTATION;HORIZONTAL
|
| 1013 |
|
|
Reports;Reports;0
|
| 1014 |
|
|
ReportsCurrentItem;Synthesize:synplify.log
|
| 1015 |
|
|
SmartDesign;top;0
|
| 1016 |
|
|
HDL;hdl\AHBMASTER_FIC.vhd;0
|
| 1017 |
|
|
SmartDesign;tb_top;0
|
| 1018 |
|
|
StartPage;StartPage;0
|
| 1019 |
|
|
ACTIVEVIEW;top
|
| 1020 |
|
|
ENDLIST
|
| 1021 |
|
|
LIST ModuleSubBlockList
|
| 1022 |
|
|
LIST "AHBMASTER_FIC::work","hdl\AHBMASTER_FIC.vhd","FALSE","FALSE"
|
| 1023 |
|
|
ENDLIST
|
| 1024 |
|
|
LIST "CoreAHB2APB::work","component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd","FALSE","FALSE"
|
| 1025 |
|
|
ENDLIST
|
| 1026 |
|
|
LIST "CoreAPB::work","component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd","FALSE","FALSE"
|
| 1027 |
|
|
SUBBLOCK "CoreAPB_L::work","component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\MuxP2B.vhd","FALSE","FALSE"
|
| 1028 |
|
|
ENDLIST
|
| 1029 |
|
|
LIST "CoreAPB_L::work","component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\MuxP2B.vhd","FALSE","FALSE"
|
| 1030 |
|
|
ENDLIST
|
| 1031 |
|
|
LIST "DESIGN_FIRMWARE::work","component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf","TRUE","FALSE"
|
| 1032 |
|
|
ENDLIST
|
| 1033 |
|
|
LIST "DESIGN_IO::work","component\work\DESIGN_IO\DESIGN_IO.cxf","TRUE","FALSE"
|
| 1034 |
|
|
ENDLIST
|
| 1035 |
|
|
LIST "top::work","component\work\top\top.vhd","TRUE","FALSE"
|
| 1036 |
|
|
SUBBLOCK "AHBMASTER_FIC::work","hdl\AHBMASTER_FIC.vhd","FALSE","FALSE"
|
| 1037 |
|
|
SUBBLOCK "CoreAHB2APB::work","component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd","FALSE","FALSE"
|
| 1038 |
|
|
SUBBLOCK "CoreAPB::work","component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd","FALSE","FALSE"
|
| 1039 |
|
|
SUBBLOCK "top_CoreAHBLite_0_CoreAHBLite::COREAHBLITE_LIB::top_CoreAHBLite_0_components","component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd","FALSE","FALSE"
|
| 1040 |
|
|
SUBBLOCK "top_CoreUARTapb_0_CoreUARTapb::COREUARTAPB_LIB::top_CoreUARTapb_0_components","component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd","FALSE","FALSE"
|
| 1041 |
|
|
ENDLIST
|
| 1042 |
|
|
LIST "tb_clk::work","stimulus\tb_clk.vhd","FALSE","TRUE"
|
| 1043 |
|
|
ENDLIST
|
| 1044 |
|
|
LIST "tb_top::work","component\work\tb_top\tb_top.vhd","TRUE","TRUE"
|
| 1045 |
|
|
SUBBLOCK "tb_clk::work","stimulus\tb_clk.vhd","FALSE","TRUE"
|
| 1046 |
|
|
SUBBLOCK "top::work","component\work\top\top.vhd","TRUE","FALSE"
|
| 1047 |
|
|
ENDLIST
|
| 1048 |
|
|
LIST "COREAHBLITE_ADDRDEC::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_addrdec.vhd","FALSE","FALSE"
|
| 1049 |
|
|
ENDLIST
|
| 1050 |
|
|
LIST "COREAHBLITE_DEFAULTSLAVESM::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_defaultslavesm.vhd","FALSE","FALSE"
|
| 1051 |
|
|
ENDLIST
|
| 1052 |
|
|
LIST "COREAHBLITE_MASTERSTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd","FALSE","FALSE"
|
| 1053 |
|
|
SUBBLOCK "COREAHBLITE_ADDRDEC::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_addrdec.vhd","FALSE","FALSE"
|
| 1054 |
|
|
SUBBLOCK "COREAHBLITE_DEFAULTSLAVESM::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_defaultslavesm.vhd","FALSE","FALSE"
|
| 1055 |
|
|
ENDLIST
|
| 1056 |
|
|
LIST "COREAHBLITE_MATRIX4X16::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd","FALSE","FALSE"
|
| 1057 |
|
|
SUBBLOCK "COREAHBLITE_MASTERSTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd","FALSE","FALSE"
|
| 1058 |
|
|
SUBBLOCK "COREAHBLITE_SLAVESTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavestage.vhd","FALSE","FALSE"
|
| 1059 |
|
|
ENDLIST
|
| 1060 |
|
|
LIST "coreahblite_pkg::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_pkg.vhd","FALSE","FALSE"
|
| 1061 |
|
|
ENDLIST
|
| 1062 |
|
|
LIST "COREAHBLITE_SLAVEARBITER::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd","FALSE","FALSE"
|
| 1063 |
|
|
ENDLIST
|
| 1064 |
|
|
LIST "COREAHBLITE_SLAVESTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavestage.vhd","FALSE","FALSE"
|
| 1065 |
|
|
SUBBLOCK "COREAHBLITE_SLAVEARBITER::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd","FALSE","FALSE"
|
| 1066 |
|
|
ENDLIST
|
| 1067 |
|
|
LIST "coreahblite_support::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_addrdec.vhd","FALSE","FALSE"
|
| 1068 |
|
|
ENDLIST
|
| 1069 |
|
|
LIST "top_CoreAHBLite_0_components::COREAHBLITE_LIB","component\work\top\CoreAHBLite_0\rtl\vhdl\core\components.vhd","FALSE","FALSE"
|
| 1070 |
|
|
SUBBLOCK "top_CoreAHBLite_0_CoreAHBLite::COREAHBLITE_LIB::top_CoreAHBLite_0_components","component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd","FALSE","FALSE"
|
| 1071 |
|
|
ENDLIST
|
| 1072 |
|
|
LIST "top_CoreAHBLite_0_CoreAHBLite::COREAHBLITE_LIB::top_CoreAHBLite_0_components","component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd","FALSE","FALSE"
|
| 1073 |
|
|
SUBBLOCK "COREAHBLITE_MATRIX4X16::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd","FALSE","FALSE"
|
| 1074 |
|
|
ENDLIST
|
| 1075 |
|
|
LIST "bfM_Ahbl::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbl.vhd","FALSE","TRUE"
|
| 1076 |
|
|
SUBBLOCK "bfm_Main::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_main.vhd","FALSE","TRUE"
|
| 1077 |
|
|
ENDLIST
|
| 1078 |
|
|
LIST "bfM_ahblAPB::COREAHBLITE_LIB","","FALSE","FALSE"
|
| 1079 |
|
|
ENDLIST
|
| 1080 |
|
|
LIST "BFM_ahbSLAve::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd","FALSE","TRUE"
|
| 1081 |
|
|
SUBBLOCK "Bfm_aHBSlavEEXt::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd","FALSE","TRUE"
|
| 1082 |
|
|
ENDLIST
|
| 1083 |
|
|
LIST "Bfm_aHBSlavEEXt::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd","FALSE","TRUE"
|
| 1084 |
|
|
ENDLIST
|
| 1085 |
|
|
LIST "bfm_APb::COREAHBLITE_LIB","","FALSE","FALSE"
|
| 1086 |
|
|
ENDLIST
|
| 1087 |
|
|
LIST "Bfm_aPB2apb::COREAHBLITE_LIB","","FALSE","FALSE"
|
| 1088 |
|
|
ENDLIST
|
| 1089 |
|
|
LIST "BFM_apbSLAve::COREAHBLITE_LIB","","FALSE","FALSE"
|
| 1090 |
|
|
ENDLIST
|
| 1091 |
|
|
LIST "BFm_apBSLaveEXT::COREAHBLITE_LIB","","FALSE","FALSE"
|
| 1092 |
|
|
ENDLIST
|
| 1093 |
|
|
LIST "bfm_Main::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_main.vhd","FALSE","TRUE"
|
| 1094 |
|
|
ENDLIST
|
| 1095 |
|
|
LIST "bfm_misc::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\misc.vhd","FALSE","TRUE"
|
| 1096 |
|
|
ENDLIST
|
| 1097 |
|
|
LIST "bfM_packAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_package.vhd","FALSE","TRUE"
|
| 1098 |
|
|
SUBBLOCK "BFMA1i1lI::COREAHBLITE_LIB","","FALSE","FALSE"
|
| 1099 |
|
|
SUBBLOCK "BFM_ahbSLAve::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd","FALSE","TRUE"
|
| 1100 |
|
|
SUBBLOCK "BFM_apbSLAve::COREAHBLITE_LIB","","FALSE","FALSE"
|
| 1101 |
|
|
SUBBLOCK "BFm_apBSLaveEXT::COREAHBLITE_LIB","","FALSE","FALSE"
|
| 1102 |
|
|
SUBBLOCK "Bfm_aHBSlavEEXt::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd","FALSE","TRUE"
|
| 1103 |
|
|
SUBBLOCK "Bfm_aPB2apb::COREAHBLITE_LIB","","FALSE","FALSE"
|
| 1104 |
|
|
SUBBLOCK "bfM_Ahbl::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbl.vhd","FALSE","TRUE"
|
| 1105 |
|
|
SUBBLOCK "bfM_ahblAPB::COREAHBLITE_LIB","","FALSE","FALSE"
|
| 1106 |
|
|
SUBBLOCK "bfm_APb::COREAHBLITE_LIB","","FALSE","FALSE"
|
| 1107 |
|
|
SUBBLOCK "bfm_Main::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_main.vhd","FALSE","TRUE"
|
| 1108 |
|
|
ENDLIST
|
| 1109 |
|
|
LIST "bfm_textio::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\textio.vhd","FALSE","TRUE"
|
| 1110 |
|
|
ENDLIST
|
| 1111 |
|
|
LIST "bfm_textio_test::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\textio.vhd","FALSE","TRUE"
|
| 1112 |
|
|
ENDLIST
|
| 1113 |
|
|
LIST "BFMA1i1lI::COREAHBLITE_LIB","","FALSE","FALSE"
|
| 1114 |
|
|
ENDLIST
|
| 1115 |
|
|
LIST "coreparameters::COREAHBLITE_LIB","component\work\top\CoreAHBLite_0\coreparameters.vhd","FALSE","TRUE"
|
| 1116 |
|
|
ENDLIST
|
| 1117 |
|
|
LIST "testbench::COREAHBLITE_LIB","component\work\top\CoreAHBLite_0\rtl\vhdl\test\user\testbench.vhd","FALSE","TRUE"
|
| 1118 |
|
|
SUBBLOCK "bfM_Ahbl::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbl.vhd","FALSE","TRUE"
|
| 1119 |
|
|
SUBBLOCK "BFM_ahbSLAve::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd","FALSE","TRUE"
|
| 1120 |
|
|
SUBBLOCK "top_CoreAHBLite_0_CoreAHBLite::COREAHBLITE_LIB::top_CoreAHBLite_0_components","component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd","FALSE","FALSE"
|
| 1121 |
|
|
ENDLIST
|
| 1122 |
|
|
LIST "top_CoreUARTapb_0_Clock_gen::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd","FALSE","FALSE"
|
| 1123 |
|
|
ENDLIST
|
| 1124 |
|
|
LIST "top_CoreUARTapb_0_components::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\components.vhd","FALSE","FALSE"
|
| 1125 |
|
|
SUBBLOCK "top_CoreUARTapb_0_CoreUARTapb::COREUARTAPB_LIB::top_CoreUARTapb_0_components","component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd","FALSE","FALSE"
|
| 1126 |
|
|
ENDLIST
|
| 1127 |
|
|
LIST "top_CoreUARTapb_0_COREUART::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd","FALSE","FALSE"
|
| 1128 |
|
|
SUBBLOCK "top_CoreUARTapb_0_Clock_gen::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd","FALSE","FALSE"
|
| 1129 |
|
|
SUBBLOCK "top_CoreUARTapb_0_Rx_async::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd","FALSE","FALSE"
|
| 1130 |
|
|
SUBBLOCK "top_CoreUARTapb_0_Tx_async::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd","FALSE","FALSE"
|
| 1131 |
|
|
SUBBLOCK "top_CoreUARTapb_0_fifo_256x8::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\fifo_256x8_pa3.vhd","FALSE","FALSE"
|
| 1132 |
|
|
ENDLIST
|
| 1133 |
|
|
LIST "top_CoreUARTapb_0_coreuart_pkg::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\coreuart_pkg.vhd","FALSE","FALSE"
|
| 1134 |
|
|
ENDLIST
|
| 1135 |
|
|
LIST "top_CoreUARTapb_0_CoreUARTapb::COREUARTAPB_LIB::top_CoreUARTapb_0_components","component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd","FALSE","FALSE"
|
| 1136 |
|
|
SUBBLOCK "top_CoreUARTapb_0_COREUART::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd","FALSE","FALSE"
|
| 1137 |
|
|
ENDLIST
|
| 1138 |
|
|
LIST "top_CoreUARTapb_0_fifo_256x8::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\fifo_256x8_pa3.vhd","FALSE","FALSE"
|
| 1139 |
|
|
SUBBLOCK "top_CoreUARTapb_0_fifo_256x8_pa3::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\fifo_256x8_pa3.vhd","FALSE","FALSE"
|
| 1140 |
|
|
ENDLIST
|
| 1141 |
|
|
LIST "top_CoreUARTapb_0_fifo_256x8_pa3::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\fifo_256x8_pa3.vhd","FALSE","FALSE"
|
| 1142 |
|
|
ENDLIST
|
| 1143 |
|
|
LIST "top_CoreUARTapb_0_Rx_async::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd","FALSE","FALSE"
|
| 1144 |
|
|
ENDLIST
|
| 1145 |
|
|
LIST "top_CoreUARTapb_0_Tx_async::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd","FALSE","FALSE"
|
| 1146 |
|
|
ENDLIST
|
| 1147 |
|
|
LIST "bfm_misc::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\misc.vhd","FALSE","TRUE"
|
| 1148 |
|
|
ENDLIST
|
| 1149 |
|
|
LIST "bfm_textio::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\textio.vhd","FALSE","TRUE"
|
| 1150 |
|
|
ENDLIST
|
| 1151 |
|
|
LIST "bfm_textio_test::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\textio.vhd","FALSE","TRUE"
|
| 1152 |
|
|
ENDLIST
|
| 1153 |
|
|
LIST "coreparameters::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\coreparameters.vhd","FALSE","TRUE"
|
| 1154 |
|
|
ENDLIST
|
| 1155 |
|
|
LIST "testbench::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\test\user\testbench.vhd","FALSE","TRUE"
|
| 1156 |
|
|
SUBBLOCK "top_CoreUARTapb_0_CoreUARTapb::COREUARTAPB_LIB::top_CoreUARTapb_0_components","component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd","FALSE","FALSE"
|
| 1157 |
|
|
SUBBLOCK "top_CoreUARTapb_0_BFM_APB::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apb.vhd","FALSE","TRUE"
|
| 1158 |
|
|
ENDLIST
|
| 1159 |
|
|
LIST "top_CoreUARTapb_0_BFM_AHBL::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbl.vhd","FALSE","TRUE"
|
| 1160 |
|
|
SUBBLOCK "top_CoreUARTapb_0_BFM_MAIN::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd","FALSE","TRUE"
|
| 1161 |
|
|
ENDLIST
|
| 1162 |
|
|
LIST "top_CoreUARTapb_0_BFM_AHBLAPB::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahblapb.vhd","FALSE","TRUE"
|
| 1163 |
|
|
SUBBLOCK "top_CoreUARTapb_0_BFM_MAIN::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd","FALSE","TRUE"
|
| 1164 |
|
|
SUBBLOCK "top_CoreUARTapb_0_BFMA1i1lI::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd","FALSE","TRUE"
|
| 1165 |
|
|
ENDLIST
|
| 1166 |
|
|
LIST "top_CoreUARTapb_0_BFM_AHBSLAVE::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd","FALSE","TRUE"
|
| 1167 |
|
|
SUBBLOCK "top_CoreUARTapb_0_BFM_AHBSLAVEEXt::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd","FALSE","TRUE"
|
| 1168 |
|
|
ENDLIST
|
| 1169 |
|
|
LIST "top_CoreUARTapb_0_BFM_AHBSLAVEEXt::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd","FALSE","TRUE"
|
| 1170 |
|
|
ENDLIST
|
| 1171 |
|
|
LIST "top_CoreUARTapb_0_BFM_APB::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apb.vhd","FALSE","TRUE"
|
| 1172 |
|
|
SUBBLOCK "top_CoreUARTapb_0_BFM_MAIN::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd","FALSE","TRUE"
|
| 1173 |
|
|
SUBBLOCK "top_CoreUARTapb_0_BFMA1i1lI::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd","FALSE","TRUE"
|
| 1174 |
|
|
ENDLIST
|
| 1175 |
|
|
LIST "top_CoreUARTapb_0_BFM_APB2APB::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbtoapb.vhd","FALSE","TRUE"
|
| 1176 |
|
|
ENDLIST
|
| 1177 |
|
|
LIST "top_CoreUARTapb_0_BFM_APBSLAVE::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslave.vhd","FALSE","TRUE"
|
| 1178 |
|
|
SUBBLOCK "top_CoreUARTapb_0_BFM_APBSLAVEEXT::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd","FALSE","TRUE"
|
| 1179 |
|
|
ENDLIST
|
| 1180 |
|
|
LIST "top_CoreUARTapb_0_BFM_APBSLAVEEXT::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd","FALSE","TRUE"
|
| 1181 |
|
|
ENDLIST
|
| 1182 |
|
|
LIST "top_CoreUARTapb_0_BFM_MAIN::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd","FALSE","TRUE"
|
| 1183 |
|
|
ENDLIST
|
| 1184 |
|
|
LIST "top_CoreUARTapb_0_bfM_packAGE::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_package.vhd","FALSE","TRUE"
|
| 1185 |
|
|
SUBBLOCK "top_CoreUARTapb_0_BFMA1i1lI::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd","FALSE","TRUE"
|
| 1186 |
|
|
SUBBLOCK "top_CoreUARTapb_0_BFM_AHBL::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbl.vhd","FALSE","TRUE"
|
| 1187 |
|
|
SUBBLOCK "top_CoreUARTapb_0_BFM_AHBLAPB::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahblapb.vhd","FALSE","TRUE"
|
| 1188 |
|
|
SUBBLOCK "top_CoreUARTapb_0_BFM_AHBSLAVE::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd","FALSE","TRUE"
|
| 1189 |
|
|
SUBBLOCK "top_CoreUARTapb_0_BFM_AHBSLAVEEXt::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd","FALSE","TRUE"
|
| 1190 |
|
|
SUBBLOCK "top_CoreUARTapb_0_BFM_APB::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apb.vhd","FALSE","TRUE"
|
| 1191 |
|
|
SUBBLOCK "top_CoreUARTapb_0_BFM_APB2APB::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbtoapb.vhd","FALSE","TRUE"
|
| 1192 |
|
|
SUBBLOCK "top_CoreUARTapb_0_BFM_APBSLAVE::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslave.vhd","FALSE","TRUE"
|
| 1193 |
|
|
SUBBLOCK "top_CoreUARTapb_0_BFM_APBSLAVEEXT::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd","FALSE","TRUE"
|
| 1194 |
|
|
SUBBLOCK "top_CoreUARTapb_0_BFM_MAIN::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd","FALSE","TRUE"
|
| 1195 |
|
|
ENDLIST
|
| 1196 |
|
|
LIST "top_CoreUARTapb_0_BFMA1i1lI::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd","FALSE","TRUE"
|
| 1197 |
|
|
ENDLIST
|
| 1198 |
|
|
ENDLIST
|
| 1199 |
|
|
LIST ActiveTestBenchList
|
| 1200 |
|
|
LIST "top::work"
|
| 1201 |
|
|
ACTIVETESTBENCH "tb_top::work","component\work\tb_top\tb_top.vhd","TRUE"
|
| 1202 |
|
|
ENDLIST
|
| 1203 |
|
|
LIST "AHBMASTER_FIC::work"
|
| 1204 |
|
|
ACTIVETESTBENCH "tb_top::work","component\work\tb_top\tb_top.cxf","TRUE"
|
| 1205 |
|
|
ENDLIST
|
| 1206 |
|
|
ENDLIST
|
| 1207 |
|
|
LIST IOTabList
|
| 1208 |
|
|
ENDLIST
|
| 1209 |
|
|
LIST FPTabList
|
| 1210 |
|
|
ENDLIST
|
| 1211 |
|
|
LIST TimingTabList
|
| 1212 |
|
|
ENDLIST
|
| 1213 |
|
|
LIST FDCTabList
|
| 1214 |
|
|
ENDLIST
|
