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[/] [aic1106_avalon_ip/] [trunk/] [AIC1106_PCM.v] - Blame information for rev 2

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1 2 AlexO 
module AIC1106_PCM(
2 
        // Avalon clock
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        csi_avalon_clk,
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        csi_reset,
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        // Avalon stream audio clock 2.048 MHz
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        csi_audio_clk,
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         // Control/status reg Avalon slave
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                avs_creg_address,
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                avs_creg_chipselect,
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                avs_creg_write,
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                avs_creg_read,
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                avs_creg_writedata,
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                avs_creg_readdata,
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         // Avalon stream sink
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        asi_data,
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        asi_valid,
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        asi_ready,
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         // Avalon stream source
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        aso_data,
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        aso_valid,
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                        // TLV320AIC1106 signal
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        coe_mclk,
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        coe_pcmsyn,
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        coe_pcmi,
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        coe_pcmo,
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        coe_reset_n,
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        coe_mute,
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        coe_linsel   // always 0 (linear mode)
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         );
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input                   csi_avalon_clk;
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input                   csi_reset;
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input                   csi_audio_clk;
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output   [ 31:0]        avs_creg_readdata;
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input    [  1:0]        avs_creg_address;
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input                   avs_creg_chipselect;
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input                   avs_creg_read;
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input                   avs_creg_write;
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input    [ 31:0]        avs_creg_writedata;
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input    [ 31:0]        asi_data;
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input                   asi_valid;
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output                  asi_ready;
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output                  aso_valid;
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output   [31:0]         aso_data;
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output                  coe_mclk;
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output                  coe_pcmsyn;
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output                  coe_pcmi;
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input                   coe_pcmo;
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output                  coe_reset_n;
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output                  coe_mute;
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output   wire           coe_linsel = 1'b0;  // linear mode
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reg                     enable_r;
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reg                     loopback_r;
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reg                     reset_req_r;
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reg                     pcmsyn_r;
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reg                     mute_r;
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reg                     underflow_r;
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reg      [31:0]         tx_latch_r;
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reg      [31:0]         rx_latch_r;
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reg      [15:0]         tx_shft_r;
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reg      [15:0]         rx_shft_r;
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reg      [2:0]          volume_r;
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reg                     asi_ready_r;
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reg                     aso_valid_r;
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reg                                             reset_r;
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reg      [8:0]          main_cnt;
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wire                    asi_ready = asi_ready_r;
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wire                    aso_valid = aso_valid_r;
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assign                  aso_data[31:0] = rx_latch_r[31:0];
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wire                    coe_mclk = csi_audio_clk & enable_r;
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wire                    coe_pcmsyn = pcmsyn_r & enable_r;
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wire                    coe_pcmi = tx_shft_r[15] & enable_r;
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wire                    coe_mute = mute_r;
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wire                    coe_reset_n = reset_r;//~(reset_req_r | csi_reset);
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wire                    rx_shft_in = (loopback_r)?(coe_pcmi):(coe_pcmo);
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assign                  avs_creg_readdata = (avs_creg_address[1:0] == 2'h0)?(state):(0);
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wire     [31:0]         state = {25'b0, underflow_r, coe_mute, ~coe_reset_n, 1'b0, volume_r[2:0]};
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wire                    creg_reg_sel_w      = avs_creg_write & avs_creg_chipselect & (avs_creg_address[1:0] == 2'h0);
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// NIOS control interface
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always @(posedge csi_avalon_clk or posedge csi_reset)
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begin
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  if (csi_reset)
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  begin
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     reset_req_r <= 0;
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     mute_r <= 0;
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     volume_r[2:0] <= 1;  // 0 db gain
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     loopback_r <= 0;
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         enable_r <= 0;
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  end
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  else if (creg_reg_sel_w)
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  begin
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     volume_r[2:0] <= avs_creg_writedata[2:0];
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     mute_r        <= avs_creg_writedata[3];
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         enable_r      <= avs_creg_writedata[4];
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     loopback_r    <= avs_creg_writedata[5];
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     reset_req_r   <= avs_creg_writedata[6];
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  end
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end
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// PCM state decoder
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wire     fs_avalon_rdy_on   = (main_cnt == 9'd0);
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wire     fs_avalon_rdy_off  = (main_cnt == 9'd1);
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wire     fs_txlatch         = (main_cnt == 9'd2);
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wire     fs_pcmsyn1_on      = (main_cnt == 9'd3);
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wire     fs_pcmsyn1_off     = (main_cnt == 9'd4);
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wire     fs_shift1          = ((main_cnt > 9'd4) && (main_cnt <= 9'd20));
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wire     fs_rxlatch1        = (main_cnt == 9'd21);//21
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wire     fs_pcmsyn2_on      = (main_cnt == 9'd259);
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wire     fs_pcmsyn2_off     = (main_cnt == 9'd260);
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wire     fs_shift2          = ((main_cnt > 9'd260) && (main_cnt <= 9'd276));
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wire     fs_rxlatch2        = (main_cnt == 9'd277);//277
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wire     fs_rxvalid_off     = (main_cnt == 9'd278);
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131 
 
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// PCM receive shift register; clocked by negedge
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always @(negedge csi_audio_clk or posedge reset_req_r)
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begin
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   if (reset_req_r)
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   begin
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      rx_shft_r <= 0;
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   end
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   else begin
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      if (fs_shift1 || fs_shift2)
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      begin
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         rx_shft_r[15:0] <= {rx_shft_r[14:0], rx_shft_in};
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      end
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   end
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end
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// PCM receive path and AVALON stream source logic
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always @(posedge csi_audio_clk or posedge reset_req_r)
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begin
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   if (reset_req_r)
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   begin
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      rx_latch_r <= 0;
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      aso_valid_r <= 0;
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   end
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   else begin
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      if (fs_rxlatch1)
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      begin
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         rx_latch_r[15:0] <= rx_shft_r[15:0];
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      end
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      else if (fs_rxlatch2)
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      begin
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         rx_latch_r[31:16] <= rx_shft_r[15:0];
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         aso_valid_r <= 1;
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      end
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      else if (fs_rxvalid_off)
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      begin
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         aso_valid_r <= 0;
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      end
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   end
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end
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// PCM transmit path and AVALON stream sink logic
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always @(posedge csi_audio_clk or posedge reset_req_r)
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begin
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   if (reset_req_r)
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   begin
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      main_cnt <= 0;
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      underflow_r <= 0;
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      asi_ready_r <= 0;
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      pcmsyn_r <= 0;
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   end
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   else begin
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      main_cnt <= main_cnt + 1'b1;
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      if (fs_avalon_rdy_on)
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      begin
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         asi_ready_r <= 1;
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      end
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      else if (fs_avalon_rdy_off)
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      begin
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         asi_ready_r <= 0;
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      end
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      else if (fs_txlatch)
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      begin
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         if (asi_valid)
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         begin
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            tx_latch_r[31:0] <= asi_data[31:0];
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         end
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         else begin
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            underflow_r <= 1;
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            tx_latch_r[31:0] <= 0;
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         end
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      end
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      else if (fs_pcmsyn1_on)
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      begin
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         pcmsyn_r <= 1;
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         tx_shft_r[15:0] <= {tx_latch_r[12:0], volume_r[2:0]}; //!!
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      end
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      else if (fs_pcmsyn1_off)
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      begin
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         pcmsyn_r <= 0;
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      end
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      else if (fs_shift1)
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      begin
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         tx_shft_r[15:0] <= {tx_shft_r[14:0], 1'b0};
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      end
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      else if (fs_pcmsyn2_on)
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      begin
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         pcmsyn_r <= 1;
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         tx_shft_r[15:0] <= {tx_latch_r[28:16], volume_r[2:0]};   //!!
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      end
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      else if (fs_pcmsyn2_off)
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      begin
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         pcmsyn_r <= 0;
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      end
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      else if (fs_shift2)
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      begin
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         tx_shft_r[15:0] <= {tx_shft_r[14:0], 1'b0};
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      end
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   end
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end
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// resync reset to csi_audio_clk
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always @(posedge csi_audio_clk)
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begin
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        reset_r <= ~(reset_req_r | csi_reset);
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end
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endmodule
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