1 |
11 |
fcorthay |
--##############################################################################
|
2 |
|
|
--
|
3 |
|
|
-- filter_tester
|
4 |
|
|
-- Signal generator for digital lowpass filters testbench
|
5 |
|
|
--
|
6 |
|
|
-- This tester has 2 architectures:
|
7 |
|
|
-- - one providing a step input,
|
8 |
|
|
-- - one generating a sine sweep.
|
9 |
|
|
--
|
10 |
|
|
--------------------------------------------------------------------------------
|
11 |
|
|
--
|
12 |
|
|
-- Versions / Authors
|
13 |
|
|
-- 1.1 Francois Corthay logarithmic step for frequency sweep
|
14 |
|
|
-- 1.0 Francois Corthay first implementation
|
15 |
|
|
--
|
16 |
|
|
-- Provided under GNU LGPL licence: <http://www.gnu.org/copyleft/lesser.html>
|
17 |
|
|
--
|
18 |
|
|
-- by the electronics group of "HES-SO//Valais Wallis", in Switzerland:
|
19 |
|
|
-- <http://isi.hevs.ch/switzerland/robust-electronics.html>.
|
20 |
|
|
--
|
21 |
|
|
--------------------------------------------------------------------------------
|
22 |
|
|
--
|
23 |
|
|
-- Usage
|
24 |
|
|
-- The usage can vary from on EDA tool to another. However, it can be
|
25 |
|
|
-- used with a minimal preparation in the standard library "work".
|
26 |
|
|
--
|
27 |
|
|
-- Compile the filter to test and the filter tester (see
|
28 |
|
|
-- "filter_tester.vhd").
|
29 |
|
|
--
|
30 |
|
|
-- Choose the test architecture: comment-out the other or rely on the
|
31 |
|
|
-- possibilities of your EDA tool.
|
32 |
|
|
--
|
33 |
|
|
-- Compile and continue with the testbench "filter_tb.vhd".
|
34 |
|
|
--
|
35 |
|
|
--##############################################################################
|
36 |
|
|
|
37 |
|
|
LIBRARY ieee;
|
38 |
|
|
USE ieee.std_logic_1164.all;
|
39 |
|
|
USE ieee.numeric_std.ALL;
|
40 |
|
|
|
41 |
|
|
ENTITY filter_tester IS
|
42 |
|
|
GENERIC(
|
43 |
|
|
inputBitNb : positive := 16;
|
44 |
|
|
outputBitNb : positive := 16;
|
45 |
|
|
shiftBitNb : positive := 16
|
46 |
|
|
);
|
47 |
|
|
PORT(
|
48 |
|
|
reset : OUT std_ulogic;
|
49 |
|
|
clock : OUT std_ulogic;
|
50 |
|
|
en : OUT std_ulogic;
|
51 |
|
|
filterIn : OUT signed (inputBitNb-1 DOWNTO 0);
|
52 |
|
|
filterOut : IN signed (outputBitNb-1 DOWNTO 0)
|
53 |
|
|
);
|
54 |
|
|
END filter_tester ;
|
55 |
|
|
|
56 |
|
|
|
57 |
|
|
--==============================================================================
|
58 |
|
|
|
59 |
|
|
ARCHITECTURE step OF filter_tester IS
|
60 |
|
|
|
61 |
|
|
constant clockFrequency: real := 66.0E6;
|
62 |
|
|
constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
|
63 |
|
|
signal sClock: std_uLogic := '1';
|
64 |
|
|
|
65 |
|
|
constant enablePeriod: positive := 10;
|
66 |
|
|
signal sEn: std_uLogic;
|
67 |
|
|
|
68 |
|
|
constant stepPeriod: time := 10000 * enablePeriod * clockPeriod;
|
69 |
|
|
signal filterIn_int: integer;
|
70 |
|
|
|
71 |
|
|
BEGIN
|
72 |
|
|
------------------------------------------------------------------------------
|
73 |
|
|
-- clock and reset
|
74 |
|
|
sClock <= not sClock after clockPeriod/2;
|
75 |
|
|
clock <= transport sClock after clockPeriod*9/10;
|
76 |
|
|
reset <= '1', '0' after 2*clockPeriod;
|
77 |
|
|
|
78 |
|
|
------------------------------------------------------------------------------
|
79 |
|
|
-- enable signal
|
80 |
|
|
process
|
81 |
|
|
begin
|
82 |
|
|
sEn <= '0';
|
83 |
|
|
for index in 1 to (enablePeriod-1) loop
|
84 |
|
|
wait until rising_edge(sClock);
|
85 |
|
|
end loop;
|
86 |
|
|
sEn <= '1';
|
87 |
|
|
wait until rising_edge(sClock);
|
88 |
|
|
end process;
|
89 |
|
|
|
90 |
|
|
en <= sEn;
|
91 |
|
|
|
92 |
|
|
------------------------------------------------------------------------------
|
93 |
|
|
-- time signal
|
94 |
|
|
filterIn <= (others => '0'),
|
95 |
|
|
(filterIn'high => '0', others => '1') after 0.1*stepPeriod,
|
96 |
|
|
(filterIn'high => '1', others => '0') after 1.1*stepPeriod;
|
97 |
|
|
|
98 |
|
|
END ARCHITECTURE step;
|
99 |
|
|
|
100 |
|
|
--==============================================================================
|
101 |
|
|
|
102 |
|
|
library ieee;
|
103 |
|
|
use ieee.math_real.all;
|
104 |
|
|
|
105 |
|
|
ARCHITECTURE sweep OF filter_tester IS
|
106 |
|
|
|
107 |
|
|
constant clockFrequency: real := 66.0E6;
|
108 |
|
|
constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
|
109 |
|
|
signal sClock: std_uLogic := '1';
|
110 |
|
|
|
111 |
|
|
constant enablePeriod: positive := 4;
|
112 |
|
|
signal sEn: std_uLogic := '0';
|
113 |
|
|
|
114 |
|
|
constant minFrequencyLog: real := 3.0;
|
115 |
|
|
constant maxFrequencyLog: real := 5.0;
|
116 |
|
|
constant frequencyStepLog: real := 1.0/5.0;
|
117 |
|
|
constant frequencyStepPeriod: time := 1.0 * (1.0/(10.0**minFrequencyLog)) * 1 sec;
|
118 |
|
|
signal tReal: real := 0.0;
|
119 |
|
|
signal phase: real := 0.0;
|
120 |
|
|
signal sineFrequency: real;
|
121 |
|
|
signal outAmplitude: real := 1.0;
|
122 |
|
|
signal outReal: real := 0.0;
|
123 |
|
|
signal outSigned: signed(filterIn'range);
|
124 |
|
|
|
125 |
|
|
BEGIN
|
126 |
|
|
------------------------------------------------------------------------------
|
127 |
|
|
-- clock and reset
|
128 |
|
|
sClock <= not sClock after clockPeriod/2;
|
129 |
|
|
clock <= transport sClock after clockPeriod*9/10;
|
130 |
|
|
reset <= '1', '0' after 2*clockPeriod;
|
131 |
|
|
|
132 |
|
|
------------------------------------------------------------------------------
|
133 |
|
|
-- enable signal
|
134 |
|
|
process
|
135 |
|
|
begin
|
136 |
|
|
sEn <= '0';
|
137 |
|
|
for index in 1 to (enablePeriod-1) loop
|
138 |
|
|
wait until rising_edge(sClock);
|
139 |
|
|
end loop;
|
140 |
|
|
sEn <= '1';
|
141 |
|
|
wait until rising_edge(sClock);
|
142 |
|
|
end process;
|
143 |
|
|
|
144 |
|
|
en <= sEn;
|
145 |
|
|
|
146 |
|
|
------------------------------------------------------------------------------
|
147 |
|
|
-- frequency sweep
|
148 |
|
|
process
|
149 |
|
|
variable sineFrequencyLog: real;
|
150 |
|
|
begin
|
151 |
|
|
sineFrequencyLog := minFrequencyLog;
|
152 |
|
|
sineFrequency <= 10**sineFrequencyLog;
|
153 |
|
|
while sineFrequencyLog <= maxFrequencyLog loop
|
154 |
|
|
wait for frequencyStepPeriod;
|
155 |
|
|
sineFrequencyLog := sineFrequencyLog + frequencyStepLog;
|
156 |
|
|
sineFrequency <= 10**sineFrequencyLog;
|
157 |
|
|
end loop;
|
158 |
|
|
end process;
|
159 |
|
|
|
160 |
|
|
------------------------------------------------------------------------------
|
161 |
|
|
-- time signals
|
162 |
|
|
process(sClock)
|
163 |
|
|
begin
|
164 |
|
|
if rising_edge(sClock) then
|
165 |
|
|
if sEn = '1' then
|
166 |
|
|
tReal <= tReal + real(enablePeriod)/clockFrequency;
|
167 |
|
|
phase <= phase + 2.0*math_pi*sineFrequency*real(enablePeriod)/clockFrequency;
|
168 |
|
|
end if;
|
169 |
|
|
end if;
|
170 |
|
|
end process;
|
171 |
|
|
|
172 |
|
|
outReal <= outAmplitude * sin(phase);
|
173 |
|
|
|
174 |
|
|
outSigned <= to_signed(
|
175 |
|
|
integer(outReal * ( 2.0**(outSigned'length-1) - 1.0 )),
|
176 |
|
|
outSigned'length
|
177 |
|
|
);
|
178 |
|
|
filterIn <= outSigned;
|
179 |
|
|
|
180 |
|
|
END ARCHITECTURE sweep;
|