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[/] [all_digital_fm_receiver/] [trunk/] [multiplier.vhd] - Blame information for rev 5

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
 
 
ENTITY multiplier IS
-- Declarations
port (CLK       : in  std_logic;
                        RESET   : in  std_logic;
                        input1          : in  std_logic_vector(7 downto 0);
      input2    : in  signed(7 downto 0);
      output    : out signed(7 downto 0)
                );
END multiplier ;
 
 
ARCHITECTURE behavior OF multiplier IS
 
signal out_temp : signed(15 downto 0);
signal input1_buf : signed(15 downto 0);
signal part0, part1, part2, part3, part4, part5, part6, part7 : signed(15 downto 0);
 
begin
 
process(CLK, RESET)
begin
    if (RESET='1') then
        out_temp <= (others => '0');
                output <= (others => '0');
                input1_buf <= (others => '0');
                part0 <= (others => '0');
                part1 <= (others => '0');
                part2 <= (others => '0');
                part3 <= (others => '0');
                part4 <= (others => '0');
                part5 <= (others => '0');
                part6 <= (others => '0');
                part7 <= (others => '0');
                elsif rising_edge(CLK) then
                        input1_buf <= input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&signed(input1);
                        if (input2(0)='1') then
                                part0 <= -(input1_buf);
                                        else
                                                        part0 <= (others => '0');
                        end if;
                        if (input2(1)='1') then
                                if (input2(0)='1') then
                                        part1 <= (others => '0');
                                                else
                                                        part1 <= -(input1_buf);
                                end if;
                                else
                                        if (input2(0)='1') then
                                                part1 <= input1_buf;
                                                        else
                                                                part1 <= (others => '0');
                                        end if;
                        end if;
                        if (input2(2)='1') then
                                if (input2(1)='1') then
                                        part2 <= (others => '0');
                                                else
                                                        part2 <= -(input1_buf);
                                end if;
                                else
                                        if (input2(1)='1') then
                                                part2 <= input1_buf;
                                                        else
                                                                part2 <= (others => '0');
                                        end if;
                        end if;
                        if (input2(3)='1') then
                                if (input2(2)='1') then
                                        part3 <= (others => '0');
                                                else
                                                        part3 <= -(input1_buf);
                                end if;
                                else
                                        if (input2(2)='1') then
                                                part3 <= input1_buf;
                                                        else
                                                                part3 <= (others => '0');
                                        end if;
                        end if;
                        if (input2(4)='1') then
                                if (input2(3)='1') then
                                        part4 <= (others => '0');
                                                else
                                                        part4 <= -(input1_buf);
                                end if;
                                else
                                        if (input2(3)='1') then
                                                part4 <= input1_buf;
                                                        else
                                                                part4 <= (others => '0');
                                        end if;
                        end if;
                        if (input2(5)='1') then
                                if (input2(4)='1') then
                                        part5 <= (others => '0');
                                                else
                                                        part5 <= -(input1_buf);
                                end if;
                                else
                                        if (input2(4)='1') then
                                                part5 <= input1_buf;
                                                        else
                                                                part5 <= (others => '0');
                                        end if;
                        end if;
                        if (input2(6)='1') then
                                if (input2(5)='1') then
                                        part6 <= (others => '0');
                                                else
                                                        part6 <= -(input1_buf);
                                end if;
                                else
                                        if (input2(5)='1') then
                                                part6 <= input1_buf;
                                                        else
                                                                part6 <= (others => '0');
                                        end if;
                        end if;
                        if (input2(7)='1') then
                                if (input2(6)='1') then
                                        part7 <= (others => '0');
                                                else
                                                        part7 <= -(input1_buf);
                                end if;
                                else
                                        if (input2(6)='1') then
                                                part7 <= input1_buf;
                                                        else
                                                                part7 <= (others => '0');
                                        end if;
                        end if;
                out_temp <= part0+(part1(14 downto 0)&'0')+(part2(13 downto 0)&"00")+(part3(12 downto 0)&"000")+(part4(11 downto 0)&"0000")+(part5(10 downto 0)&"00000")+(part6(9 downto 0)&"000000")+(part7(8 downto 0)&"0000000");
                output <= out_temp(15 downto 8);
end if;
end process;
END behavior;
 

Line No.	Rev	Author	Line
1	2	rahmatulla	`LIBRARY ieee;`
2			`USE ieee.std_logic_1164.all;`
3			`USE IEEE.numeric_std.ALL;`
4
5
6			`ENTITY multiplier IS`
7			`-- Declarations`
8			`port (CLK : in std_logic;`
9			`RESET : in std_logic;`
10			`input1 : in std_logic_vector(7 downto 0);`
11			`input2 : in signed(7 downto 0);`
12			`output : out signed(7 downto 0)`
13			`);`
14			`END multiplier ;`
15
16
17			`ARCHITECTURE behavior OF multiplier IS`
18
19			`signal out_temp : signed(15 downto 0);`
20			`signal input1_buf : signed(15 downto 0);`
21			`signal part0, part1, part2, part3, part4, part5, part6, part7 : signed(15 downto 0);`
22
23			`begin`
24
25			`process(CLK, RESET)`
26			`begin`
27			`if (RESET='1') then`
28			`out_temp <= (others => '0');`
29			`output <= (others => '0');`
30			`input1_buf <= (others => '0');`
31			`part0 <= (others => '0');`
32			`part1 <= (others => '0');`
33			`part2 <= (others => '0');`
34			`part3 <= (others => '0');`
35			`part4 <= (others => '0');`
36			`part5 <= (others => '0');`
37			`part6 <= (others => '0');`
38			`part7 <= (others => '0');`
39			`elsif rising_edge(CLK) then`
40			`input1_buf <= input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&signed(input1);`
41			`if (input2(0)='1') then`
42			`part0 <= -(input1_buf);`
43			`else`
44			`part0 <= (others => '0');`
45			`end if;`
46			`if (input2(1)='1') then`
47			`if (input2(0)='1') then`
48			`part1 <= (others => '0');`
49			`else`
50			`part1 <= -(input1_buf);`
51			`end if;`
52			`else`
53			`if (input2(0)='1') then`
54			`part1 <= input1_buf;`
55			`else`
56			`part1 <= (others => '0');`
57			`end if;`
58			`end if;`
59			`if (input2(2)='1') then`
60			`if (input2(1)='1') then`
61			`part2 <= (others => '0');`
62			`else`
63			`part2 <= -(input1_buf);`
64			`end if;`
65			`else`
66			`if (input2(1)='1') then`
67			`part2 <= input1_buf;`
68			`else`
69			`part2 <= (others => '0');`
70			`end if;`
71			`end if;`
72			`if (input2(3)='1') then`
73			`if (input2(2)='1') then`
74			`part3 <= (others => '0');`
75			`else`
76			`part3 <= -(input1_buf);`
77			`end if;`
78			`else`
79			`if (input2(2)='1') then`
80			`part3 <= input1_buf;`
81			`else`
82			`part3 <= (others => '0');`
83			`end if;`
84			`end if;`
85			`if (input2(4)='1') then`
86			`if (input2(3)='1') then`
87			`part4 <= (others => '0');`
88			`else`
89			`part4 <= -(input1_buf);`
90			`end if;`
91			`else`
92			`if (input2(3)='1') then`
93			`part4 <= input1_buf;`
94			`else`
95			`part4 <= (others => '0');`
96			`end if;`
97			`end if;`
98			`if (input2(5)='1') then`
99			`if (input2(4)='1') then`
100			`part5 <= (others => '0');`
101			`else`
102			`part5 <= -(input1_buf);`
103			`end if;`
104			`else`
105			`if (input2(4)='1') then`
106			`part5 <= input1_buf;`
107			`else`
108			`part5 <= (others => '0');`
109			`end if;`
110			`end if;`
111			`if (input2(6)='1') then`
112			`if (input2(5)='1') then`
113			`part6 <= (others => '0');`
114			`else`
115			`part6 <= -(input1_buf);`
116			`end if;`
117			`else`
118			`if (input2(5)='1') then`
119			`part6 <= input1_buf;`
120			`else`
121			`part6 <= (others => '0');`
122			`end if;`
123			`end if;`
124			`if (input2(7)='1') then`
125			`if (input2(6)='1') then`
126			`part7 <= (others => '0');`
127			`else`
128			`part7 <= -(input1_buf);`
129			`end if;`
130			`else`
131			`if (input2(6)='1') then`
132			`part7 <= input1_buf;`
133			`else`
134			`part7 <= (others => '0');`
135			`end if;`
136			`end if;`
137			`out_temp <= part0+(part1(14 downto 0)&'0')+(part2(13 downto 0)&"00")+(part3(12 downto 0)&"000")+(part4(11 downto 0)&"0000")+(part5(10 downto 0)&"00000")+(part6(9 downto 0)&"000000")+(part7(8 downto 0)&"0000000");`
138			`output <= out_temp(15 downto 8);`
139			`end if;`
140			`end process;`
141			`END behavior;`
142

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[/] [all_digital_fm_receiver/] [trunk/] [multiplier.vhd] - Blame information for rev 5