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[/] [alternascope/] [branches/] [Alpha/] [AdcDriver/] [d_Driver_ADC.v] - Blame information for rev 30

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//==================================================================
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// File:    d_Driver_ADC.v
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// Version: 0.01
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Copyright Stephen Pickett
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//   April 28, 2005
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//------------------------------------------------------------------
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// Revisions:
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// Ver 0.01     Apr 28, 2005    Initial Release
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//
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//==================================================================
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module Driver_ADC(
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    CLK_64MHZ, MASTER_RST,
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    TIMESCALE,
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    CLK_ADC, ADC_DATA,
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    DATA_OUT
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    );
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//==================================================================//
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// DEFINITIONS                                                      //
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//==================================================================//
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parameter US1       = 4'd0;
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parameter US2       = 4'd1;
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parameter US4       = 4'd2;
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parameter US8       = 4'd3;
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parameter US16      = 4'd4;
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parameter US32      = 4'd5;
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parameter US64      = 4'd6;
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parameter US128     = 4'd7;
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parameter US512     = 4'd8;
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parameter US1024    = 4'd9;
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parameter US2048    = 4'd10;
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parameter US4096    = 4'd11;
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parameter US8192    = 4'd12;
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parameter US16384   = 4'd13;
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parameter US32768   = 4'd14;
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parameter US65536   = 4'd15;
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parameter US131072  = 4'd16;
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parameter US262144  = 4'd17;
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parameter US524288  = 4'd18;
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parameter US1048576 = 4'd19;
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parameter US2097152 = 4'd20;
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parameter US4194304 = 4'd21;
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parameter US8388608 = 4'd22;
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//==================================================================//
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// VARIABLE DEFINITIONS                                             //
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//==================================================================//
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//----------------------//
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// INPUTS / OUTPUTS     //
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//----------------------//
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input       CLK_64MHZ;          // Global System Clock
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input       MASTER_RST;         // Global Asyncronous Reset
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input[3:0]  TIMESCALE;          // The selected V/Div
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input[8:0]  ADC_DATA;           // Data recieved from ADC
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output      CLK_ADC;            // Clock out to the ADC
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output[8:0] DATA_OUT;           // Data output (essentially buffered from ADC by one clk)
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//----------------------//
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// WIRES / NODES        //
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//----------------------//
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wire CLK_64MHZ, MASTER_RST;
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wire[3:0] TIMESCALE;
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wire[8:0] ADC_DATA;
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reg  CLK_ADC;
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reg [8:0] DATA_OUT;
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//----------------------//
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// VARIABLES            //
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//----------------------//
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reg[15:0] Counter_CLK;
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wire CLK_32MHZ, CLK_16MHZ, CLK_8MHZ, CLK_4MHZ, CLK_2MHZ, CLK_1MHZ, CLK_500KHZ, CLK_250KHZ, CLK_125KHZ,
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     CLK_62KHZ, CLK_31KHZ, CLK_16KHZ, CLK_8KHZ, CLK_4KHZ, CLK_2KHZ, CLK_1KHZ;
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//==================================================================//
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// FUNCTIONAL DEFINITIONS                                           //
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//==================================================================//
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always @ (posedge CLK_ADC or posedge MASTER_RST) begin
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    if(MASTER_RST)  DATA_OUT <= 9'b0;
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    else            DATA_OUT <= ADC_DATA;
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end
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/*
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assign CLK_ADC = CLK_62KHZ;
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*/
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//------------------------------------------------------------------//
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// CLOCK GENERATION AND SELECTION                                   //
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//------------------------------------------------------------------//
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always @ (posedge CLK_64MHZ or posedge MASTER_RST) begin
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    if(MASTER_RST == 1'b1) begin
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        Counter_CLK <= 16'b0;
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    end else begin
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        Counter_CLK <= Counter_CLK + 1;
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    end
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end
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assign CLK_32MHZ    = Counter_CLK[0];
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assign CLK_16MHZ    = Counter_CLK[1];
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assign CLK_8MHZ     = Counter_CLK[2];
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assign CLK_4MHZ     = Counter_CLK[3];
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assign CLK_2MHZ     = Counter_CLK[4];
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assign CLK_1MHZ     = Counter_CLK[5];
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assign CLK_500KHZ   = Counter_CLK[6];
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assign CLK_250KHZ   = Counter_CLK[7];
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assign CLK_125KHZ   = Counter_CLK[8];
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assign CLK_62KHZ    = Counter_CLK[9];
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assign CLK_31KHZ    = Counter_CLK[10];
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assign CLK_16KHZ    = Counter_CLK[11];
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assign CLK_8KHZ     = Counter_CLK[12];
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assign CLK_4KHZ     = Counter_CLK[13];
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assign CLK_2KHZ     = Counter_CLK[14];
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assign CLK_1KHZ     = Counter_CLK[15];
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//assign CLK_500HZ    = Counter_CLK[16];
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always @ (TIMESCALE or MASTER_RST or CLK_64MHZ or CLK_32MHZ or CLK_16MHZ or
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            CLK_8MHZ or CLK_4MHZ or CLK_2MHZ or CLK_1MHZ or CLK_500KHZ or CLK_250KHZ or
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            CLK_125KHZ or CLK_62KHZ or CLK_31KHZ or CLK_16KHZ or CLK_8KHZ or CLK_4KHZ or
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            CLK_2KHZ or CLK_1KHZ) begin
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    if(MASTER_RST == 1'b1) begin
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        CLK_ADC = 1'b0;
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    end else if(TIMESCALE == 4'd0) begin    // 1us/Div, 1samp/pxl
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        CLK_ADC = CLK_64MHZ;
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    end else if(TIMESCALE == 4'd1) begin    // 2us/Div, 2samp/pxl
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        CLK_ADC = CLK_64MHZ;
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    end else if(TIMESCALE == 4'd2) begin    // 4us/Div, 2samp/pxl
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        CLK_ADC = CLK_32MHZ;
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    end else if(TIMESCALE == 4'd3) begin    // 8us/Div, 2samp/pxl
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        CLK_ADC = CLK_16MHZ;
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    end else if(TIMESCALE == 4'd4) begin    // 16us/Div, 2samp/pxl
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        CLK_ADC = CLK_8MHZ;
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    end else if(TIMESCALE == 4'd5) begin    // 32us/Div, 2samp/pxl
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        CLK_ADC = CLK_4MHZ;
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    end else if(TIMESCALE == 4'd6) begin    // 64us/Div, 2samp/pxl
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        CLK_ADC = CLK_2MHZ;
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    end else if(TIMESCALE == 4'd7) begin    // 128us/Div, 2samp/pxl
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        CLK_ADC = CLK_1MHZ;
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    end else if(TIMESCALE == 4'd8) begin    // 256us/Div, 2samp/pxl
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        CLK_ADC = CLK_500KHZ;
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    end else if(TIMESCALE == 4'd9) begin    // 512us/Div, 2samp/pxl
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        CLK_ADC = CLK_250KHZ;
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    end else if(TIMESCALE == 4'd10) begin   //      ...
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        CLK_ADC = CLK_125KHZ;
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    end else if(TIMESCALE == 4'd11) begin
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        CLK_ADC = CLK_62KHZ;
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    end else if(TIMESCALE == 4'd12) begin
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        CLK_ADC = CLK_31KHZ;
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    end else if(TIMESCALE == 4'd13) begin
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        CLK_ADC = CLK_16KHZ;
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    end else if(TIMESCALE == 4'd14) begin
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        CLK_ADC = CLK_8KHZ;
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    end else if(TIMESCALE == 4'd15) begin
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        CLK_ADC = CLK_4KHZ;
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/*
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    end else if(TIMESCALE == 4'd16) begin
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        CLK_ADC = CLK_2KHZ;
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    end else if(TIMESCALE == 4'd17) begin
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        CLK_ADC = CLK_1KHZ;
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//    end else if(TIMESCALE == 4'd18) begin
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//        CLK_ADC = CLK_500HZ;
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    end else if(TIMESCALE == 4'd19) begin
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        CLK_ADC = CLK_US524288;
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    end else if(TIMESCALE == 4'd20) begin
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        CLK_ADC = CLK_US1048576;
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    end else if(TIMESCALE == 4'd21) begin
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        CLK_ADC = CLK_US2097152;
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    end else if(TIMESCALE == 4'd22) begin
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        CLK_ADC = CLK_US4194304;
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    end else if(TIMESCALE == 4'd23) begin
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        CLK_ADC = CLK_US8388608;
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*/
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    end else begin
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        CLK_ADC = 1'b0;
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    end
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end
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  /*
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//------------------------------------------------------------------//
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// ADC DATA READING                                                 //
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//------------------------------------------------------------------//
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always @ (negedge CLK_ADC or posedge MASTER_RST) begin
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    if(MASTER_RST == 1'b1) begin
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        DATA_OUT <= 8'b0;
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    end else begin
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        DATA_OUT <= ADC_DATA;
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    end
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end
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//assign DATA_OUT = ADC_DATA;
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*/
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endmodule
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