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[/] [alternascope/] [branches/] [Alpha/] [VGA/] [d_VGAdriver.v] - Blame information for rev 8

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1 8 smpickett 
//==================================================================//
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// File:    d_VGAdriver.v                                           //
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// Version: 0.0.0.2                                                 //
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -//
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// Copyright (C) Stephen Pickett                                    //
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//   Jun 09, 2005                                                   //
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//                                                                  //
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// This program is free software; you can redistribute it and/or    //
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// modify it under the terms of the GNU General Public License      //
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// as published by the Free Software Foundation; either version 2   //
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// of the License, or (at your option) any later version.           //
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//                                                                  //
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// This program is distributed in the hope that it will be useful,  //
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// but WITHOUT ANY WARRANTY; without even the implied warranty of   //
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the    //
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// GNU General Public License for more details.                     //
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//                                                                  //
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// If you have not received a copy of the GNU General Public License//
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// along with this program; write to:                               //
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//     Free Software Foundation, Inc.,                              //
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//     51 Franklin Street, Fifth Floor,                             //
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//     Boston, MA  02110-1301, USA.                                 //
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//                                                                  //
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//------------------------------------------------------------------//
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// Revisions:                                                       //
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// Ver 0.0.0.1     Apr 28, 2005   Under Development                 //
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//     0.0.0.2     Jun 09, 2005   Cleaning                          //
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//                                                                  //
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//==================================================================//
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31 2 smpickett 
module Driver_VGA(
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    CLK_50MHZ, MASTER_RST,
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    VGA_RAM_DATA, VGA_RAM_ADDR,
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    VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS,
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    VGA_RAM_ACCESS_OK,
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    H_SYNC, V_SYNC, VGA_OUTPUT,
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    XCOORD, YCOORD, ram_vshift,
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    TRIGGER_LEVEL,
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    SHOW_LEVELS
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    );
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42 
//==================================================================//
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// PARAMETER DEFINITIONS                                            //
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//==================================================================//
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parameter P_black   = 3'b000;
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parameter P_yellow  = 3'b110;
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parameter P_cyan    = 3'b011;
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parameter P_green   = 3'b010;
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parameter P_white   = 3'b111;
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51 
//==================================================================//
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// VARIABLE DEFINITIONS                                             //
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//==================================================================//
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//----------------------//
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// INPUTS / OUTPUTS     //
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//----------------------//
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input CLK_50MHZ;                // System wide clock
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input MASTER_RST;               // System wide reset
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output H_SYNC;                  // The H_SYNC timing signal to the VGA monitor
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output V_SYNC;                  // The V_SYNC timing signal to the VGA monitor
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output[2:0]  VGA_OUTPUT;        // The 3-bit VGA output
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input[11:0]  XCOORD, YCOORD;
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input[15:0]  VGA_RAM_DATA;
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output[17:0] VGA_RAM_ADDR;
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output VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
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output VGA_RAM_ACCESS_OK;
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input[8:0] TRIGGER_LEVEL;
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input SHOW_LEVELS;
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70 
output[15:0] ram_vshift;
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72 
 
73 
 
74 
//----------------------//
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// WIRES / NODES        //
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//----------------------//
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reg H_SYNC, V_SYNC;
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reg [2:0]  VGA_OUTPUT;
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wire CLK_50MHZ, MASTER_RST;
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wire[11:0] XCOORD, YCOORD;
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wire[15:0] VGA_RAM_DATA;
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reg[17:0]  VGA_RAM_ADDR;
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reg VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
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reg VGA_RAM_ACCESS_OK;
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wire[8:0] TRIGGER_LEVEL;
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wire SHOW_LEVELS;
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88 
 
89 
//----------------------//
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// REGISTERS            //
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//----------------------//
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reg CLK_25MHZ;      // General system clock for VGA timing
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reg [9:0] hcnt;     // Counter - generates the H_SYNC signal
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reg [9:0] vcnt;     // Counter - counts the H_SYNC pulses to generate V_SYNC signal
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reg[2:0]  vga_out;
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97 
//==================================================================//
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// FUNCTIONAL DEFINITIONS                                           //
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//==================================================================//
100 
 
101 
//------------------------------------------------------------------//
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// CLOCK FUNCTIONS                                                  //
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//------------------------------------------------------------------//
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always @ (posedge CLK_50MHZ or posedge MASTER_RST)
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        if (MASTER_RST == 1'b1)
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            CLK_25MHZ <= 1'b0;
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        else
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            CLK_25MHZ <= ~CLK_25MHZ;
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110 
 
111 
//------------------------------------------------------------------//
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// SYNC TIMING COUNTERS                                             //
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//------------------------------------------------------------------//
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always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
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    if (MASTER_RST == 1'b1) begin
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        hcnt <= 10'd0;
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        vcnt <= 10'd0;
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    end else if (hcnt == 10'd0799) begin
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        hcnt <= 10'd0;
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        if (vcnt == 10'd0520)
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            vcnt <= 10'd0;
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        else
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            vcnt <= vcnt + 1'b1;
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    end else
125 
        hcnt <= hcnt + 1'b1;
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end
127 
 
128 
 
129 
//------------------------------------------------------------------//
130 
// HORIZONTAL SYNC TIMING                                           //
131 
//------------------------------------------------------------------//
132 
always @ (hcnt)
133 
    if (hcnt <= 10'd0095)
134 
        H_SYNC = 1'b0;
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    else
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        H_SYNC = 1'b1;
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138 
 
139 
//------------------------------------------------------------------//
140 
// VERTICAL SYNC TIMING                                             //
141 
//------------------------------------------------------------------//
142 
always @ (vcnt)
143 
    if (vcnt <= 10'd0001)
144 
        V_SYNC = 1'b0;
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    else
146 
        V_SYNC = 1'b1;
147 
 
148 
 
149 
//------------------------------------------------------------------//
150 
// VGA DATA SIGNAL TIMING                                           //
151 
//------------------------------------------------------------------//
152 
always @ (hcnt or vcnt or XCOORD or YCOORD or MASTER_RST or vga_out or SHOW_LEVELS or TRIGGER_LEVEL) begin
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    if(MASTER_RST == 1'b1) begin
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        VGA_OUTPUT = P_black;
155 
    //------------------------------------------------------------------------------//
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    // UNSEEN BORDERS                                                               //
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    end else if( (vcnt <= 10'd30) || (vcnt >= 10'd511) ) begin
158 
        VGA_OUTPUT = P_black;
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    end else if( (hcnt <= 10'd143) || (hcnt >= 10'd784) ) begin
160 
        VGA_OUTPUT = P_black;
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    //------------------------------------------------------------------------------//
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    // MOUSE CURSORS                                                                //
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    end else if(vcnt == (YCOORD+10'd31)) begin
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        VGA_OUTPUT = P_green;
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    end else if(hcnt == (XCOORD+10'd144)) begin
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        VGA_OUTPUT = P_green;
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    //------------------------------------------------------------------------------//
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    // TRIGGER SPRITE         (shows as ------T------ )                             //
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    end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL+10'd31) && hcnt != 10'd700 && hcnt != 10'd702) begin
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        VGA_OUTPUT = P_yellow;
171 8 smpickett 
    end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL-1'b1+10'd31) && hcnt >= 10'd700 && hcnt <= 10'd702) begin
172 2 smpickett 
        VGA_OUTPUT = P_yellow;
173 8 smpickett 
    end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL+1'b1+10'd31) && hcnt == 10'd701) begin
174 2 smpickett 
        VGA_OUTPUT = P_yellow;
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///*
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    //------------------------------------------------------------------------------//
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    // MOVE THE WAVEFORM TO THE 'TOP'                                               //
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    end else if(vga_out != 0 && (vcnt < 10'd431)) begin
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        VGA_OUTPUT = vga_out;
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//*/
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    //------------------------------------------------------------------------------//
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    // TOP, BOTTOM, LEFT AND RIGHT GRID LINES                                       //
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    end else if( vcnt == 10'd031 || vcnt == 10'd431 || vcnt == 10'd510) begin
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        VGA_OUTPUT = P_cyan;
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    end else if( hcnt == 10'd144 || hcnt == 10'd783) begin
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        VGA_OUTPUT = P_cyan;
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    //------------------------------------------------------------------------------//
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    // MIDDLE GRID LINES (dashed at 8pxls)                                          //
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    end else if(vcnt == 10'd231 && hcnt[3] == 1'b1) begin
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        VGA_OUTPUT = P_cyan;
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    end else if((hcnt == 10'd464) && (vcnt <= 10'd431) && (vcnt[3] == 1'b1)) begin
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        VGA_OUTPUT = P_cyan;
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    //------------------------------------------------------------------------------//
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    // OTHER HORIZONTAL LINES (dashed at 4pxls)                                     //
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    end else if((vcnt == 10'd071 || vcnt == 10'd111 || vcnt == 10'd151 || vcnt == 10'd191 || vcnt == 10'd271 || vcnt == 10'd311 || vcnt == 10'd351 || vcnt == 10'd391) && (hcnt[2] == 1'b1)) begin
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        VGA_OUTPUT = P_cyan;
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    //------------------------------------------------------------------------------//
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    // OTHER VERTICAL LINES (dashed at 4pxls)                                       //
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    end else if(((hcnt[5:0] == 6'b010000) && (vcnt <= 10'd431)) && (vcnt[2] == 1'b1)) begin
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        VGA_OUTPUT = P_cyan;
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    //------------------------------------------------------------------------------//
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    // OTHERWISE...                                                                 //
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    end else
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        VGA_OUTPUT = P_black;
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/*
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    //------------------------------------------------------------------------------//
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    // DISPLAY DATA                                                                 //
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    end else if(vcnt >= 10'd431) begin
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        VGA_OUTPUT = P_black;
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    end else begin
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        VGA_OUTPUT = vga_out;
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    end
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*/
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end
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216 
//------------------------------------------------------------------//
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// RAM DATA READING                                                 //
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//------------------------------------------------------------------//
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// on reset, ram_addr = 24 and add 25 on each pxl
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//     row 0: ram_addr = 24 and 25 for each pxl
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//     row 1: ram_addr = 24 and 25 for each pxl
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//       ...
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//     row 15: ram_addr = 24 and 25 for each pxl
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//     row 16: ram_addr = 23 and 25 for each pxl *
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//     row 17: ram_addr = 23 and 25 for each pxl *
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//       ...
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reg[9:0]  ram_hcnt;
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reg[4:0]  ram_vcnt;
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reg[15:0] ram_vshift;
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231 
 
232 
always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
233 
    if(MASTER_RST == 1'b1) begin
234 
        ram_hcnt <= 10'd639;
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    end else if(hcnt >= 10'd143 && hcnt <= 782) begin
236 
        if(ram_hcnt == 10'd639)
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            ram_hcnt <= 10'b0;
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        else
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            ram_hcnt <= ram_hcnt + 1'b1;
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    end else begin
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        ram_hcnt <= 10'd639;
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    end
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end
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245 
always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
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    if(MASTER_RST == 1'b1) begin
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        ram_vshift <= 16'h8000;
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    end else if(vcnt < 10'd31) begin
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        ram_vshift <= 16'h8000;
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    end else if((vcnt >= 10'd31) && (hcnt == 10'd0799)) begin
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        if(ram_vshift == 16'h0001)
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            ram_vshift <= 16'h8000;
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        else
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            ram_vshift <= (ram_vshift >> 1);
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    end else
256 
        ram_vshift <= ram_vshift;
257 
end
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always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
260 
    if(MASTER_RST == 1'b1) begin
261 
        ram_vcnt <= 5'd0;
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    end else if(vcnt < 10'd30) begin
263 
        ram_vcnt <= 5'd0;
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    end else if((vcnt >= 10'd30) && (hcnt == 10'd0799) && (ram_vshift == 16'h0001)) begin
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        if(ram_vcnt == 5'd0)
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            ram_vcnt <= 5'd24;
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        else
268 
            ram_vcnt <= ram_vcnt - 1'b1;
269 
    end else begin
270 
        ram_vcnt <= ram_vcnt;
271 
    end
272 
end
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274 
 
275 
 
276 
always @ (ram_hcnt or ram_vcnt) begin
277 
    VGA_RAM_ADDR = ram_vcnt + (ram_hcnt * 7'd025);
278 
end
279 
 
280 
 
281 
always @ (VGA_RAM_DATA or ram_vshift) begin
282 
    if((VGA_RAM_DATA & ram_vshift) != 16'b0)
283 
        vga_out = P_white;
284 
    else
285 
        vga_out = 3'b0;
286 
end
287 
 
288 
 
289 
always begin
290 
    VGA_RAM_CS = 1'b0;  // #CS
291 
    VGA_RAM_OE = 1'b0;  // #OE
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    VGA_RAM_WE = 1'b1;  // #WE
293 
end
294 
 
295 
 
296 
//------------------------------------------------------------------//
297 
// ALL CLEAR?                                                       //
298 
//------------------------------------------------------------------//
299 
always @ (vcnt) begin
300 
    if(vcnt >= 10'd512 || vcnt < 10'd30)
301 
        VGA_RAM_ACCESS_OK = 1'b1;
302 
    else
303 
        VGA_RAM_ACCESS_OK = 1'b0;
304 
end
305 
 
306 
 
307 
endmodule

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