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[/] [alternascope/] [tags/] [Development/] [VGA/] [d_VgaRamBuffer.v] - Blame information for rev 2

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1 2 smpickett 
//==================================================================
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// File:    d_VgaRamBuffer.v
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// Version: 0.01
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Copyright Stephen Pickett
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//   April 28, 2005
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//------------------------------------------------------------------
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// Revisions:
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// Ver 0.01     Apr 28, 2005    Initial Release
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//
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//==================================================================
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module VGADataBuffer(
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    CLK_50MHZ, MASTER_RST,
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    VGA_RAM_DATA, VGA_RAM_ADDR, VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS,
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    VGA_RAM_ACCESS_OK,
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    ADC_RAM_DATA, ADC_RAM_ADDR, ADC_RAM_CLK,
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    TIME_BASE,
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    TRIG_ADDR, VGA_WRITE_DONE
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    );
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//==================================================================//
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// VARIABLE DEFINITIONS                                             //
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//==================================================================//
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//----------------------//
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// INPUTS / OUTPUTS     //
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//----------------------//
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input CLK_50MHZ;                // System wide clock
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input MASTER_RST;               // System wide reset
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output[15:0] VGA_RAM_DATA;
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output[17:0] VGA_RAM_ADDR;
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output       VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
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input        VGA_RAM_ACCESS_OK;
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input[7:0]   ADC_RAM_DATA;
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output[10:0] ADC_RAM_ADDR;
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output       ADC_RAM_CLK;
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input[5:0] TIME_BASE;
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output      VGA_WRITE_DONE;
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input[10:0] TRIG_ADDR;
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//----------------------//
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// WIRES / NODES        //
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//----------------------//
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wire CLK_50MHZ;                // System wide clock
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wire MASTER_RST;               // System wide reset
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wire[15:0] VGA_RAM_DATA;
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reg[17:0] VGA_RAM_ADDR;
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reg VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
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wire  VGA_RAM_ACCESS_OK;
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wire[7:0] ADC_RAM_DATA;
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reg[10:0] ADC_RAM_ADDR;
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wire ADC_RAM_CLK;
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wire[5:0] TIME_BASE;
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reg VGA_WRITE_DONE;
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wire[10:0] TRIG_ADDR;
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//----------------------//
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// REGISTERS            //
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//----------------------//
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reg[4:0]  vcnt;
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reg[9:0]  hcnt;
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reg[15:0] data_to_ram;
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reg[8:0]  adc_data_scale;
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reg[10:0] TRIG_ADDR_buffered;
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//==================================================================//
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// FUNCTIONAL DEFINITIONS                                           //
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//==================================================================//
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always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
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    if(MASTER_RST == 1'b1) begin
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        vcnt <= 5'd0;
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    end else if(VGA_RAM_ACCESS_OK && hcnt != 10'd640) begin
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        if(vcnt == 5'd24)
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            vcnt <= 5'b0;
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        else
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            vcnt <= vcnt + 1'b1;
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    end else begin
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        vcnt <= 5'd0;
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    end
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end
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always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
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    if(MASTER_RST == 1'b1) begin
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        hcnt <= 10'd0;
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    end else if(VGA_RAM_ACCESS_OK) begin
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        if(hcnt == 10'd640)
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            hcnt <= hcnt;
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        else if(vcnt == 5'd24)
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            hcnt <= hcnt + 1'b1;
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        else
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            hcnt <= hcnt;
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    end else begin
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        hcnt <= 10'b0;
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    end
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end
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/* VGA_WRITE_DONE -> BASED ON hcnt */
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always @ (hcnt) begin
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    if(hcnt == 10'd640)
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        VGA_WRITE_DONE = 1'b1;
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    else
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        VGA_WRITE_DONE = 1'b0;
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end
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/* TRIG_ADDR modified */
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always @ (TRIG_ADDR) begin
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    if(TRIG_ADDR < 10'd320)
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        TRIG_ADDR_buffered = (10'd2048 - 10'd1 - 10'd320) - TRIG_ADDR;
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    else
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        TRIG_ADDR_buffered = TRIG_ADDR;
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end
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118 
 
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always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
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    if(MASTER_RST == 1'b1) begin
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        ADC_RAM_ADDR <= 11'b0;
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    end else if(VGA_RAM_ACCESS_OK) begin
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        if((hcnt == 10'd640) || !(vcnt == 5'd24))
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            ADC_RAM_ADDR <= ADC_RAM_ADDR;
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        else
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            ADC_RAM_ADDR <= ADC_RAM_ADDR + 1'b1;
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    end else begin
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        ADC_RAM_ADDR <= TRIG_ADDR_buffered;
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    end
130 
end
131 
 
132 
always @ (ADC_RAM_DATA) begin
133 
    adc_data_scale = ADC_RAM_DATA + (ADC_RAM_DATA>>1);
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end
135 
 
136 
 
137 
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
138 
    if(MASTER_RST == 1'b1) begin
139 
        VGA_RAM_ADDR <= 18'b0;
140 
    end else if(VGA_RAM_ACCESS_OK) begin
141 
        if(hcnt == 10'd640)
142 
            VGA_RAM_ADDR <= VGA_RAM_ADDR;
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        else
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            VGA_RAM_ADDR <= VGA_RAM_ADDR + 1'b1;
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    end else begin
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        VGA_RAM_ADDR <= 18'b0;
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    end
148 
end
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/*
150 
always @ (vcnt or VGA_RAM_ACCESS_OK or adc_data_scale) begin
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    if(VGA_RAM_ACCESS_OK) begin
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        if(vcnt == adc_data_scale[8:4]) begin
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            data_to_ram = (adc_data_scale[3:0] == 4'd0)  & 16'h0001 |
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                          (adc_data_scale[3:0] == 4'd1)  & 16'h0002 |
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                          (adc_data_scale[3:0] == 4'd2)  & 16'h0004 |
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                          (adc_data_scale[3:0] == 4'd3)  & 16'h0008 |
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                          (adc_data_scale[3:0] == 4'd4)  & 16'h0010 |
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                          (adc_data_scale[3:0] == 4'd5)  & 16'h0020 |
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                          (adc_data_scale[3:0] == 4'd6)  & 16'h0040 |
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                          (adc_data_scale[3:0] == 4'd7)  & 16'h0080 |
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                          (adc_data_scale[3:0] == 4'd8)  & 16'h0100 |
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                          (adc_data_scale[3:0] == 4'd9)  & 16'h0200 |
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                          (adc_data_scale[3:0] == 4'd10) & 16'h0400 |
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                          (adc_data_scale[3:0] == 4'd11) & 16'h0800 |
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                          (adc_data_scale[3:0] == 4'd12) & 16'h1000 |
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                          (adc_data_scale[3:0] == 4'd13) & 16'h2000 |
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                          (adc_data_scale[3:0] == 4'd14) & 16'h4000 |
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                          (adc_data_scale[3:0] == 4'd15) & 16'h8000;
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        end else begin
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            data_to_ram = 16'b0;
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        end
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    end else begin
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        data_to_ram = 16'bZ;
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    end
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end
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*/
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always @ (vcnt or VGA_RAM_ACCESS_OK or adc_data_scale) begin
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    if(VGA_RAM_ACCESS_OK) begin
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        if(vcnt == adc_data_scale[8:4]) begin
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            if(adc_data_scale[3:0] == 4'd0)
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                data_to_ram = 16'h0001;
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            else if(adc_data_scale[3:0] == 4'd1)
184 
                data_to_ram = 16'h0002;
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            else if(adc_data_scale[3:0] == 4'd2)
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                data_to_ram = 16'h0004;
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            else if(adc_data_scale[3:0] == 4'd3)
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                data_to_ram = 16'h0008;
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            else if(adc_data_scale[3:0] == 4'd4)
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                data_to_ram = 16'h0010;
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            else if(adc_data_scale[3:0] == 4'd5)
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                data_to_ram = 16'h0020;
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            else if(adc_data_scale[3:0] == 4'd6)
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                data_to_ram = 16'h0040;
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            else if(adc_data_scale[3:0] == 4'd7)
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                data_to_ram = 16'h0080;
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            else if(adc_data_scale[3:0] == 4'd8)
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                data_to_ram = 16'h0100;
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            else if(adc_data_scale[3:0] == 4'd9)
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                data_to_ram = 16'h0200;
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            else if(adc_data_scale[3:0] == 4'd10)
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                data_to_ram = 16'h0400;
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            else if(adc_data_scale[3:0] == 4'd11)
204 
                data_to_ram = 16'h0800;
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            else if(adc_data_scale[3:0] == 4'd12)
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                data_to_ram = 16'h1000;
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            else if(adc_data_scale[3:0] == 4'd13)
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                data_to_ram = 16'h2000;
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            else if(adc_data_scale[3:0] == 4'd14)
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                data_to_ram = 16'h4000;
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            else if(adc_data_scale[3:0] == 4'd15)
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                data_to_ram = 16'h8000;
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            else
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                data_to_ram = 16'hFFFF;
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        end else //end bigIF
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            data_to_ram = 16'b0;
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    end else begin
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        data_to_ram = 16'bZ;
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    end
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end
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/*
223 
always @ (vcnt or VGA_RAM_ACCESS_OK or ADC_RAM_DATA) begin
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    if(VGA_RAM_ACCESS_OK) begin
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        if((vcnt[3:0] == ADC_RAM_DATA[7:4]) && vcnt[4] != 1'b1) begin
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            if(ADC_RAM_DATA[3:0] == 4'd0)
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                data_to_ram = 16'h0001;
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            else if(ADC_RAM_DATA[3:0] == 4'd1)
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                data_to_ram = 16'h0002;
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            else if(ADC_RAM_DATA[3:0] == 4'd2)
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                data_to_ram = 16'h0004;
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            else if(ADC_RAM_DATA[3:0] == 4'd3)
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                data_to_ram = 16'h0008;
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            else if(ADC_RAM_DATA[3:0] == 4'd4)
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                data_to_ram = 16'h0010;
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            else if(ADC_RAM_DATA[3:0] == 4'd5)
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                data_to_ram = 16'h0020;
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            else if(ADC_RAM_DATA[3:0] == 4'd6)
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                data_to_ram = 16'h0040;
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            else if(ADC_RAM_DATA[3:0] == 4'd7)
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                data_to_ram = 16'h0080;
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            else if(ADC_RAM_DATA[3:0] == 4'd8)
243 
                data_to_ram = 16'h0100;
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            else if(ADC_RAM_DATA[3:0] == 4'd9)
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                data_to_ram = 16'h0200;
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            else if(ADC_RAM_DATA[3:0] == 4'd10)
247 
                data_to_ram = 16'h0400;
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            else if(ADC_RAM_DATA[3:0] == 4'd11)
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                data_to_ram = 16'h0800;
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            else if(ADC_RAM_DATA[3:0] == 4'd12)
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                data_to_ram = 16'h1000;
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            else if(ADC_RAM_DATA[3:0] == 4'd13)
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                data_to_ram = 16'h2000;
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            else if(ADC_RAM_DATA[3:0] == 4'd14)
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                data_to_ram = 16'h4000;
256 
            else if(ADC_RAM_DATA[3:0] == 4'd15)
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                data_to_ram = 16'h8000;
258 
            else
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                data_to_ram = 16'hFFFF;
260 
        end else //end bigIF
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            data_to_ram = 16'b0;
262 
    end else begin
263 
        data_to_ram = 16'bZ;
264 
    end
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end
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*/
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/*
268 
always @ (vcnt) begin
269 
    if(vcnt == 5'd00 && hcnt <= 10'd319)
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        data_to_ram = 16'h000F;
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    else
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        data_to_ram = 16'b0;
273 
end
274 
*/
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276 
assign ADC_RAM_CLK = CLK_50MHZ;
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278 
assign VGA_RAM_DATA = data_to_ram;
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280 
always begin
281 
    VGA_RAM_OE = 1'b1;
282 
    VGA_RAM_WE = 1'b0;
283 
    VGA_RAM_CS = 1'b0;
284 
end
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endmodule

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