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[/] [alternascope/] [trunk/] [AdcDriver/] [d_Driver_ADCRamBuffer.v] - Blame information for rev 21

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//==================================================================//
// File:    d_Driver_ADCRamBuffer.v                                 //
// Version: X                                                       //
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -//
// Copyright (C) Stephen Pickett                                    //
//   July 15, 2005                                                  //
//                                                                  //
// This program is free software; you can redistribute it and/or    //
// modify it under the terms of the GNU General Public License      //
// as published by the Free Software Foundation; either version 2   //
// of the License, or (at your option) any later version.           //
//                                                                  //
// This program is distributed in the hope that it will be useful,  //
// but WITHOUT ANY WARRANTY; without even the implied warranty of   //
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the    //
// GNU General Public License for more details.                     //
//                                                                  //
// If you have not received a copy of the GNU General Public License//
// along with this program; write to:                               //
//     Free Software Foundation, Inc.,                              //
//     51 Franklin Street, Fifth Floor,                             //
//     Boston, MA  02110-1301, USA.                                 //
//                                                                  //
//------------------------------------------------------------------//
// Revisions:                                                       //
// Ver X          July 15, 2005   Initial Development Release       //
//                                                                  //
//==================================================================//
 
module ADCDataBuffer(
    CLK_64MHZ, MASTER_CLK, MASTER_RST,
    TIME_BASE, TRIGGER_LEVEL, ADC_DATA,
    CLK_ADC,
    SNAP_DATA_EXT, SNAP_ADDR_EXT, SNAP_CLK_EXT,
    sm_adc_ram, triggered
    );
 
//==================================================================//
// PARAMETER DEFINITIONS                                            //
//==================================================================//
parameter ss_fifo_fill      = 2'b00;
parameter ss_fifo_half      = 2'b01;
parameter ss_save_snapshot  = 2'b11;
parameter ss_invalid        = 2'b10;
 
 
 
//==================================================================//
// VARIABLE DEFINITIONS                                             //
//==================================================================//
 
//----------------------//
// INPUTS / OUTPUTS     //
//----------------------//
input       CLK_64MHZ;
input       MASTER_CLK;
input       MASTER_RST;
input[5:0]  TIME_BASE;
input[8:0]  TRIGGER_LEVEL;
input[8:0]  ADC_DATA;
 
output      CLK_ADC;
 
output[8:0] SNAP_DATA_EXT;
input[10:0] SNAP_ADDR_EXT;
input       SNAP_CLK_EXT;
 
output[1:0]sm_adc_ram;
output triggered;
//----------------------//
// WIRES / NODES        //
//----------------------//
wire CLK_64MHZ, MASTER_CLK, MASTER_RST;
wire[5:0]  TIME_BASE;
wire[8:0]  TRIGGER_LEVEL;
wire[8:0]  ADC_DATA;
wire CLK_ADC;
wire[8:0] SNAP_DATA_EXT;
wire[10:0] SNAP_ADDR_EXT;
wire SNAP_CLK_EXT;
 
 
//----------------------//
// VARIABLES            //
//----------------------//
wire[8:0]   data_from_adc;
reg triggered;
reg[1:0]    sm_adc_ram;
reg[10:0]   fifo_addr;
reg[8:0]    data_from_adc_buffered;
reg[10:0]   trig_addr;
wire[8:0]   buf_adc_data;
reg[10:0]   snap_addr, buf_adc_addr;
 
 
 
//==================================================================//
// 'SUB-ROUTINES'                                                   //
//==================================================================//
//------------------------------------------------------------------//
// Instanstiate the ADC                                             //
//------------------------------------------------------------------//
 
Driver_ADC ADC(
    .CLK_64MHZ(CLK_64MHZ),
    .MASTER_RST(MASTER_RST),
    .TIME_BASE(TIME_BASE),
    .CLK_ADC(CLK_ADC),
    .ADC_DATA(ADC_DATA),
    .DATA_OUT(data_from_adc)
    );
 
//------------------------------------------------------------------//
// Initialize the RAMs WE WILL NEED MORE!                           //
//   RAM is structured as follows:                                  //
//     Dual-Access RAM                                              //
//     18kBits -> 2048Bytes + 1Parity/Byte                          //
//     Access A: 8bit + 1parity (ADC_Write)                         //
//     Access B: 8bit + 1parity (Read)                              //
//------------------------------------------------------------------//
wire VCC, GND;
assign VCC = 1'b1;
assign GND = 1'b0;
 
RAMB16_S9_S9 ADC_QuasiFifo_Buffer(
    .DOA(),                     .DOB(buf_adc_data[7:0]),
    .DOPA(),                    .DOPB(buf_adc_data[8]),
    .ADDRA(fifo_addr),          .ADDRB(buf_adc_addr),
    .CLKA(CLK_ADC),             .CLKB(CLK_ADC),
    .DIA(data_from_adc[7:0]),   .DIB(8'b0),
    .DIPA(data_from_adc[8]),    .DIPB(GND),
    .ENA(VCC),                  .ENB(VCC),
    .WEA(VCC),                  .WEB(GND),
    .SSRA(GND),                 .SSRB(GND)
    );
 
RAMB16_S9_S9 ADC_Data_Snapshot(
    .DOA(),                     .DOB(SNAP_DATA_EXT[7:0]),
    .DOPA(),                    .DOPB(SNAP_DATA_EXT[8]),
    .ADDRA(snap_addr),          .ADDRB(SNAP_ADDR_EXT),
    .CLKA(CLK_ADC),             .CLKB(SNAP_CLK_EXT),
    .DIA(buf_adc_data[7:0]),    .DIB(8'b0),
    .DIPA(buf_adc_data[8]),     .DIPB(GND),
    .ENA(VCC),                  .ENB(VCC),
    .WEA(VCC),                  .WEB(GND),
    .SSRA(GND),                 .SSRB(GND)
    );
 
 
//==================================================================//
// FUNCTIONAL DEFINITIONS                                           //
//==================================================================//
 
/* STATE_MACHINE */
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
    if(MASTER_RST)
        sm_adc_ram <= ss_fifo_fill;
    else begin
//        if(sm_adc_ram != ss_fifo_fill || sm_adc_ram != ss_fifo_half || sm_adc_ram != ss_save_snapshot)
//            sm_adc_ram <= ss_fifo_fill;
        if(sm_adc_ram == ss_fifo_fill && triggered)
            sm_adc_ram <= ss_fifo_half;
        else if(sm_adc_ram == ss_fifo_half && (fifo_addr == trig_addr + 11'd1024))
            sm_adc_ram <= ss_save_snapshot;
        else if(sm_adc_ram == ss_save_snapshot && snap_addr == 11'd2047)
            sm_adc_ram <= ss_fifo_fill;
        else if(sm_adc_ram == ss_invalid)
            sm_adc_ram <= ss_fifo_fill;
        else
            sm_adc_ram <= sm_adc_ram;
    end
end
 
/* FIFO ADDR */
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
    if(MASTER_RST)
        fifo_addr <= 11'b0;
    else if(sm_adc_ram == ss_fifo_fill || sm_adc_ram == ss_fifo_half)
        fifo_addr <= fifo_addr + 1;
    else
        fifo_addr <= fifo_addr;
end
 
/* TRIGGER */
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
    if(MASTER_RST)
        data_from_adc_buffered <= 9'b0;
    else
        data_from_adc_buffered <= data_from_adc;
end
 
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
    if(MASTER_RST)
        triggered <= 1'b0;
    else
        triggered <= (data_from_adc_buffered < TRIGGER_LEVEL && data_from_adc >= TRIGGER_LEVEL);
end
 
always @ (posedge triggered or posedge MASTER_RST) begin
    if(MASTER_RST)
        trig_addr <= 11'b0;
    else if(sm_adc_ram == ss_fifo_fill)
        trig_addr <= fifo_addr;
    else
        trig_addr <= trig_addr;
end
 
/* SNAPSHOT */
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
    if(MASTER_RST) begin
        snap_addr <= 11'b0;
        buf_adc_addr <= 11'b0;
    end else if(sm_adc_ram == ss_save_snapshot) begin
        snap_addr <= snap_addr + 1;
        buf_adc_addr <= buf_adc_addr + 1;
    end else begin
        buf_adc_addr <= trig_addr;
        snap_addr <= 11'b0;
    end
end
 
endmodule

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[/] [alternascope/] [trunk/] [AdcDriver/] [d_Driver_ADCRamBuffer.v] - Blame information for rev 21

Line No.	Rev	Author	Line
1	21	smpickett	`//==================================================================//`
2			`// File: d_Driver_ADCRamBuffer.v //`
3			`// Version: X //`
4			`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -//`
5			`// Copyright (C) Stephen Pickett //`
6			`// July 15, 2005 //`
7			`// //`
8			`// This program is free software; you can redistribute it and/or //`
9			`// modify it under the terms of the GNU General Public License //`
10			`// as published by the Free Software Foundation; either version 2 //`
11			`// of the License, or (at your option) any later version. //`
12			`// //`
13			`// This program is distributed in the hope that it will be useful, //`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of //`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //`
16			`// GNU General Public License for more details. //`
17			`// //`
18			`// If you have not received a copy of the GNU General Public License//`
19			`// along with this program; write to: //`
20			`// Free Software Foundation, Inc., //`
21			`// 51 Franklin Street, Fifth Floor, //`
22			`// Boston, MA 02110-1301, USA. //`
23			`// //`
24			`//------------------------------------------------------------------//`
25			`// Revisions: //`
26			`// Ver X July 15, 2005 Initial Development Release //`
27			`// //`
28			`//==================================================================//`
29
30			`module ADCDataBuffer(`
31			`CLK_64MHZ, MASTER_CLK, MASTER_RST,`
32			`TIME_BASE, TRIGGER_LEVEL, ADC_DATA,`
33			`CLK_ADC,`
34			`SNAP_DATA_EXT, SNAP_ADDR_EXT, SNAP_CLK_EXT,`
35			`sm_adc_ram, triggered`
36			`);`
37
38			`//==================================================================//`
39			`// PARAMETER DEFINITIONS //`
40			`//==================================================================//`
41			`parameter ss_fifo_fill = 2'b00;`
42			`parameter ss_fifo_half = 2'b01;`
43			`parameter ss_save_snapshot = 2'b11;`
44			`parameter ss_invalid = 2'b10;`
45
46
47
48			`//==================================================================//`
49			`// VARIABLE DEFINITIONS //`
50			`//==================================================================//`
51
52			`//----------------------//`
53			`// INPUTS / OUTPUTS //`
54			`//----------------------//`
55			`input CLK_64MHZ;`
56			`input MASTER_CLK;`
57			`input MASTER_RST;`
58			`input[5:0] TIME_BASE;`
59			`input[8:0] TRIGGER_LEVEL;`
60			`input[8:0] ADC_DATA;`
61
62			`output CLK_ADC;`
63
64			`output[8:0] SNAP_DATA_EXT;`
65			`input[10:0] SNAP_ADDR_EXT;`
66			`input SNAP_CLK_EXT;`
67
68			`output[1:0]sm_adc_ram;`
69			`output triggered;`
70			`//----------------------//`
71			`// WIRES / NODES //`
72			`//----------------------//`
73			`wire CLK_64MHZ, MASTER_CLK, MASTER_RST;`
74			`wire[5:0] TIME_BASE;`
75			`wire[8:0] TRIGGER_LEVEL;`
76			`wire[8:0] ADC_DATA;`
77			`wire CLK_ADC;`
78			`wire[8:0] SNAP_DATA_EXT;`
79			`wire[10:0] SNAP_ADDR_EXT;`
80			`wire SNAP_CLK_EXT;`
81
82
83			`//----------------------//`
84			`// VARIABLES //`
85			`//----------------------//`
86			`wire[8:0] data_from_adc;`
87			`reg triggered;`
88			`reg[1:0] sm_adc_ram;`
89			`reg[10:0] fifo_addr;`
90			`reg[8:0] data_from_adc_buffered;`
91			`reg[10:0] trig_addr;`
92			`wire[8:0] buf_adc_data;`
93			`reg[10:0] snap_addr, buf_adc_addr;`
94
95
96
97			`//==================================================================//`
98			`// 'SUB-ROUTINES' //`
99			`//==================================================================//`
100			`//------------------------------------------------------------------//`
101			`// Instanstiate the ADC //`
102			`//------------------------------------------------------------------//`
103
104			`Driver_ADC ADC(`
105			`.CLK_64MHZ(CLK_64MHZ),`
106			`.MASTER_RST(MASTER_RST),`
107			`.TIME_BASE(TIME_BASE),`
108			`.CLK_ADC(CLK_ADC),`
109			`.ADC_DATA(ADC_DATA),`
110			`.DATA_OUT(data_from_adc)`
111			`);`
112
113			`//------------------------------------------------------------------//`
114			`// Initialize the RAMs WE WILL NEED MORE! //`
115			`// RAM is structured as follows: //`
116			`// Dual-Access RAM //`
117			`// 18kBits -> 2048Bytes + 1Parity/Byte //`
118			`// Access A: 8bit + 1parity (ADC_Write) //`
119			`// Access B: 8bit + 1parity (Read) //`
120			`//------------------------------------------------------------------//`
121			`wire VCC, GND;`
122			`assign VCC = 1'b1;`
123			`assign GND = 1'b0;`
124
125			`RAMB16_S9_S9 ADC_QuasiFifo_Buffer(`
126			`.DOA(), .DOB(buf_adc_data[7:0]),`
127			`.DOPA(), .DOPB(buf_adc_data[8]),`
128			`.ADDRA(fifo_addr), .ADDRB(buf_adc_addr),`
129			`.CLKA(CLK_ADC), .CLKB(CLK_ADC),`
130			`.DIA(data_from_adc[7:0]), .DIB(8'b0),`
131			`.DIPA(data_from_adc[8]), .DIPB(GND),`
132			`.ENA(VCC), .ENB(VCC),`
133			`.WEA(VCC), .WEB(GND),`
134			`.SSRA(GND), .SSRB(GND)`
135			`);`
136
137			`RAMB16_S9_S9 ADC_Data_Snapshot(`
138			`.DOA(), .DOB(SNAP_DATA_EXT[7:0]),`
139			`.DOPA(), .DOPB(SNAP_DATA_EXT[8]),`
140			`.ADDRA(snap_addr), .ADDRB(SNAP_ADDR_EXT),`
141			`.CLKA(CLK_ADC), .CLKB(SNAP_CLK_EXT),`
142			`.DIA(buf_adc_data[7:0]), .DIB(8'b0),`
143			`.DIPA(buf_adc_data[8]), .DIPB(GND),`
144			`.ENA(VCC), .ENB(VCC),`
145			`.WEA(VCC), .WEB(GND),`
146			`.SSRA(GND), .SSRB(GND)`
147			`);`
148
149
150			`//==================================================================//`
151			`// FUNCTIONAL DEFINITIONS //`
152			`//==================================================================//`
153
154			`/* STATE_MACHINE */`
155			`always @ (posedge CLK_ADC or posedge MASTER_RST) begin`
156			`if(MASTER_RST)`
157			`sm_adc_ram <= ss_fifo_fill;`
158			`else begin`
159			`// if(sm_adc_ram != ss_fifo_fill \|\| sm_adc_ram != ss_fifo_half \|\| sm_adc_ram != ss_save_snapshot)`
160			`// sm_adc_ram <= ss_fifo_fill;`
161			`if(sm_adc_ram == ss_fifo_fill && triggered)`
162			`sm_adc_ram <= ss_fifo_half;`
163			`else if(sm_adc_ram == ss_fifo_half && (fifo_addr == trig_addr + 11'd1024))`
164			`sm_adc_ram <= ss_save_snapshot;`
165			`else if(sm_adc_ram == ss_save_snapshot && snap_addr == 11'd2047)`
166			`sm_adc_ram <= ss_fifo_fill;`
167			`else if(sm_adc_ram == ss_invalid)`
168			`sm_adc_ram <= ss_fifo_fill;`
169			`else`
170			`sm_adc_ram <= sm_adc_ram;`
171			`end`
172			`end`
173
174			`/* FIFO ADDR */`
175			`always @ (posedge CLK_ADC or posedge MASTER_RST) begin`
176			`if(MASTER_RST)`
177			`fifo_addr <= 11'b0;`
178			`else if(sm_adc_ram == ss_fifo_fill \|\| sm_adc_ram == ss_fifo_half)`
179			`fifo_addr <= fifo_addr + 1;`
180			`else`
181			`fifo_addr <= fifo_addr;`
182			`end`
183
184			`/* TRIGGER */`
185			`always @ (posedge CLK_ADC or posedge MASTER_RST) begin`
186			`if(MASTER_RST)`
187			`data_from_adc_buffered <= 9'b0;`
188			`else`
189			`data_from_adc_buffered <= data_from_adc;`
190			`end`
191
192			`always @ (posedge CLK_ADC or posedge MASTER_RST) begin`
193			`if(MASTER_RST)`
194			`triggered <= 1'b0;`
195			`else`
196			`triggered <= (data_from_adc_buffered < TRIGGER_LEVEL && data_from_adc >= TRIGGER_LEVEL);`
197			`end`
198
199			`always @ (posedge triggered or posedge MASTER_RST) begin`
200			`if(MASTER_RST)`
201			`trig_addr <= 11'b0;`
202			`else if(sm_adc_ram == ss_fifo_fill)`
203			`trig_addr <= fifo_addr;`
204			`else`
205			`trig_addr <= trig_addr;`
206			`end`
207
208			`/* SNAPSHOT */`
209			`always @ (posedge CLK_ADC or posedge MASTER_RST) begin`
210			`if(MASTER_RST) begin`
211			`snap_addr <= 11'b0;`
212			`buf_adc_addr <= 11'b0;`
213			`end else if(sm_adc_ram == ss_save_snapshot) begin`
214			`snap_addr <= snap_addr + 1;`
215			`buf_adc_addr <= buf_adc_addr + 1;`
216			`end else begin`
217			`buf_adc_addr <= trig_addr;`
218			`snap_addr <= 11'b0;`
219			`end`
220			`end`
221
222			`endmodule`