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//==================================================================//
// File:    d_Driver_ADCRamBuffer.v                                 //
// Version: X                                                       //
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -//
// Copyright (C) Stephen Pickett                                    //
//   July 15, 2005                                                  //
//                                                                  //
// This program is free software; you can redistribute it and/or    //
// modify it under the terms of the GNU General Public License      //
// as published by the Free Software Foundation; either version 2   //
// of the License, or (at your option) any later version.           //
//                                                                  //
// This program is distributed in the hope that it will be useful,  //
// but WITHOUT ANY WARRANTY; without even the implied warranty of   //
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the    //
// GNU General Public License for more details.                     //
//                                                                  //
// If you have not received a copy of the GNU General Public License//
// along with this program; write to:                               //
//     Free Software Foundation, Inc.,                              //
//     51 Franklin Street, Fifth Floor,                             //
//     Boston, MA  02110-1301, USA.                                 //
//                                                                  //
//------------------------------------------------------------------//
// Revisions:                                                       //
// Ver X          July 15, 2005   Initial Development Release       //
//                                                                  //
//==================================================================//
 
module ADCDataBuffer(
    CLK_64MHZ, MASTER_CLK, MASTER_RST,
    TIMESCALE, TRIGGER_LEVEL, VERT_OFFSET, HORZ_OFFSET,
    ADC_DATA,
    CLK_ADC,
    SNAP_DATA_EXT, SNAP_ADDR_EXT, SNAP_CLK_EXT,
    TRIGGERSTYLE
    );
 
//==================================================================//
// PARAMETER DEFINITIONS                                            //
//==================================================================//
parameter ss_fifo_fill      = 2'b00;
parameter ss_fifo_half      = 2'b01;
parameter ss_save_snapshot  = 2'b11;
parameter ss_invalid        = 2'b10;
 
 
 
//==================================================================//
// VARIABLE DEFINITIONS                                             //
//==================================================================//
 
//----------------------//
// INPUTS / OUTPUTS     //
//----------------------//
input       CLK_64MHZ;
input       MASTER_CLK;
input       MASTER_RST;
input[3:0]  TIMESCALE;
input[10:0]  TRIGGER_LEVEL, VERT_OFFSET, HORZ_OFFSET;
input[8:0]  ADC_DATA;
 
output      CLK_ADC;
 
output[8:0] SNAP_DATA_EXT;
input[10:0] SNAP_ADDR_EXT;
input       SNAP_CLK_EXT;
 
input[1:0] TRIGGERSTYLE;
 
//----------------------//
// WIRES / NODES        //
//----------------------//
wire CLK_64MHZ, MASTER_CLK, MASTER_RST;
wire[3:0]  TIMESCALE;
wire[10:0]  TRIGGER_LEVEL, VERT_OFFSET, HORZ_OFFSET;
wire[8:0]  ADC_DATA;
wire CLK_ADC;
wire[8:0] SNAP_DATA_EXT;
wire[10:0] SNAP_ADDR_EXT;
wire SNAP_CLK_EXT;
wire[1:0] TRIGGERSTYLE;
 
 
//----------------------//
// VARIABLES            //
//----------------------//
wire[8:0]   data_from_adc;
reg triggered;
reg[1:0]    sm_adc_ram;
reg[10:0]   fifo_addr;
reg[8:0]    data_from_adc_buffered;
reg[10:0]   trig_addr;
wire[8:0]   buf_adc_data;
reg[10:0]   snap_addr, buf_adc_addr;
 
 
 
//==================================================================//
// 'SUB-ROUTINES'                                                   //
//==================================================================//
//------------------------------------------------------------------//
// Instanstiate the ADC                                             //
//------------------------------------------------------------------//
 
Driver_ADC ADC(
    .CLK_64MHZ(CLK_64MHZ),
    .MASTER_RST(MASTER_RST),
    .TIMESCALE(TIMESCALE),
    .CLK_ADC(CLK_ADC),
    .ADC_DATA(ADC_DATA),
    .DATA_OUT(data_from_adc)
    );
 
//------------------------------------------------------------------//
// Initialize the RAMs WE WILL NEED MORE!                           //
//   RAM is structured as follows:                                  //
//     Dual-Access RAM                                              //
//     18kBits -> 2048Bytes + 1Parity/Byte                          //
//     Access A: 8bit + 1parity (ADC_Write)                         //
//     Access B: 8bit + 1parity (Read)                              //
//------------------------------------------------------------------//
wire VCC, GND;
assign VCC = 1'b1;
assign GND = 1'b0;
 
// move the following into a more organized area
wire[10:0] vert_adjustment;
assign vert_adjustment = (VERT_OFFSET);
 
RAMB16_S9_S9 ADC_QuasiFifo_Buffer(
    .DOA(),                     .DOB(buf_adc_data[7:0]),
    .DOPA(),                    .DOPB(buf_adc_data[8]),
    .ADDRA(fifo_addr),          .ADDRB(buf_adc_addr),
    .CLKA(CLK_ADC),             .CLKB(CLK_ADC),
    .DIA(data_from_adc[7:0]),   .DIB(8'b0),
    .DIPA(data_from_adc[8]),    .DIPB(GND),
    .ENA(VCC),                  .ENB(VCC),
    .WEA(VCC),                  .WEB(GND),
    .SSRA(GND),                 .SSRB(GND)
    );
 
RAMB16_S9_S9 ADC_Data_Snapshot(
    .DOA(),                                             .DOB(SNAP_DATA_EXT[7:0]),
    .DOPA(),                                            .DOPB(SNAP_DATA_EXT[8]),
    .ADDRA(snap_addr),                                  .ADDRB(SNAP_ADDR_EXT),
    .CLKA(CLK_ADC),                                     .CLKB(SNAP_CLK_EXT),
    .DIA(buf_adc_data[7:0]+vert_adjustment[7:0]),       .DIB(8'b0),   /* VERTICAL OFFSET */
    .DIPA(buf_adc_data[8]+vert_adjustment[8]),          .DIPB(GND),   /* VERTICAL OFFSET */
    .ENA(VCC),                                          .ENB(VCC),
    .WEA(VCC),                                          .WEB(GND),
    .SSRA(GND),                                         .SSRB(GND)
    );
 
 
//==================================================================//
// FUNCTIONAL DEFINITIONS                                           //
//==================================================================//
 
/* STATE_MACHINE */
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
    if(MASTER_RST)
        sm_adc_ram <= ss_fifo_fill;
    else begin
//        if(sm_adc_ram != ss_fifo_fill || sm_adc_ram != ss_fifo_half || sm_adc_ram != ss_save_snapshot)
//            sm_adc_ram <= ss_fifo_fill;
        if(sm_adc_ram == ss_fifo_fill && triggered)
            sm_adc_ram <= ss_fifo_half;
        else if(sm_adc_ram == ss_fifo_half && (fifo_addr == (trig_addr + 11'd1023)))
            sm_adc_ram <= ss_save_snapshot;
        else if(sm_adc_ram == ss_save_snapshot && snap_addr == 11'd2047)
            sm_adc_ram <= ss_fifo_fill;
        else if(sm_adc_ram == ss_invalid)
            sm_adc_ram <= ss_fifo_fill;
        else
            sm_adc_ram <= sm_adc_ram;
    end
end
 
/* FIFO ADDR */
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
    if(MASTER_RST)
        fifo_addr <= 11'b0;
    else if(sm_adc_ram == ss_fifo_fill || sm_adc_ram == ss_fifo_half)
        fifo_addr <= fifo_addr + 1;
    else
        fifo_addr <= fifo_addr;
end
 
/* TRIGGER */
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
    if(MASTER_RST)
        data_from_adc_buffered <= 9'b0;
    else
        data_from_adc_buffered <= data_from_adc;
end
 
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
    if(MASTER_RST)
        triggered <= 1'b0;
    else
        triggered <= (TRIGGERSTYLE == 2'b00) && (data_from_adc_buffered < TRIGGER_LEVEL && data_from_adc >= TRIGGER_LEVEL) || // >=
                     (TRIGGERSTYLE == 2'b01) && (data_from_adc_buffered > TRIGGER_LEVEL && data_from_adc <= TRIGGER_LEVEL);   // <=
end
 
always @ (posedge triggered or posedge MASTER_RST) begin
    if(MASTER_RST)
        trig_addr <= 11'b0;
    else if(sm_adc_ram == ss_fifo_fill)
        trig_addr <= fifo_addr;
    else
        trig_addr <= trig_addr;
end
 
/* SNAPSHOT */
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
    if(MASTER_RST) begin
        snap_addr <= 11'b0;
        buf_adc_addr <= 11'b0;
    end else if(sm_adc_ram == ss_save_snapshot) begin
        snap_addr <= snap_addr + 1;
        buf_adc_addr <= buf_adc_addr + 1;
    end else begin
        buf_adc_addr <= trig_addr - (HORZ_OFFSET-11'd319);        /* HORIZONTAL OFFSET */
        snap_addr <= 11'b0;
    end
end
 
endmodule

Line No.	Rev	Author	Line
1	21	smpickett	`//==================================================================//`
2			`// File: d_Driver_ADCRamBuffer.v //`
3			`// Version: X //`
4			`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -//`
5			`// Copyright (C) Stephen Pickett //`
6			`// July 15, 2005 //`
7			`// //`
8			`// This program is free software; you can redistribute it and/or //`
9			`// modify it under the terms of the GNU General Public License //`
10			`// as published by the Free Software Foundation; either version 2 //`
11			`// of the License, or (at your option) any later version. //`
12			`// //`
13			`// This program is distributed in the hope that it will be useful, //`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of //`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //`
16			`// GNU General Public License for more details. //`
17			`// //`
18			`// If you have not received a copy of the GNU General Public License//`
19			`// along with this program; write to: //`
20			`// Free Software Foundation, Inc., //`
21			`// 51 Franklin Street, Fifth Floor, //`
22			`// Boston, MA 02110-1301, USA. //`
23			`// //`
24			`//------------------------------------------------------------------//`
25			`// Revisions: //`
26			`// Ver X July 15, 2005 Initial Development Release //`
27			`// //`
28			`//==================================================================//`
29
30			`module ADCDataBuffer(`
31			`CLK_64MHZ, MASTER_CLK, MASTER_RST,`
32	27	smpickett	`TIMESCALE, TRIGGER_LEVEL, VERT_OFFSET, HORZ_OFFSET,`
33			`ADC_DATA,`
34	21	smpickett	`CLK_ADC,`
35			`SNAP_DATA_EXT, SNAP_ADDR_EXT, SNAP_CLK_EXT,`
36	27	smpickett	`TRIGGERSTYLE`
37	21	smpickett	`);`
38
39			`//==================================================================//`
40			`// PARAMETER DEFINITIONS //`
41			`//==================================================================//`
42			`parameter ss_fifo_fill = 2'b00;`
43			`parameter ss_fifo_half = 2'b01;`
44			`parameter ss_save_snapshot = 2'b11;`
45			`parameter ss_invalid = 2'b10;`
46
47
48
49			`//==================================================================//`
50			`// VARIABLE DEFINITIONS //`
51			`//==================================================================//`
52
53			`//----------------------//`
54			`// INPUTS / OUTPUTS //`
55			`//----------------------//`
56			`input CLK_64MHZ;`
57			`input MASTER_CLK;`
58			`input MASTER_RST;`
59	27	smpickett	`input[3:0] TIMESCALE;`
60			`input[10:0] TRIGGER_LEVEL, VERT_OFFSET, HORZ_OFFSET;`
61	21	smpickett	`input[8:0] ADC_DATA;`
62
63			`output CLK_ADC;`
64
65			`output[8:0] SNAP_DATA_EXT;`
66			`input[10:0] SNAP_ADDR_EXT;`
67			`input SNAP_CLK_EXT;`
68
69	27	smpickett	`input[1:0] TRIGGERSTYLE;`
70
71	21	smpickett	`//----------------------//`
72			`// WIRES / NODES //`
73			`//----------------------//`
74			`wire CLK_64MHZ, MASTER_CLK, MASTER_RST;`
75	27	smpickett	`wire[3:0] TIMESCALE;`
76			`wire[10:0] TRIGGER_LEVEL, VERT_OFFSET, HORZ_OFFSET;`
77	21	smpickett	`wire[8:0] ADC_DATA;`
78			`wire CLK_ADC;`
79			`wire[8:0] SNAP_DATA_EXT;`
80			`wire[10:0] SNAP_ADDR_EXT;`
81			`wire SNAP_CLK_EXT;`
82	27	smpickett	`wire[1:0] TRIGGERSTYLE;`
83	21	smpickett
84
85			`//----------------------//`
86			`// VARIABLES //`
87			`//----------------------//`
88			`wire[8:0] data_from_adc;`
89			`reg triggered;`
90			`reg[1:0] sm_adc_ram;`
91			`reg[10:0] fifo_addr;`
92			`reg[8:0] data_from_adc_buffered;`
93			`reg[10:0] trig_addr;`
94			`wire[8:0] buf_adc_data;`
95			`reg[10:0] snap_addr, buf_adc_addr;`
96
97
98
99			`//==================================================================//`
100			`// 'SUB-ROUTINES' //`
101			`//==================================================================//`
102			`//------------------------------------------------------------------//`
103			`// Instanstiate the ADC //`
104			`//------------------------------------------------------------------//`
105
106			`Driver_ADC ADC(`
107			`.CLK_64MHZ(CLK_64MHZ),`
108			`.MASTER_RST(MASTER_RST),`
109	27	smpickett	`.TIMESCALE(TIMESCALE),`
110	21	smpickett	`.CLK_ADC(CLK_ADC),`
111			`.ADC_DATA(ADC_DATA),`
112			`.DATA_OUT(data_from_adc)`
113			`);`
114
115			`//------------------------------------------------------------------//`
116			`// Initialize the RAMs WE WILL NEED MORE! //`
117			`// RAM is structured as follows: //`
118			`// Dual-Access RAM //`
119			`// 18kBits -> 2048Bytes + 1Parity/Byte //`
120			`// Access A: 8bit + 1parity (ADC_Write) //`
121			`// Access B: 8bit + 1parity (Read) //`
122			`//------------------------------------------------------------------//`
123			`wire VCC, GND;`
124			`assign VCC = 1'b1;`
125			`assign GND = 1'b0;`
126
127	27	smpickett	`// move the following into a more organized area`
128			`wire[10:0] vert_adjustment;`
129			`assign vert_adjustment = (VERT_OFFSET);`
130
131	21	smpickett	`RAMB16_S9_S9 ADC_QuasiFifo_Buffer(`
132			`.DOA(), .DOB(buf_adc_data[7:0]),`
133			`.DOPA(), .DOPB(buf_adc_data[8]),`
134			`.ADDRA(fifo_addr), .ADDRB(buf_adc_addr),`
135			`.CLKA(CLK_ADC), .CLKB(CLK_ADC),`
136			`.DIA(data_from_adc[7:0]), .DIB(8'b0),`
137			`.DIPA(data_from_adc[8]), .DIPB(GND),`
138			`.ENA(VCC), .ENB(VCC),`
139			`.WEA(VCC), .WEB(GND),`
140			`.SSRA(GND), .SSRB(GND)`
141			`);`
142
143			`RAMB16_S9_S9 ADC_Data_Snapshot(`
144	27	smpickett	`.DOA(), .DOB(SNAP_DATA_EXT[7:0]),`
145			`.DOPA(), .DOPB(SNAP_DATA_EXT[8]),`
146			`.ADDRA(snap_addr), .ADDRB(SNAP_ADDR_EXT),`
147			`.CLKA(CLK_ADC), .CLKB(SNAP_CLK_EXT),`
148			`.DIA(buf_adc_data[7:0]+vert_adjustment[7:0]), .DIB(8'b0), /* VERTICAL OFFSET */`
149			`.DIPA(buf_adc_data[8]+vert_adjustment[8]), .DIPB(GND), /* VERTICAL OFFSET */`
150			`.ENA(VCC), .ENB(VCC),`
151			`.WEA(VCC), .WEB(GND),`
152			`.SSRA(GND), .SSRB(GND)`
153	21	smpickett	`);`
154
155
156			`//==================================================================//`
157			`// FUNCTIONAL DEFINITIONS //`
158			`//==================================================================//`
159
160			`/* STATE_MACHINE */`
161			`always @ (posedge CLK_ADC or posedge MASTER_RST) begin`
162			`if(MASTER_RST)`
163			`sm_adc_ram <= ss_fifo_fill;`
164			`else begin`
165			`// if(sm_adc_ram != ss_fifo_fill \|\| sm_adc_ram != ss_fifo_half \|\| sm_adc_ram != ss_save_snapshot)`
166			`// sm_adc_ram <= ss_fifo_fill;`
167			`if(sm_adc_ram == ss_fifo_fill && triggered)`
168			`sm_adc_ram <= ss_fifo_half;`
169	27	smpickett	`else if(sm_adc_ram == ss_fifo_half && (fifo_addr == (trig_addr + 11'd1023)))`
170	21	smpickett	`sm_adc_ram <= ss_save_snapshot;`
171			`else if(sm_adc_ram == ss_save_snapshot && snap_addr == 11'd2047)`
172			`sm_adc_ram <= ss_fifo_fill;`
173			`else if(sm_adc_ram == ss_invalid)`
174			`sm_adc_ram <= ss_fifo_fill;`
175			`else`
176			`sm_adc_ram <= sm_adc_ram;`
177			`end`
178			`end`
179
180			`/* FIFO ADDR */`
181			`always @ (posedge CLK_ADC or posedge MASTER_RST) begin`
182			`if(MASTER_RST)`
183			`fifo_addr <= 11'b0;`
184			`else if(sm_adc_ram == ss_fifo_fill \|\| sm_adc_ram == ss_fifo_half)`
185			`fifo_addr <= fifo_addr + 1;`
186			`else`
187			`fifo_addr <= fifo_addr;`
188			`end`
189
190			`/* TRIGGER */`
191			`always @ (posedge CLK_ADC or posedge MASTER_RST) begin`
192			`if(MASTER_RST)`
193			`data_from_adc_buffered <= 9'b0;`
194			`else`
195			`data_from_adc_buffered <= data_from_adc;`
196			`end`
197
198			`always @ (posedge CLK_ADC or posedge MASTER_RST) begin`
199			`if(MASTER_RST)`
200			`triggered <= 1'b0;`
201			`else`
202	27	smpickett	`triggered <= (TRIGGERSTYLE == 2'b00) && (data_from_adc_buffered < TRIGGER_LEVEL && data_from_adc >= TRIGGER_LEVEL) \|\| // >=`
203			`(TRIGGERSTYLE == 2'b01) && (data_from_adc_buffered > TRIGGER_LEVEL && data_from_adc <= TRIGGER_LEVEL); // <=`
204	21	smpickett	`end`
205
206			`always @ (posedge triggered or posedge MASTER_RST) begin`
207			`if(MASTER_RST)`
208			`trig_addr <= 11'b0;`
209			`else if(sm_adc_ram == ss_fifo_fill)`
210			`trig_addr <= fifo_addr;`
211			`else`
212			`trig_addr <= trig_addr;`
213			`end`
214
215			`/* SNAPSHOT */`
216			`always @ (posedge CLK_ADC or posedge MASTER_RST) begin`
217			`if(MASTER_RST) begin`
218			`snap_addr <= 11'b0;`
219			`buf_adc_addr <= 11'b0;`
220			`end else if(sm_adc_ram == ss_save_snapshot) begin`
221			`snap_addr <= snap_addr + 1;`
222			`buf_adc_addr <= buf_adc_addr + 1;`
223			`end else begin`
224	27	smpickett	`buf_adc_addr <= trig_addr - (HORZ_OFFSET-11'd319); /* HORIZONTAL OFFSET */`
225	21	smpickett	`snap_addr <= 11'b0;`
226			`end`
227			`end`
228
229			`endmodule`

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[/] [alternascope/] [trunk/] [AdcDriver/] [d_Driver_ADCRamBuffer.v] - Blame information for rev 32