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[/] [alternascope/] [trunk/] [SegDriver/] [d_SegDriver.v] - Blame information for rev 32

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Line No.	Rev	Author	Line
1	2	smpickett	`//==================================================================`
2			`// File: d_MouseDriver.v`
3			`// Version: 0.01`
4			`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
5			`// Copyright Stephen Pickett, Clarke Ellis`
6			`// April 28, 2005`
7			`//------------------------------------------------------------------`
8			`// Revisions:`
9			`// Ver 0.01 Apr 28, 2005 Initial Release`
10			`//`
11			`//==================================================================`
12
13			`module sub_SegDriver(`
14			`CLK_50MHZ, MASTER_RST,`
15			`DATA_IN,`
16			`SEG_OUT, SEG_SEL`
17			`);`
18
19			`//==================================================================//`
20			`// VARIABLE DEFINITIONS //`
21			`//==================================================================//`
22			`//----------------------//`
23			`// INPUTS //`
24			`//----------------------//`
25			`input CLK_50MHZ; // System wide clock`
26			`input MASTER_RST; // System wide reset`
27			`input[15:0] DATA_IN;`
28			`//----------------------//`
29			`// OUTPUTS //`
30			`//----------------------//`
31			`output[6:0] SEG_OUT;`
32			`output[3:0] SEG_SEL;`
33
34			`//----------------------//`
35			`// WIRES / NODES //`
36			`//----------------------//`
37			`wire CLK_50MHZ, MASTER_RST;`
38			`wire[15:0] DATA_IN;`
39			`reg [6:0] SEG_OUT;`
40			`reg [3:0] SEG_SEL;`
41
42			`//----------------------//`
43			`// REGISTERS //`
44			`//----------------------//`
45			`wire[6:0] seg0, seg1, seg2, seg3;`
46			`reg[7:0] clk_390kHz;`
47
48			`//==================================================================//`
49			`// FUNCTIONAL DEFINITIONS //`
50			`//==================================================================//`
51			`always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin`
52			`if(MASTER_RST == 1'b1)`
53			`clk_390kHz <= 8'b0;`
54			`else`
55			`clk_390kHz <= clk_390kHz + 1;`
56			`end`
57
58			`always @ (posedge clk_390kHz[7] or posedge MASTER_RST) begin`
59			`if(MASTER_RST == 1'b1)`
60			`SEG_SEL <= 4'b1110;`
61			`else begin`
62			`SEG_SEL[3:1] <= SEG_SEL[2:0];`
63			`SEG_SEL[0] <= SEG_SEL[3];`
64			`end`
65			`end`
66
67			`always @ (SEG_SEL or seg0 or seg1 or seg2 or seg3) begin`
68			`if(SEG_SEL == 4'b1110)`
69			`SEG_OUT = seg0;`
70			`else if(SEG_SEL == 4'b1101)`
71			`SEG_OUT = seg1;`
72			`else if(SEG_SEL == 4'b1011)`
73			`SEG_OUT = seg2;`
74			`else if(SEG_SEL == 4'b0111)`
75			`SEG_OUT = seg3;`
76			`else`
77			`SEG_OUT = 7'b1111111;`
78			`end`
79
80			`sub_HexSeg sub_seg3( .DATA_IN(DATA_IN[15:12]),`
81			`.SEG_OUT(seg3)`
82			`);`
83			`sub_HexSeg sub_seg2( .DATA_IN(DATA_IN[11:8]),`
84			`.SEG_OUT(seg2)`
85			`);`
86			`sub_HexSeg sub_seg1( .DATA_IN(DATA_IN[7:4]),`
87			`.SEG_OUT(seg1)`
88			`);`
89			`sub_HexSeg sub_seg0( .DATA_IN(DATA_IN[3:0]),`
90			`.SEG_OUT(seg0)`
91			`);`
92
93			`endmodule`
94
95
96
97
98

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[/] [alternascope/] [trunk/] [SegDriver/] [d_SegDriver.v] - Blame information for rev 32