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//==================================================================//
// File:    d_VGAdriver.v                                           //
// Version: 0.0.0.3                                                 //
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -//
// Copyright (C) Stephen Pickett                                    //
//   Jun 09, 2005                                                   //
//                                                                  //
// This program is free software; you can redistribute it and/or    //
// modify it under the terms of the GNU General Public License      //
// as published by the Free Software Foundation; either version 2   //
// of the License, or (at your option) any later version.           //
//                                                                  //
// This program is distributed in the hope that it will be useful,  //
// but WITHOUT ANY WARRANTY; without even the implied warranty of   //
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the    //
// GNU General Public License for more details.                     //
//                                                                  //
// If you have not received a copy of the GNU General Public License//
// along with this program; write to:                               //
//     Free Software Foundation, Inc.,                              //
//     51 Franklin Street, Fifth Floor,                             //
//     Boston, MA  02110-1301, USA.                                 //
//                                                                  //
//------------------------------------------------------------------//
// Revisions:                                                       //
// Ver 0.0.0.1     Apr 28, 2005   Under Development                 //
//     0.0.0.2     Jun 09, 2005   Cleaning                          //
//     0.0.0.3     Jun 10, 2005   Re-structuerd the VCNT and HCNT   //
//                                so they line up with the PXLs.    //
//                                                                  //
//==================================================================//
 
module Driver_VGA(
    CLK_50MHZ, MASTER_RST,
    CLK_VGA,
    VGA_RAM_DATA, VGA_RAM_ADDR,
    VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS,
    VGA_RAM_ACCESS_OK,
    H_SYNC, V_SYNC, VGA_OUTPUT,
    XCOORD, YCOORD,
    TRIGGER_LEVEL,
    SHOW_LEVELS,
    HCNT, VCNT,
    RGB_CHAR
    );
 
//==================================================================//
// PARAMETER DEFINITIONS                                            //
//==================================================================//
parameter P_black   = 3'b000;
parameter P_yellow  = 3'b110;
parameter P_cyan    = 3'b011;
parameter P_green   = 3'b010;
parameter P_white   = 3'b111;
 
//==================================================================//
// VARIABLE DEFINITIONS                                             //
//==================================================================//
//----------------------//
// INPUTS / OUTPUTS     //
//----------------------//
input CLK_50MHZ;                // System wide clock
input MASTER_RST;               // System wide reset
input CLK_VGA;
output H_SYNC;                  // The H_SYNC timing signal to the VGA monitor
output V_SYNC;                  // The V_SYNC timing signal to the VGA monitor
output[2:0]  VGA_OUTPUT;        // The 3-bit VGA output
input[11:0]  XCOORD, YCOORD;
input[15:0]  VGA_RAM_DATA;
output[17:0] VGA_RAM_ADDR;
output VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
output VGA_RAM_ACCESS_OK;
input[8:0] TRIGGER_LEVEL;
input SHOW_LEVELS;
output[9:0] HCNT, VCNT;
input[2:0] RGB_CHAR;
 
 
 
 
//----------------------//
// WIRES / NODES        //
//----------------------//
reg H_SYNC, V_SYNC;
reg [2:0]  VGA_OUTPUT;
wire CLK_50MHZ, MASTER_RST;
wire CLK_VGA;
wire[11:0] XCOORD, YCOORD;
wire[15:0] VGA_RAM_DATA;
reg[17:0]  VGA_RAM_ADDR;
reg VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
reg VGA_RAM_ACCESS_OK;
wire[8:0] TRIGGER_LEVEL;
wire SHOW_LEVELS;
wire[9:0] HCNT, VCNT;
wire[2:0] RGB_CHAR;
 
 
//----------------------//
// REGISTERS            //
//----------------------//
wire CLK_25MHZ = CLK_VGA;
reg [9:0] hcnt;     // Counter - generates the H_SYNC signal
reg [9:0] vcnt;     // Counter - counts the H_SYNC pulses to generate V_SYNC signal
reg[2:0]  vga_out;
 
//==================================================================//
// FUNCTIONAL DEFINITIONS                                           //
//==================================================================//
assign HCNT = hcnt;
assign VCNT = vcnt;
 
 
//------------------------------------------------------------------//
// SYNC TIMING COUNTERS                                             //
//------------------------------------------------------------------//
always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
    if (MASTER_RST == 1'b1) begin
        hcnt <= 10'd0;
        vcnt <= 10'd430;
    end else if (hcnt == 10'd0799) begin
        hcnt <= 10'd0;
        if (vcnt == 10'd0)
            vcnt <= 10'd520;
        else
            vcnt <= vcnt - 1'b1;
    end else
        hcnt <= hcnt + 1'b1;
end
 
 
//------------------------------------------------------------------//
// HORIZONTAL SYNC TIMING                                           //
//------------------------------------------------------------------//
always @ (hcnt)
    if (hcnt >= 10'd656 && hcnt <= 10'd751)
        H_SYNC = 1'b0;
    else
        H_SYNC = 1'b1;
 
 
//------------------------------------------------------------------//
// VERTICAL SYNC TIMING                                             //
//------------------------------------------------------------------//
always @ (vcnt)
    if (vcnt == 10'd430 || vcnt == 10'd429)
        V_SYNC = 1'b0;
    else
        V_SYNC = 1'b1;
 
 
//------------------------------------------------------------------//
// VGA DATA SIGNAL TIMING                                           //
//------------------------------------------------------------------//
always @ (hcnt or vcnt or XCOORD or YCOORD or MASTER_RST or vga_out or SHOW_LEVELS or TRIGGER_LEVEL) begin
    if(MASTER_RST == 1'b1) begin
        VGA_OUTPUT = P_black;
    //------------------------------------------------------------------------------//
    // UNSEEN BORDERS                                                               //
    end else if( (vcnt >= 10'd400) && (vcnt <= 10'd440) ) begin
        VGA_OUTPUT = P_black;
    end else if( (hcnt >= 10'd640) ) begin
        VGA_OUTPUT = P_black;
    //------------------------------------------------------------------------------//
    // MOUSE CURSORS                                                                //
    end else if(vcnt == YCOORD) begin
        VGA_OUTPUT = P_green;
    end else if(hcnt == XCOORD) begin
        VGA_OUTPUT = P_green;
    //------------------------------------------------------------------------------//
    // TRIGGER SPRITE         (shows as ------T------ )                             //
    end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL) && hcnt != 10'd556 && hcnt != 10'd558) begin
        VGA_OUTPUT = P_yellow;
    end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL+1'b1) && hcnt >= 10'd556 && hcnt <= 10'd558) begin
        VGA_OUTPUT = P_yellow;
    end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL-1'b1) && hcnt == 10'd557) begin
        VGA_OUTPUT = P_yellow;
    //------------------------------------------------------------------------------//
    // TOP, BOTTOM, LEFT AND RIGHT GRID LINES                                       //
    end else if(vcnt == 10'd0 || vcnt == 10'd399 || vcnt == 10'd441) begin
        VGA_OUTPUT = P_cyan;
    end else if(hcnt == 10'd0 || hcnt == 10'd639) begin
        VGA_OUTPUT = P_cyan;
    //------------------------------------------------------------------------------//
    // CHARACTER DISPLAY
    end else if(vcnt <= 10'd520 && vcnt >= 10'd441) begin
        VGA_OUTPUT = RGB_CHAR;
    //------------------------------------------------------------------------------//
    // THE WAVEFORM                                                                 //
    end else if(vga_out != 0) begin
        VGA_OUTPUT = vga_out;
    //------------------------------------------------------------------------------//
    // MIDDLE GRID LINES (dashed at 8pxls)                                          //
    end else if(vcnt == 10'd199 && hcnt[3] == 1'b1) begin
        VGA_OUTPUT = P_cyan;
    end else if((hcnt == 10'd319) && (vcnt <= 10'd399) && (vcnt[3] == 1'b1)) begin
        VGA_OUTPUT = P_cyan;
    //------------------------------------------------------------------------------//
    // OTHER HORIZONTAL LINES (dashed at 4pxls)                                     //
    end else if((vcnt == 10'd39 || vcnt == 10'd79 || vcnt == 10'd119 || vcnt == 10'd159 || vcnt == 10'd239 || vcnt == 10'd279 || vcnt == 10'd319 || vcnt == 10'd359) && (hcnt[2] == 1'b1)) begin
        VGA_OUTPUT = P_cyan;
    //------------------------------------------------------------------------------//
    // OTHER VERTICAL LINES (dashed at 4pxls)                                       //
    end else if(((hcnt[5:0] == 6'b111111) && (vcnt <= 10'd399)) && (vcnt[2] == 1'b1)) begin
        VGA_OUTPUT = P_cyan;
    //------------------------------------------------------------------------------//
    // OTHERWISE...                                                                 //
    end else
        VGA_OUTPUT = P_black;
end
 
//------------------------------------------------------------------//
// RAM DATA READING                                                 //
//------------------------------------------------------------------//
// on reset, ram_addr = 24 and add 25 on each pxl
//     row 0: ram_addr = 24 and 25 for each pxl
//     row 1: ram_addr = 24 and 25 for each pxl
//       ...
//     row 15: ram_addr = 24 and 25 for each pxl
//     row 16: ram_addr = 23 and 25 for each pxl *
//     row 17: ram_addr = 23 and 25 for each pxl *
//       ...
reg[4:0]  ram_vcnt;
reg[15:0] ram_vshift;
 
always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
    if(MASTER_RST == 1'b1) begin
        ram_vshift <= 16'h8000;
    end else if(vcnt > 10'd399) begin
        ram_vshift <= 16'h8000;
    end else if(/*(vcnt <= 10'd399) && */(hcnt == 10'd640)) begin
        if(ram_vshift == 16'h0001)
            ram_vshift <= 16'h8000;
        else
            ram_vshift <= (ram_vshift >> 1);
    end else
        ram_vshift <= ram_vshift;
end
 
always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
    if(MASTER_RST == 1'b1) begin
        ram_vcnt <= 5'd24;//5'b0
    end else if(vcnt > 10'd399) begin
        ram_vcnt <= 5'd24;
    end else if(/*(vcnt >= 10'd30) &&*/ (hcnt == 10'd640) && (ram_vshift == 16'h0001)) begin
        if(ram_vcnt == 5'd0)
            ram_vcnt <= 5'd24;
        else
            ram_vcnt <= ram_vcnt - 1'b1;
    end else begin
        ram_vcnt <= ram_vcnt;
    end
end
 
 
 
always @ (hcnt or ram_vcnt) begin
    VGA_RAM_ADDR = ram_vcnt + (hcnt * 7'd25);
//    VGA_RAM_ADDR = vcnt * hcnt;
end
 
 
always @ (VGA_RAM_DATA or ram_vshift) begin
    if((VGA_RAM_DATA & ram_vshift) != 16'b0)
        vga_out = P_white;
    else
        vga_out = 3'b0;
end
 
 
always begin
    VGA_RAM_CS = 1'b0;  // #CS
    VGA_RAM_OE = 1'b0;  // #OE
    VGA_RAM_WE = 1'b1;  // #WE
end
 
 
//------------------------------------------------------------------//
// ALL CLEAR?                                                       //
//------------------------------------------------------------------//
always @ (vcnt) begin
    if(vcnt > 10'd399)
        VGA_RAM_ACCESS_OK = 1'b1;
    else
        VGA_RAM_ACCESS_OK = 1'b0;
end
 
 
endmodule

Line No.	Rev	Author	Line
1	8	smpickett	`//==================================================================//`
2			`// File: d_VGAdriver.v //`
3	14	smpickett	`// Version: 0.0.0.3 //`
4	8	smpickett	`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -//`
5			`// Copyright (C) Stephen Pickett //`
6			`// Jun 09, 2005 //`
7			`// //`
8			`// This program is free software; you can redistribute it and/or //`
9			`// modify it under the terms of the GNU General Public License //`
10			`// as published by the Free Software Foundation; either version 2 //`
11			`// of the License, or (at your option) any later version. //`
12			`// //`
13			`// This program is distributed in the hope that it will be useful, //`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of //`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //`
16			`// GNU General Public License for more details. //`
17			`// //`
18			`// If you have not received a copy of the GNU General Public License//`
19			`// along with this program; write to: //`
20			`// Free Software Foundation, Inc., //`
21			`// 51 Franklin Street, Fifth Floor, //`
22			`// Boston, MA 02110-1301, USA. //`
23			`// //`
24			`//------------------------------------------------------------------//`
25			`// Revisions: //`
26			`// Ver 0.0.0.1 Apr 28, 2005 Under Development //`
27			`// 0.0.0.2 Jun 09, 2005 Cleaning //`
28	11	smpickett	`// 0.0.0.3 Jun 10, 2005 Re-structuerd the VCNT and HCNT //`
29			`// so they line up with the PXLs. //`
30	8	smpickett	`// //`
31			`//==================================================================//`
32
33	2	smpickett	`module Driver_VGA(`
34			`CLK_50MHZ, MASTER_RST,`
35	11	smpickett	`CLK_VGA,`
36	2	smpickett	`VGA_RAM_DATA, VGA_RAM_ADDR,`
37			`VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS,`
38			`VGA_RAM_ACCESS_OK,`
39			`H_SYNC, V_SYNC, VGA_OUTPUT,`
40	17	smpickett	`XCOORD, YCOORD,`
41	2	smpickett	`TRIGGER_LEVEL,`
42	11	smpickett	`SHOW_LEVELS,`
43			`HCNT, VCNT,`
44			`RGB_CHAR`
45	2	smpickett	`);`
46
47			`//==================================================================//`
48			`// PARAMETER DEFINITIONS //`
49			`//==================================================================//`
50			`parameter P_black = 3'b000;`
51			`parameter P_yellow = 3'b110;`
52			`parameter P_cyan = 3'b011;`
53			`parameter P_green = 3'b010;`
54			`parameter P_white = 3'b111;`
55
56			`//==================================================================//`
57			`// VARIABLE DEFINITIONS //`
58			`//==================================================================//`
59			`//----------------------//`
60			`// INPUTS / OUTPUTS //`
61			`//----------------------//`
62			`input CLK_50MHZ; // System wide clock`
63			`input MASTER_RST; // System wide reset`
64	11	smpickett	`input CLK_VGA;`
65	2	smpickett	`output H_SYNC; // The H_SYNC timing signal to the VGA monitor`
66			`output V_SYNC; // The V_SYNC timing signal to the VGA monitor`
67			`output[2:0] VGA_OUTPUT; // The 3-bit VGA output`
68			`input[11:0] XCOORD, YCOORD;`
69			`input[15:0] VGA_RAM_DATA;`
70			`output[17:0] VGA_RAM_ADDR;`
71			`output VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;`
72			`output VGA_RAM_ACCESS_OK;`
73			`input[8:0] TRIGGER_LEVEL;`
74			`input SHOW_LEVELS;`
75	11	smpickett	`output[9:0] HCNT, VCNT;`
76			`input[2:0] RGB_CHAR;`
77	2	smpickett
78
79
80
81			`//----------------------//`
82			`// WIRES / NODES //`
83			`//----------------------//`
84			`reg H_SYNC, V_SYNC;`
85			`reg [2:0] VGA_OUTPUT;`
86			`wire CLK_50MHZ, MASTER_RST;`
87	11	smpickett	`wire CLK_VGA;`
88	2	smpickett	`wire[11:0] XCOORD, YCOORD;`
89			`wire[15:0] VGA_RAM_DATA;`
90			`reg[17:0] VGA_RAM_ADDR;`
91			`reg VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;`
92			`reg VGA_RAM_ACCESS_OK;`
93			`wire[8:0] TRIGGER_LEVEL;`
94			`wire SHOW_LEVELS;`
95	11	smpickett	`wire[9:0] HCNT, VCNT;`
96			`wire[2:0] RGB_CHAR;`
97	2	smpickett
98
99			`//----------------------//`
100			`// REGISTERS //`
101			`//----------------------//`
102	11	smpickett	`wire CLK_25MHZ = CLK_VGA;`
103	2	smpickett	`reg [9:0] hcnt; // Counter - generates the H_SYNC signal`
104			`reg [9:0] vcnt; // Counter - counts the H_SYNC pulses to generate V_SYNC signal`
105			`reg[2:0] vga_out;`
106
107			`//==================================================================//`
108			`// FUNCTIONAL DEFINITIONS //`
109			`//==================================================================//`
110	11	smpickett	`assign HCNT = hcnt;`
111			`assign VCNT = vcnt;`
112	2	smpickett
113
114			`//------------------------------------------------------------------//`
115			`// SYNC TIMING COUNTERS //`
116			`//------------------------------------------------------------------//`
117			`always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin`
118			`if (MASTER_RST == 1'b1) begin`
119			`hcnt <= 10'd0;`
120	11	smpickett	`vcnt <= 10'd430;`
121	2	smpickett	`end else if (hcnt == 10'd0799) begin`
122			`hcnt <= 10'd0;`
123	11	smpickett	`if (vcnt == 10'd0)`
124			`vcnt <= 10'd520;`
125	2	smpickett	`else`
126	11	smpickett	`vcnt <= vcnt - 1'b1;`
127	2	smpickett	`end else`
128			`hcnt <= hcnt + 1'b1;`
129			`end`
130
131
132			`//------------------------------------------------------------------//`
133			`// HORIZONTAL SYNC TIMING //`
134			`//------------------------------------------------------------------//`
135			`always @ (hcnt)`
136	11	smpickett	`if (hcnt >= 10'd656 && hcnt <= 10'd751)`
137	2	smpickett	`H_SYNC = 1'b0;`
138			`else`
139			`H_SYNC = 1'b1;`
140
141
142			`//------------------------------------------------------------------//`
143			`// VERTICAL SYNC TIMING //`
144			`//------------------------------------------------------------------//`
145			`always @ (vcnt)`
146	11	smpickett	`if (vcnt == 10'd430 \|\| vcnt == 10'd429)`
147	2	smpickett	`V_SYNC = 1'b0;`
148			`else`
149			`V_SYNC = 1'b1;`
150
151
152			`//------------------------------------------------------------------//`
153			`// VGA DATA SIGNAL TIMING //`
154			`//------------------------------------------------------------------//`
155			`always @ (hcnt or vcnt or XCOORD or YCOORD or MASTER_RST or vga_out or SHOW_LEVELS or TRIGGER_LEVEL) begin`
156			`if(MASTER_RST == 1'b1) begin`
157			`VGA_OUTPUT = P_black;`
158			`//------------------------------------------------------------------------------//`
159			`// UNSEEN BORDERS //`
160	11	smpickett	`end else if( (vcnt >= 10'd400) && (vcnt <= 10'd440) ) begin`
161	2	smpickett	`VGA_OUTPUT = P_black;`
162	11	smpickett	`end else if( (hcnt >= 10'd640) ) begin`
163	2	smpickett	`VGA_OUTPUT = P_black;`
164			`//------------------------------------------------------------------------------//`
165			`// MOUSE CURSORS //`
166	11	smpickett	`end else if(vcnt == YCOORD) begin`
167	2	smpickett	`VGA_OUTPUT = P_green;`
168	11	smpickett	`end else if(hcnt == XCOORD) begin`
169	2	smpickett	`VGA_OUTPUT = P_green;`
170			`//------------------------------------------------------------------------------//`
171			`// TRIGGER SPRITE (shows as ------T------ ) //`
172	11	smpickett	`end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL) && hcnt != 10'd556 && hcnt != 10'd558) begin`
173	2	smpickett	`VGA_OUTPUT = P_yellow;`
174	11	smpickett	`end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL+1'b1) && hcnt >= 10'd556 && hcnt <= 10'd558) begin`
175	2	smpickett	`VGA_OUTPUT = P_yellow;`
176	11	smpickett	`end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL-1'b1) && hcnt == 10'd557) begin`
177	2	smpickett	`VGA_OUTPUT = P_yellow;`
178			`//------------------------------------------------------------------------------//`
179			`// TOP, BOTTOM, LEFT AND RIGHT GRID LINES //`
180	11	smpickett	`end else if(vcnt == 10'd0 \|\| vcnt == 10'd399 \|\| vcnt == 10'd441) begin`
181	2	smpickett	`VGA_OUTPUT = P_cyan;`
182	11	smpickett	`end else if(hcnt == 10'd0 \|\| hcnt == 10'd639) begin`
183	2	smpickett	`VGA_OUTPUT = P_cyan;`
184			`//------------------------------------------------------------------------------//`
185	17	smpickett	`// CHARACTER DISPLAY`
186			`end else if(vcnt <= 10'd520 && vcnt >= 10'd441) begin`
187			`VGA_OUTPUT = RGB_CHAR;`
188			`//------------------------------------------------------------------------------//`
189			`// THE WAVEFORM //`
190			`end else if(vga_out != 0) begin`
191			`VGA_OUTPUT = vga_out;`
192			`//------------------------------------------------------------------------------//`
193	2	smpickett	`// MIDDLE GRID LINES (dashed at 8pxls) //`
194	11	smpickett	`end else if(vcnt == 10'd199 && hcnt[3] == 1'b1) begin`
195	2	smpickett	`VGA_OUTPUT = P_cyan;`
196	11	smpickett	`end else if((hcnt == 10'd319) && (vcnt <= 10'd399) && (vcnt[3] == 1'b1)) begin`
197	2	smpickett	`VGA_OUTPUT = P_cyan;`
198			`//------------------------------------------------------------------------------//`
199			`// OTHER HORIZONTAL LINES (dashed at 4pxls) //`
200	11	smpickett	`end else if((vcnt == 10'd39 \|\| vcnt == 10'd79 \|\| vcnt == 10'd119 \|\| vcnt == 10'd159 \|\| vcnt == 10'd239 \|\| vcnt == 10'd279 \|\| vcnt == 10'd319 \|\| vcnt == 10'd359) && (hcnt[2] == 1'b1)) begin`
201	2	smpickett	`VGA_OUTPUT = P_cyan;`
202			`//------------------------------------------------------------------------------//`
203			`// OTHER VERTICAL LINES (dashed at 4pxls) //`
204	11	smpickett	`end else if(((hcnt[5:0] == 6'b111111) && (vcnt <= 10'd399)) && (vcnt[2] == 1'b1)) begin`
205	2	smpickett	`VGA_OUTPUT = P_cyan;`
206			`//------------------------------------------------------------------------------//`
207			`// OTHERWISE... //`
208			`end else`
209			`VGA_OUTPUT = P_black;`
210			`end`
211
212			`//------------------------------------------------------------------//`
213			`// RAM DATA READING //`
214			`//------------------------------------------------------------------//`
215			`// on reset, ram_addr = 24 and add 25 on each pxl`
216			`// row 0: ram_addr = 24 and 25 for each pxl`
217			`// row 1: ram_addr = 24 and 25 for each pxl`
218			`// ...`
219			`// row 15: ram_addr = 24 and 25 for each pxl`
220			`// row 16: ram_addr = 23 and 25 for each pxl *`
221			`// row 17: ram_addr = 23 and 25 for each pxl *`
222			`// ...`
223			`reg[4:0] ram_vcnt;`
224			`reg[15:0] ram_vshift;`
225
226			`always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin`
227			`if(MASTER_RST == 1'b1) begin`
228			`ram_vshift <= 16'h8000;`
229	11	smpickett	`end else if(vcnt > 10'd399) begin`
230	2	smpickett	`ram_vshift <= 16'h8000;`
231	17	smpickett	`end else if(/(vcnt <= 10'd399) && /(hcnt == 10'd640)) begin`
232	2	smpickett	`if(ram_vshift == 16'h0001)`
233			`ram_vshift <= 16'h8000;`
234			`else`
235			`ram_vshift <= (ram_vshift >> 1);`
236			`end else`
237			`ram_vshift <= ram_vshift;`
238			`end`
239
240			`always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin`
241			`if(MASTER_RST == 1'b1) begin`
242	17	smpickett	`ram_vcnt <= 5'd24;//5'b0`
243			`end else if(vcnt > 10'd399) begin`
244			`ram_vcnt <= 5'd24;`
245			`end else if(/(vcnt >= 10'd30) &&/ (hcnt == 10'd640) && (ram_vshift == 16'h0001)) begin`
246	2	smpickett	`if(ram_vcnt == 5'd0)`
247			`ram_vcnt <= 5'd24;`
248	17	smpickett	`else`
249	2	smpickett	`ram_vcnt <= ram_vcnt - 1'b1;`
250			`end else begin`
251			`ram_vcnt <= ram_vcnt;`
252			`end`
253			`end`
254
255
256
257	11	smpickett	`always @ (hcnt or ram_vcnt) begin`
258			`VGA_RAM_ADDR = ram_vcnt + (hcnt * 7'd25);`
259	17	smpickett	`// VGA_RAM_ADDR = vcnt * hcnt;`
260	2	smpickett	`end`
261
262
263			`always @ (VGA_RAM_DATA or ram_vshift) begin`
264			`if((VGA_RAM_DATA & ram_vshift) != 16'b0)`
265			`vga_out = P_white;`
266			`else`
267			`vga_out = 3'b0;`
268			`end`
269
270
271			`always begin`
272			`VGA_RAM_CS = 1'b0; // #CS`
273			`VGA_RAM_OE = 1'b0; // #OE`
274			`VGA_RAM_WE = 1'b1; // #WE`
275			`end`
276
277
278			`//------------------------------------------------------------------//`
279			`// ALL CLEAR? //`
280			`//------------------------------------------------------------------//`
281			`always @ (vcnt) begin`
282	17	smpickett	`if(vcnt > 10'd399)`
283	2	smpickett	`VGA_RAM_ACCESS_OK = 1'b1;`
284			`else`
285			`VGA_RAM_ACCESS_OK = 1'b0;`
286			`end`
287
288
289			`endmodule`

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