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[/] [alternascope/] [trunk/] [VGA/] [d_VGAdriver.v] - Blame information for rev 2

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1 2 smpickett 
//==================================================================
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// File:    d_VGAdriver.v
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// Version: 0.01
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Copyright Stephen Pickett
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//   April 28, 2005
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//------------------------------------------------------------------
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// Revisions:
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// Ver 0.01     Apr 28, 2005    Initial Release
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//
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//==================================================================
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module Driver_VGA(
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    CLK_50MHZ, MASTER_RST,
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    VGA_RAM_DATA, VGA_RAM_ADDR,
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    VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS,
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    VGA_RAM_ACCESS_OK,
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    H_SYNC, V_SYNC, VGA_OUTPUT,
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    XCOORD, YCOORD, ram_vshift,
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    TRIGGER_LEVEL,
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    SHOW_LEVELS
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    );
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//==================================================================//
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// PARAMETER DEFINITIONS                                            //
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//==================================================================//
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parameter P_black   = 3'b000;
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parameter P_yellow  = 3'b110;
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parameter P_cyan    = 3'b011;
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parameter P_green   = 3'b010;
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parameter P_white   = 3'b111;
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//==================================================================//
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// VARIABLE DEFINITIONS                                             //
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//==================================================================//
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//----------------------//
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// INPUTS / OUTPUTS     //
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//----------------------//
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input CLK_50MHZ;                // System wide clock
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input MASTER_RST;               // System wide reset
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output H_SYNC;                  // The H_SYNC timing signal to the VGA monitor
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output V_SYNC;                  // The V_SYNC timing signal to the VGA monitor
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output[2:0]  VGA_OUTPUT;        // The 3-bit VGA output
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input[11:0]  XCOORD, YCOORD;
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input[15:0]  VGA_RAM_DATA;
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output[17:0] VGA_RAM_ADDR;
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output VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
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output VGA_RAM_ACCESS_OK;
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input[8:0] TRIGGER_LEVEL;
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input SHOW_LEVELS;
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output[15:0] ram_vshift;
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//----------------------//
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// WIRES / NODES        //
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//----------------------//
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reg H_SYNC, V_SYNC;
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reg [2:0]  VGA_OUTPUT;
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wire CLK_50MHZ, MASTER_RST;
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wire[11:0] XCOORD, YCOORD;
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wire[15:0] VGA_RAM_DATA;
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reg[17:0]  VGA_RAM_ADDR;
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reg VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
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reg VGA_RAM_ACCESS_OK;
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wire[8:0] TRIGGER_LEVEL;
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wire SHOW_LEVELS;
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69 
 
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//----------------------//
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// REGISTERS            //
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//----------------------//
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reg CLK_25MHZ;      // General system clock for VGA timing
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reg [9:0] hcnt;     // Counter - generates the H_SYNC signal
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reg [9:0] vcnt;     // Counter - counts the H_SYNC pulses to generate V_SYNC signal
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reg[2:0]  vga_out;
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78 
//==================================================================//
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// FUNCTIONAL DEFINITIONS                                           //
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//==================================================================//
81 
 
82 
//------------------------------------------------------------------//
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// CLOCK FUNCTIONS                                                  //
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//------------------------------------------------------------------//
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always @ (posedge CLK_50MHZ or posedge MASTER_RST)
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        if (MASTER_RST == 1'b1)
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            CLK_25MHZ <= 1'b0;
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        else
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            CLK_25MHZ <= ~CLK_25MHZ;
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91 
 
92 
//------------------------------------------------------------------//
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// SYNC TIMING COUNTERS                                             //
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//------------------------------------------------------------------//
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always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
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    if (MASTER_RST == 1'b1) begin
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        hcnt <= 10'd0;
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        vcnt <= 10'd0;
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    end else if (hcnt == 10'd0799) begin
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        hcnt <= 10'd0;
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        if (vcnt == 10'd0520)
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            vcnt <= 10'd0;
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        else
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            vcnt <= vcnt + 1'b1;
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    end else
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        hcnt <= hcnt + 1'b1;
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end
108 
 
109 
 
110 
//------------------------------------------------------------------//
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// HORIZONTAL SYNC TIMING                                           //
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//------------------------------------------------------------------//
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always @ (hcnt)
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    if (hcnt <= 10'd0095)
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        H_SYNC = 1'b0;
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    else
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        H_SYNC = 1'b1;
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119 
 
120 
//------------------------------------------------------------------//
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// VERTICAL SYNC TIMING                                             //
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//------------------------------------------------------------------//
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always @ (vcnt)
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    if (vcnt <= 10'd0001)
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        V_SYNC = 1'b0;
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    else
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        V_SYNC = 1'b1;
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129 
 
130 
//------------------------------------------------------------------//
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// VGA DATA SIGNAL TIMING                                           //
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//------------------------------------------------------------------//
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always @ (hcnt or vcnt or XCOORD or YCOORD or MASTER_RST or vga_out or SHOW_LEVELS or TRIGGER_LEVEL) begin
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    if(MASTER_RST == 1'b1) begin
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        VGA_OUTPUT = P_black;
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    //------------------------------------------------------------------------------//
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    // UNSEEN BORDERS                                                               //
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    end else if( (vcnt <= 10'd30) || (vcnt >= 10'd511) ) begin
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        VGA_OUTPUT = P_black;
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    end else if( (hcnt <= 10'd143) || (hcnt >= 10'd784) ) begin
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        VGA_OUTPUT = P_black;
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    //------------------------------------------------------------------------------//
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    // MOUSE CURSORS                                                                //
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    end else if(vcnt == (YCOORD+10'd31)) begin
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        VGA_OUTPUT = P_green;
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    end else if(hcnt == (XCOORD+10'd144)) begin
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        VGA_OUTPUT = P_green;
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    //------------------------------------------------------------------------------//
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    // TRIGGER SPRITE         (shows as ------T------ )                             //
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    end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL+10'd31) && hcnt != 10'd700 && hcnt != 10'd702) begin
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        VGA_OUTPUT = P_yellow;
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    end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL+1'b1+10'd31) && hcnt >= 10'd700 && hcnt <= 10'd702) begin
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        VGA_OUTPUT = P_yellow;
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    end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL-1'b1+10'd31) && hcnt == 10'd701) begin
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        VGA_OUTPUT = P_yellow;
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///*
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    //------------------------------------------------------------------------------//
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    // MOVE THE WAVEFORM TO THE 'TOP'                                               //
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    end else if(vga_out != 0 && (vcnt < 10'd431)) begin
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        VGA_OUTPUT = vga_out;
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//*/
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    //------------------------------------------------------------------------------//
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    // TOP, BOTTOM, LEFT AND RIGHT GRID LINES                                       //
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    end else if( vcnt == 10'd031 || vcnt == 10'd431 || vcnt == 10'd510) begin
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        VGA_OUTPUT = P_cyan;
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    end else if( hcnt == 10'd144 || hcnt == 10'd783) begin
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        VGA_OUTPUT = P_cyan;
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    //------------------------------------------------------------------------------//
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    // MIDDLE GRID LINES (dashed at 8pxls)                                          //
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    end else if(vcnt == 10'd231 && hcnt[3] == 1'b1) begin
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        VGA_OUTPUT = P_cyan;
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    end else if((hcnt == 10'd464) && (vcnt <= 10'd431) && (vcnt[3] == 1'b1)) begin
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        VGA_OUTPUT = P_cyan;
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    //------------------------------------------------------------------------------//
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    // OTHER HORIZONTAL LINES (dashed at 4pxls)                                     //
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    end else if((vcnt == 10'd071 || vcnt == 10'd111 || vcnt == 10'd151 || vcnt == 10'd191 || vcnt == 10'd271 || vcnt == 10'd311 || vcnt == 10'd351 || vcnt == 10'd391) && (hcnt[2] == 1'b1)) begin
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        VGA_OUTPUT = P_cyan;
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    //------------------------------------------------------------------------------//
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    // OTHER VERTICAL LINES (dashed at 4pxls)                                       //
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    end else if(((hcnt[5:0] == 6'b010000) && (vcnt <= 10'd431)) && (vcnt[2] == 1'b1)) begin
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        VGA_OUTPUT = P_cyan;
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    //------------------------------------------------------------------------------//
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    // OTHERWISE...                                                                 //
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    end else
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        VGA_OUTPUT = P_black;
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/*
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    //------------------------------------------------------------------------------//
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    // DISPLAY DATA                                                                 //
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    end else if(vcnt >= 10'd431) begin
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        VGA_OUTPUT = P_black;
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    end else begin
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        VGA_OUTPUT = vga_out;
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    end
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*/
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end
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//------------------------------------------------------------------//
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// RAM DATA READING                                                 //
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//------------------------------------------------------------------//
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// on reset, ram_addr = 24 and add 25 on each pxl
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//     row 0: ram_addr = 24 and 25 for each pxl
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//     row 1: ram_addr = 24 and 25 for each pxl
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//       ...
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//     row 15: ram_addr = 24 and 25 for each pxl
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//     row 16: ram_addr = 23 and 25 for each pxl *
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//     row 17: ram_addr = 23 and 25 for each pxl *
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//       ...
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reg[9:0]  ram_hcnt;
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reg[4:0]  ram_vcnt;
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reg[15:0] ram_vshift;
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always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
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    if(MASTER_RST == 1'b1) begin
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        ram_hcnt <= 10'd639;
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    end else if(hcnt >= 10'd143 && hcnt <= 782) begin
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        if(ram_hcnt == 10'd639)
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            ram_hcnt <= 10'b0;
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        else
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            ram_hcnt <= ram_hcnt + 1'b1;
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    end else begin
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        ram_hcnt <= 10'd639;
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    end
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end
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always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
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    if(MASTER_RST == 1'b1) begin
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        ram_vshift <= 16'h8000;
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    end else if(vcnt < 10'd31) begin
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        ram_vshift <= 16'h8000;
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    end else if((vcnt >= 10'd31) && (hcnt == 10'd0799)) begin
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        if(ram_vshift == 16'h0001)
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            ram_vshift <= 16'h8000;
234 
        else
235 
            ram_vshift <= (ram_vshift >> 1);
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    end else
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        ram_vshift <= ram_vshift;
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end
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always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
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    if(MASTER_RST == 1'b1) begin
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        ram_vcnt <= 5'd0;
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    end else if(vcnt < 10'd30) begin
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        ram_vcnt <= 5'd0;
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    end else if((vcnt >= 10'd30) && (hcnt == 10'd0799) && (ram_vshift == 16'h0001)) begin
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        if(ram_vcnt == 5'd0)
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            ram_vcnt <= 5'd24;
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        else
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            ram_vcnt <= ram_vcnt - 1'b1;
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    end else begin
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        ram_vcnt <= ram_vcnt;
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    end
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end
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256 
 
257 
always @ (ram_hcnt or ram_vcnt) begin
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    VGA_RAM_ADDR = ram_vcnt + (ram_hcnt * 7'd025);
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end
260 
 
261 
 
262 
always @ (VGA_RAM_DATA or ram_vshift) begin
263 
    if((VGA_RAM_DATA & ram_vshift) != 16'b0)
264 
        vga_out = P_white;
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    else
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        vga_out = 3'b0;
267 
end
268 
 
269 
 
270 
always begin
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    VGA_RAM_CS = 1'b0;  // #CS
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    VGA_RAM_OE = 1'b0;  // #OE
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    VGA_RAM_WE = 1'b1;  // #WE
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end
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277 
//------------------------------------------------------------------//
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// ALL CLEAR?                                                       //
279 
//------------------------------------------------------------------//
280 
always @ (vcnt) begin
281 
    if(vcnt >= 10'd512 || vcnt < 10'd30)
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        VGA_RAM_ACCESS_OK = 1'b1;
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    else
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        VGA_RAM_ACCESS_OK = 1'b0;
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end
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endmodule

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