OpenCores
URL https://opencores.org/ocsvn/alternascope/alternascope/trunk

Subversion Repositories alternascope

[/] [alternascope/] [trunk/] [VGA/] [d_VGAdriver.v] - Blame information for rev 8

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 8 smpickett 
//==================================================================//
2 
// File:    d_VGAdriver.v                                           //
3 
// Version: 0.0.0.2                                                 //
4 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -//
5 
// Copyright (C) Stephen Pickett                                    //
6 
//   Jun 09, 2005                                                   //
7 
//                                                                  //
8 
// This program is free software; you can redistribute it and/or    //
9 
// modify it under the terms of the GNU General Public License      //
10 
// as published by the Free Software Foundation; either version 2   //
11 
// of the License, or (at your option) any later version.           //
12 
//                                                                  //
13 
// This program is distributed in the hope that it will be useful,  //
14 
// but WITHOUT ANY WARRANTY; without even the implied warranty of   //
15 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the    //
16 
// GNU General Public License for more details.                     //
17 
//                                                                  //
18 
// If you have not received a copy of the GNU General Public License//
19 
// along with this program; write to:                               //
20 
//     Free Software Foundation, Inc.,                              //
21 
//     51 Franklin Street, Fifth Floor,                             //
22 
//     Boston, MA  02110-1301, USA.                                 //
23 
//                                                                  //
24 
//------------------------------------------------------------------//
25 
// Revisions:                                                       //
26 
// Ver 0.0.0.1     Apr 28, 2005   Under Development                 //
27 
//     0.0.0.2     Jun 09, 2005   Cleaning                          //
28 
//                                                                  //
29 
//==================================================================//
30 
 
31 2 smpickett 
module Driver_VGA(
32 
    CLK_50MHZ, MASTER_RST,
33 
    VGA_RAM_DATA, VGA_RAM_ADDR,
34 
    VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS,
35 
    VGA_RAM_ACCESS_OK,
36 
    H_SYNC, V_SYNC, VGA_OUTPUT,
37 
    XCOORD, YCOORD, ram_vshift,
38 
    TRIGGER_LEVEL,
39 
    SHOW_LEVELS
40 
    );
41 
 
42 
//==================================================================//
43 
// PARAMETER DEFINITIONS                                            //
44 
//==================================================================//
45 
parameter P_black   = 3'b000;
46 
parameter P_yellow  = 3'b110;
47 
parameter P_cyan    = 3'b011;
48 
parameter P_green   = 3'b010;
49 
parameter P_white   = 3'b111;
50 
 
51 
//==================================================================//
52 
// VARIABLE DEFINITIONS                                             //
53 
//==================================================================//
54 
//----------------------//
55 
// INPUTS / OUTPUTS     //
56 
//----------------------//
57 
input CLK_50MHZ;                // System wide clock
58 
input MASTER_RST;               // System wide reset
59 
output H_SYNC;                  // The H_SYNC timing signal to the VGA monitor
60 
output V_SYNC;                  // The V_SYNC timing signal to the VGA monitor
61 
output[2:0]  VGA_OUTPUT;        // The 3-bit VGA output
62 
input[11:0]  XCOORD, YCOORD;
63 
input[15:0]  VGA_RAM_DATA;
64 
output[17:0] VGA_RAM_ADDR;
65 
output VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
66 
output VGA_RAM_ACCESS_OK;
67 
input[8:0] TRIGGER_LEVEL;
68 
input SHOW_LEVELS;
69 
 
70 
output[15:0] ram_vshift;
71 
 
72 
 
73 
 
74 
//----------------------//
75 
// WIRES / NODES        //
76 
//----------------------//
77 
reg H_SYNC, V_SYNC;
78 
reg [2:0]  VGA_OUTPUT;
79 
wire CLK_50MHZ, MASTER_RST;
80 
wire[11:0] XCOORD, YCOORD;
81 
wire[15:0] VGA_RAM_DATA;
82 
reg[17:0]  VGA_RAM_ADDR;
83 
reg VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
84 
reg VGA_RAM_ACCESS_OK;
85 
wire[8:0] TRIGGER_LEVEL;
86 
wire SHOW_LEVELS;
87 
 
88 
 
89 
//----------------------//
90 
// REGISTERS            //
91 
//----------------------//
92 
reg CLK_25MHZ;      // General system clock for VGA timing
93 
reg [9:0] hcnt;     // Counter - generates the H_SYNC signal
94 
reg [9:0] vcnt;     // Counter - counts the H_SYNC pulses to generate V_SYNC signal
95 
reg[2:0]  vga_out;
96 
 
97 
//==================================================================//
98 
// FUNCTIONAL DEFINITIONS                                           //
99 
//==================================================================//
100 
 
101 
//------------------------------------------------------------------//
102 
// CLOCK FUNCTIONS                                                  //
103 
//------------------------------------------------------------------//
104 
always @ (posedge CLK_50MHZ or posedge MASTER_RST)
105 
        if (MASTER_RST == 1'b1)
106 
            CLK_25MHZ <= 1'b0;
107 
        else
108 
            CLK_25MHZ <= ~CLK_25MHZ;
109 
 
110 
 
111 
//------------------------------------------------------------------//
112 
// SYNC TIMING COUNTERS                                             //
113 
//------------------------------------------------------------------//
114 
always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
115 
    if (MASTER_RST == 1'b1) begin
116 
        hcnt <= 10'd0;
117 
        vcnt <= 10'd0;
118 
    end else if (hcnt == 10'd0799) begin
119 
        hcnt <= 10'd0;
120 
        if (vcnt == 10'd0520)
121 
            vcnt <= 10'd0;
122 
        else
123 
            vcnt <= vcnt + 1'b1;
124 
    end else
125 
        hcnt <= hcnt + 1'b1;
126 
end
127 
 
128 
 
129 
//------------------------------------------------------------------//
130 
// HORIZONTAL SYNC TIMING                                           //
131 
//------------------------------------------------------------------//
132 
always @ (hcnt)
133 
    if (hcnt <= 10'd0095)
134 
        H_SYNC = 1'b0;
135 
    else
136 
        H_SYNC = 1'b1;
137 
 
138 
 
139 
//------------------------------------------------------------------//
140 
// VERTICAL SYNC TIMING                                             //
141 
//------------------------------------------------------------------//
142 
always @ (vcnt)
143 
    if (vcnt <= 10'd0001)
144 
        V_SYNC = 1'b0;
145 
    else
146 
        V_SYNC = 1'b1;
147 
 
148 
 
149 
//------------------------------------------------------------------//
150 
// VGA DATA SIGNAL TIMING                                           //
151 
//------------------------------------------------------------------//
152 
always @ (hcnt or vcnt or XCOORD or YCOORD or MASTER_RST or vga_out or SHOW_LEVELS or TRIGGER_LEVEL) begin
153 
    if(MASTER_RST == 1'b1) begin
154 
        VGA_OUTPUT = P_black;
155 
    //------------------------------------------------------------------------------//
156 
    // UNSEEN BORDERS                                                               //
157 
    end else if( (vcnt <= 10'd30) || (vcnt >= 10'd511) ) begin
158 
        VGA_OUTPUT = P_black;
159 
    end else if( (hcnt <= 10'd143) || (hcnt >= 10'd784) ) begin
160 
        VGA_OUTPUT = P_black;
161 
    //------------------------------------------------------------------------------//
162 
    // MOUSE CURSORS                                                                //
163 
    end else if(vcnt == (YCOORD+10'd31)) begin
164 
        VGA_OUTPUT = P_green;
165 
    end else if(hcnt == (XCOORD+10'd144)) begin
166 
        VGA_OUTPUT = P_green;
167 
    //------------------------------------------------------------------------------//
168 
    // TRIGGER SPRITE         (shows as ------T------ )                             //
169 
    end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL+10'd31) && hcnt != 10'd700 && hcnt != 10'd702) begin
170 
        VGA_OUTPUT = P_yellow;
171 8 smpickett 
    end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL-1'b1+10'd31) && hcnt >= 10'd700 && hcnt <= 10'd702) begin
172 2 smpickett 
        VGA_OUTPUT = P_yellow;
173 8 smpickett 
    end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL+1'b1+10'd31) && hcnt == 10'd701) begin
174 2 smpickett 
        VGA_OUTPUT = P_yellow;
175 
///*
176 
    //------------------------------------------------------------------------------//
177 
    // MOVE THE WAVEFORM TO THE 'TOP'                                               //
178 
    end else if(vga_out != 0 && (vcnt < 10'd431)) begin
179 
        VGA_OUTPUT = vga_out;
180 
//*/
181 
    //------------------------------------------------------------------------------//
182 
    // TOP, BOTTOM, LEFT AND RIGHT GRID LINES                                       //
183 
    end else if( vcnt == 10'd031 || vcnt == 10'd431 || vcnt == 10'd510) begin
184 
        VGA_OUTPUT = P_cyan;
185 
    end else if( hcnt == 10'd144 || hcnt == 10'd783) begin
186 
        VGA_OUTPUT = P_cyan;
187 
    //------------------------------------------------------------------------------//
188 
    // MIDDLE GRID LINES (dashed at 8pxls)                                          //
189 
    end else if(vcnt == 10'd231 && hcnt[3] == 1'b1) begin
190 
        VGA_OUTPUT = P_cyan;
191 
    end else if((hcnt == 10'd464) && (vcnt <= 10'd431) && (vcnt[3] == 1'b1)) begin
192 
        VGA_OUTPUT = P_cyan;
193 
    //------------------------------------------------------------------------------//
194 
    // OTHER HORIZONTAL LINES (dashed at 4pxls)                                     //
195 
    end else if((vcnt == 10'd071 || vcnt == 10'd111 || vcnt == 10'd151 || vcnt == 10'd191 || vcnt == 10'd271 || vcnt == 10'd311 || vcnt == 10'd351 || vcnt == 10'd391) && (hcnt[2] == 1'b1)) begin
196 
        VGA_OUTPUT = P_cyan;
197 
    //------------------------------------------------------------------------------//
198 
    // OTHER VERTICAL LINES (dashed at 4pxls)                                       //
199 
    end else if(((hcnt[5:0] == 6'b010000) && (vcnt <= 10'd431)) && (vcnt[2] == 1'b1)) begin
200 
        VGA_OUTPUT = P_cyan;
201 
    //------------------------------------------------------------------------------//
202 
    // OTHERWISE...                                                                 //
203 
    end else
204 
        VGA_OUTPUT = P_black;
205 
/*
206 
    //------------------------------------------------------------------------------//
207 
    // DISPLAY DATA                                                                 //
208 
    end else if(vcnt >= 10'd431) begin
209 
        VGA_OUTPUT = P_black;
210 
    end else begin
211 
        VGA_OUTPUT = vga_out;
212 
    end
213 
*/
214 
end
215 
 
216 
//------------------------------------------------------------------//
217 
// RAM DATA READING                                                 //
218 
//------------------------------------------------------------------//
219 
// on reset, ram_addr = 24 and add 25 on each pxl
220 
//     row 0: ram_addr = 24 and 25 for each pxl
221 
//     row 1: ram_addr = 24 and 25 for each pxl
222 
//       ...
223 
//     row 15: ram_addr = 24 and 25 for each pxl
224 
//     row 16: ram_addr = 23 and 25 for each pxl *
225 
//     row 17: ram_addr = 23 and 25 for each pxl *
226 
//       ...
227 
reg[9:0]  ram_hcnt;
228 
reg[4:0]  ram_vcnt;
229 
reg[15:0] ram_vshift;
230 
 
231 
 
232 
always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
233 
    if(MASTER_RST == 1'b1) begin
234 
        ram_hcnt <= 10'd639;
235 
    end else if(hcnt >= 10'd143 && hcnt <= 782) begin
236 
        if(ram_hcnt == 10'd639)
237 
            ram_hcnt <= 10'b0;
238 
        else
239 
            ram_hcnt <= ram_hcnt + 1'b1;
240 
    end else begin
241 
        ram_hcnt <= 10'd639;
242 
    end
243 
end
244 
 
245 
always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
246 
    if(MASTER_RST == 1'b1) begin
247 
        ram_vshift <= 16'h8000;
248 
    end else if(vcnt < 10'd31) begin
249 
        ram_vshift <= 16'h8000;
250 
    end else if((vcnt >= 10'd31) && (hcnt == 10'd0799)) begin
251 
        if(ram_vshift == 16'h0001)
252 
            ram_vshift <= 16'h8000;
253 
        else
254 
            ram_vshift <= (ram_vshift >> 1);
255 
    end else
256 
        ram_vshift <= ram_vshift;
257 
end
258 
 
259 
always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
260 
    if(MASTER_RST == 1'b1) begin
261 
        ram_vcnt <= 5'd0;
262 
    end else if(vcnt < 10'd30) begin
263 
        ram_vcnt <= 5'd0;
264 
    end else if((vcnt >= 10'd30) && (hcnt == 10'd0799) && (ram_vshift == 16'h0001)) begin
265 
        if(ram_vcnt == 5'd0)
266 
            ram_vcnt <= 5'd24;
267 
        else
268 
            ram_vcnt <= ram_vcnt - 1'b1;
269 
    end else begin
270 
        ram_vcnt <= ram_vcnt;
271 
    end
272 
end
273 
 
274 
 
275 
 
276 
always @ (ram_hcnt or ram_vcnt) begin
277 
    VGA_RAM_ADDR = ram_vcnt + (ram_hcnt * 7'd025);
278 
end
279 
 
280 
 
281 
always @ (VGA_RAM_DATA or ram_vshift) begin
282 
    if((VGA_RAM_DATA & ram_vshift) != 16'b0)
283 
        vga_out = P_white;
284 
    else
285 
        vga_out = 3'b0;
286 
end
287 
 
288 
 
289 
always begin
290 
    VGA_RAM_CS = 1'b0;  // #CS
291 
    VGA_RAM_OE = 1'b0;  // #OE
292 
    VGA_RAM_WE = 1'b1;  // #WE
293 
end
294 
 
295 
 
296 
//------------------------------------------------------------------//
297 
// ALL CLEAR?                                                       //
298 
//------------------------------------------------------------------//
299 
always @ (vcnt) begin
300 
    if(vcnt >= 10'd512 || vcnt < 10'd30)
301 
        VGA_RAM_ACCESS_OK = 1'b1;
302 
    else
303 
        VGA_RAM_ACCESS_OK = 1'b0;
304 
end
305 
 
306 
 
307 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.