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[/] [alternascope/] [trunk/] [VGA/] [d_VgaRamBuffer.v] - Blame information for rev 17

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//==================================================================
// File:    d_VgaRamBuffer.v
// Version: 0.01
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Copyright Stephen Pickett
//   April 28, 2005
//------------------------------------------------------------------
// Revisions:
// Ver 0.01     Apr 28, 2005    Initial Release
//
//==================================================================
module VGADataBuffer(
    CLK_50MHZ, MASTER_RST,
    VGA_RAM_DATA, VGA_RAM_ADDR, VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS,
    VGA_RAM_ACCESS_OK,
    ADC_RAM_DATA, ADC_RAM_ADDR, ADC_RAM_CLK,
    TIME_BASE,
    TRIG_ADDR, VGA_WRITE_DONE
    );
//==================================================================//
// VARIABLE DEFINITIONS                                             //
//==================================================================//
//----------------------//
// INPUTS / OUTPUTS     //
//----------------------//
input CLK_50MHZ;                // System wide clock
input MASTER_RST;               // System wide reset
 
output[15:0] VGA_RAM_DATA;
output[17:0] VGA_RAM_ADDR;
output       VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
input        VGA_RAM_ACCESS_OK;
 
input[7:0]   ADC_RAM_DATA;
output[10:0] ADC_RAM_ADDR;
output       ADC_RAM_CLK;
 
input[5:0] TIME_BASE;
 
output      VGA_WRITE_DONE;
input[10:0] TRIG_ADDR;
 
 
//----------------------//
// WIRES / NODES        //
//----------------------//
wire CLK_50MHZ;                // System wide clock
wire MASTER_RST;               // System wide reset
wire[15:0] VGA_RAM_DATA;
reg[17:0] VGA_RAM_ADDR;
reg VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
wire  VGA_RAM_ACCESS_OK;
wire[7:0] ADC_RAM_DATA;
reg[10:0] ADC_RAM_ADDR;
wire ADC_RAM_CLK;
wire[5:0] TIME_BASE;
reg VGA_WRITE_DONE;
wire[10:0] TRIG_ADDR;
 
 
//----------------------//
// REGISTERS            //
//----------------------//
reg[4:0]  vcnt;
reg[9:0]  hcnt;
reg[15:0] data_to_ram;
reg[8:0]  adc_data_scale;
reg[10:0] TRIG_ADDR_buffered;
 
 
//==================================================================//
// FUNCTIONAL DEFINITIONS                                           //
//==================================================================//
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
    if(MASTER_RST == 1'b1) begin
        vcnt <= 5'd0;
    end else if(VGA_RAM_ACCESS_OK && hcnt != 10'd640) begin
        if(vcnt == 5'd24)
            vcnt <= 5'b0;
        else
            vcnt <= vcnt + 1'b1;
    end else begin
        vcnt <= 5'd0;
    end
end
 
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
    if(MASTER_RST == 1'b1) begin
        hcnt <= 10'd0;
    end else if(VGA_RAM_ACCESS_OK) begin
        if(hcnt == 10'd640)
            hcnt <= hcnt;
        else if(vcnt == 5'd24)
            hcnt <= hcnt + 1'b1;
        else
            hcnt <= hcnt;
    end else begin
        hcnt <= 10'b0;
    end
end
 
/* VGA_WRITE_DONE -> BASED ON hcnt */
always @ (hcnt) begin
    if(hcnt == 10'd640)
        VGA_WRITE_DONE = 1'b1;
    else
        VGA_WRITE_DONE = 1'b0;
end
 
/* TRIG_ADDR modified */
always @ (TRIG_ADDR) begin
    if(TRIG_ADDR < 10'd320)
        TRIG_ADDR_buffered = (11'd2047 - 10'd320) - TRIG_ADDR;
    else
        TRIG_ADDR_buffered = TRIG_ADDR;
end
 
 
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
    if(MASTER_RST == 1'b1) begin
        ADC_RAM_ADDR <= 11'b0;
    end else if(VGA_RAM_ACCESS_OK) begin
        if((hcnt == 10'd640) || !(vcnt == 5'd24))
            ADC_RAM_ADDR <= ADC_RAM_ADDR;
        else
            ADC_RAM_ADDR <= ADC_RAM_ADDR + 1'b1;
    end else begin
        ADC_RAM_ADDR <= TRIG_ADDR_buffered;
    end
end
 
reg[7:0] TESTING_CNT;
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
    if(MASTER_RST == 1'b1) begin
        TESTING_CNT <= 8'd0;
    end else if(VGA_RAM_ACCESS_OK) begin
        if(vcnt == 5'd24)
            TESTING_CNT <= TESTING_CNT+1;
        else
            TESTING_CNT <= TESTING_CNT;
    end else begin
        TESTING_CNT <= 8'b0;
    end
end
 
 
always @ (ADC_RAM_DATA) begin
//      adc_data_scale = TESTING_CNT + (TESTING_CNT>>1) + (TESTING_CNT>>4) + (TESTING_CNT>>6);
//      adc_data_scale = ADC_RAM_DATA + (ADC_RAM_DATA>>1) + (ADC_RAM_DATA>>4) + (ADC_RAM_DATA>>6);
      adc_data_scale = ADC_RAM_DATA;
end
 
 
 
 
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
    if(MASTER_RST == 1'b1) begin
        VGA_RAM_ADDR <= 18'b0;
    end else if(VGA_RAM_ACCESS_OK) begin
        if(hcnt == 10'd640)
            VGA_RAM_ADDR <= VGA_RAM_ADDR;
        else
            VGA_RAM_ADDR <= VGA_RAM_ADDR + 1'b1;
    end else begin
        VGA_RAM_ADDR <= 18'b0;
    end
end
/*
always @ (vcnt or VGA_RAM_ACCESS_OK or adc_data_scale) begin
    if(VGA_RAM_ACCESS_OK) begin
        if(vcnt == adc_data_scale[8:4]) begin
            data_to_ram = (adc_data_scale[3:0] == 4'd0)  & 16'h0001 |
                          (adc_data_scale[3:0] == 4'd1)  & 16'h0002 |
                          (adc_data_scale[3:0] == 4'd2)  & 16'h0004 |
                          (adc_data_scale[3:0] == 4'd3)  & 16'h0008 |
                          (adc_data_scale[3:0] == 4'd4)  & 16'h0010 |
                          (adc_data_scale[3:0] == 4'd5)  & 16'h0020 |
                          (adc_data_scale[3:0] == 4'd6)  & 16'h0040 |
                          (adc_data_scale[3:0] == 4'd7)  & 16'h0080 |
                          (adc_data_scale[3:0] == 4'd8)  & 16'h0100 |
                          (adc_data_scale[3:0] == 4'd9)  & 16'h0200 |
                          (adc_data_scale[3:0] == 4'd10) & 16'h0400 |
                          (adc_data_scale[3:0] == 4'd11) & 16'h0800 |
                          (adc_data_scale[3:0] == 4'd12) & 16'h1000 |
                          (adc_data_scale[3:0] == 4'd13) & 16'h2000 |
                          (adc_data_scale[3:0] == 4'd14) & 16'h4000 |
                          (adc_data_scale[3:0] == 4'd15) & 16'h8000;
        end else begin
            data_to_ram = 16'b0;
        end
    end else begin
        data_to_ram = 16'bZ;
    end
end
*/
 
always @ (vcnt or VGA_RAM_ACCESS_OK or adc_data_scale) begin
    if(VGA_RAM_ACCESS_OK) begin
        if(vcnt == adc_data_scale[8:4]) begin
            if(adc_data_scale[3:0] == 4'd0)
                data_to_ram = 16'h0001;
            else if(adc_data_scale[3:0] == 4'd1)
                data_to_ram = 16'h0002;
            else if(adc_data_scale[3:0] == 4'd2)
                data_to_ram = 16'h0004;
            else if(adc_data_scale[3:0] == 4'd3)
                data_to_ram = 16'h0008;
            else if(adc_data_scale[3:0] == 4'd4)
                data_to_ram = 16'h0010;
            else if(adc_data_scale[3:0] == 4'd5)
                data_to_ram = 16'h0020;
            else if(adc_data_scale[3:0] == 4'd6)
                data_to_ram = 16'h0040;
            else if(adc_data_scale[3:0] == 4'd7)
                data_to_ram = 16'h0080;
            else if(adc_data_scale[3:0] == 4'd8)
                data_to_ram = 16'h0100;
            else if(adc_data_scale[3:0] == 4'd9)
                data_to_ram = 16'h0200;
            else if(adc_data_scale[3:0] == 4'd10)
                data_to_ram = 16'h0400;
            else if(adc_data_scale[3:0] == 4'd11)
                data_to_ram = 16'h0800;
            else if(adc_data_scale[3:0] == 4'd12)
                data_to_ram = 16'h1000;
            else if(adc_data_scale[3:0] == 4'd13)
                data_to_ram = 16'h2000;
            else if(adc_data_scale[3:0] == 4'd14)
                data_to_ram = 16'h4000;
            else if(adc_data_scale[3:0] == 4'd15)
                data_to_ram = 16'h8000;
            else
                data_to_ram = 16'hFFFF;
        end else //end bigIF
            data_to_ram = 16'b0;
    end else begin
        data_to_ram = 16'bZ;
    end
end
 
/*
always @ (vcnt or VGA_RAM_ACCESS_OK or ADC_RAM_DATA) begin
    if(VGA_RAM_ACCESS_OK) begin
        if((vcnt[3:0] == ADC_RAM_DATA[7:4]) && vcnt[4] != 1'b1) begin
            if(ADC_RAM_DATA[3:0] == 4'd0)
                data_to_ram = 16'h0001;
            else if(ADC_RAM_DATA[3:0] == 4'd1)
                data_to_ram = 16'h0002;
            else if(ADC_RAM_DATA[3:0] == 4'd2)
                data_to_ram = 16'h0004;
            else if(ADC_RAM_DATA[3:0] == 4'd3)
                data_to_ram = 16'h0008;
            else if(ADC_RAM_DATA[3:0] == 4'd4)
                data_to_ram = 16'h0010;
            else if(ADC_RAM_DATA[3:0] == 4'd5)
                data_to_ram = 16'h0020;
            else if(ADC_RAM_DATA[3:0] == 4'd6)
                data_to_ram = 16'h0040;
            else if(ADC_RAM_DATA[3:0] == 4'd7)
                data_to_ram = 16'h0080;
            else if(ADC_RAM_DATA[3:0] == 4'd8)
                data_to_ram = 16'h0100;
            else if(ADC_RAM_DATA[3:0] == 4'd9)
                data_to_ram = 16'h0200;
            else if(ADC_RAM_DATA[3:0] == 4'd10)
                data_to_ram = 16'h0400;
            else if(ADC_RAM_DATA[3:0] == 4'd11)
                data_to_ram = 16'h0800;
            else if(ADC_RAM_DATA[3:0] == 4'd12)
                data_to_ram = 16'h1000;
            else if(ADC_RAM_DATA[3:0] == 4'd13)
                data_to_ram = 16'h2000;
            else if(ADC_RAM_DATA[3:0] == 4'd14)
                data_to_ram = 16'h4000;
            else if(ADC_RAM_DATA[3:0] == 4'd15)
                data_to_ram = 16'h8000;
            else
                data_to_ram = 16'hFFFF;
        end else //end bigIF
            data_to_ram = 16'b0;
    end else begin
        data_to_ram = 16'bZ;
    end
end
*/
/*
always @ (vcnt) begin
    if(vcnt == 5'd00 && hcnt <= 10'd319)
        data_to_ram = 16'h000F;
    else
        data_to_ram = 16'b0;
end
*/
 
assign ADC_RAM_CLK = CLK_50MHZ;
 
assign VGA_RAM_DATA = data_to_ram;
 
always begin
    VGA_RAM_OE = 1'b1;
    VGA_RAM_WE = 1'b0;
    VGA_RAM_CS = 1'b0;
end
 
 
 
 
 
 
 
 
 
 
 
 
endmodule

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[/] [alternascope/] [trunk/] [VGA/] [d_VgaRamBuffer.v] - Blame information for rev 17

Line No.	Rev	Author	Line
1	2	smpickett	`//==================================================================`
2			`// File: d_VgaRamBuffer.v`
3			`// Version: 0.01`
4			`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
5			`// Copyright Stephen Pickett`
6			`// April 28, 2005`
7			`//------------------------------------------------------------------`
8			`// Revisions:`
9			`// Ver 0.01 Apr 28, 2005 Initial Release`
10			`//`
11			`//==================================================================`
12			`module VGADataBuffer(`
13			`CLK_50MHZ, MASTER_RST,`
14			`VGA_RAM_DATA, VGA_RAM_ADDR, VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS,`
15			`VGA_RAM_ACCESS_OK,`
16			`ADC_RAM_DATA, ADC_RAM_ADDR, ADC_RAM_CLK,`
17			`TIME_BASE,`
18			`TRIG_ADDR, VGA_WRITE_DONE`
19			`);`
20			`//==================================================================//`
21			`// VARIABLE DEFINITIONS //`
22			`//==================================================================//`
23			`//----------------------//`
24			`// INPUTS / OUTPUTS //`
25			`//----------------------//`
26			`input CLK_50MHZ; // System wide clock`
27			`input MASTER_RST; // System wide reset`
28
29			`output[15:0] VGA_RAM_DATA;`
30			`output[17:0] VGA_RAM_ADDR;`
31			`output VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;`
32			`input VGA_RAM_ACCESS_OK;`
33
34			`input[7:0] ADC_RAM_DATA;`
35			`output[10:0] ADC_RAM_ADDR;`
36			`output ADC_RAM_CLK;`
37
38			`input[5:0] TIME_BASE;`
39
40			`output VGA_WRITE_DONE;`
41			`input[10:0] TRIG_ADDR;`
42
43
44			`//----------------------//`
45			`// WIRES / NODES //`
46			`//----------------------//`
47			`wire CLK_50MHZ; // System wide clock`
48			`wire MASTER_RST; // System wide reset`
49			`wire[15:0] VGA_RAM_DATA;`
50			`reg[17:0] VGA_RAM_ADDR;`
51			`reg VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;`
52			`wire VGA_RAM_ACCESS_OK;`
53			`wire[7:0] ADC_RAM_DATA;`
54			`reg[10:0] ADC_RAM_ADDR;`
55			`wire ADC_RAM_CLK;`
56			`wire[5:0] TIME_BASE;`
57			`reg VGA_WRITE_DONE;`
58			`wire[10:0] TRIG_ADDR;`
59
60
61			`//----------------------//`
62			`// REGISTERS //`
63			`//----------------------//`
64			`reg[4:0] vcnt;`
65			`reg[9:0] hcnt;`
66			`reg[15:0] data_to_ram;`
67			`reg[8:0] adc_data_scale;`
68			`reg[10:0] TRIG_ADDR_buffered;`
69
70
71			`//==================================================================//`
72			`// FUNCTIONAL DEFINITIONS //`
73			`//==================================================================//`
74			`always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin`
75			`if(MASTER_RST == 1'b1) begin`
76			`vcnt <= 5'd0;`
77			`end else if(VGA_RAM_ACCESS_OK && hcnt != 10'd640) begin`
78			`if(vcnt == 5'd24)`
79			`vcnt <= 5'b0;`
80			`else`
81			`vcnt <= vcnt + 1'b1;`
82			`end else begin`
83			`vcnt <= 5'd0;`
84			`end`
85			`end`
86
87			`always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin`
88			`if(MASTER_RST == 1'b1) begin`
89			`hcnt <= 10'd0;`
90			`end else if(VGA_RAM_ACCESS_OK) begin`
91			`if(hcnt == 10'd640)`
92			`hcnt <= hcnt;`
93			`else if(vcnt == 5'd24)`
94			`hcnt <= hcnt + 1'b1;`
95			`else`
96			`hcnt <= hcnt;`
97			`end else begin`
98			`hcnt <= 10'b0;`
99			`end`
100			`end`
101
102			`/* VGA_WRITE_DONE -> BASED ON hcnt */`
103			`always @ (hcnt) begin`
104			`if(hcnt == 10'd640)`
105			`VGA_WRITE_DONE = 1'b1;`
106			`else`
107			`VGA_WRITE_DONE = 1'b0;`
108			`end`
109
110			`/* TRIG_ADDR modified */`
111			`always @ (TRIG_ADDR) begin`
112			`if(TRIG_ADDR < 10'd320)`
113	17	smpickett	`TRIG_ADDR_buffered = (11'd2047 - 10'd320) - TRIG_ADDR;`
114	2	smpickett	`else`
115			`TRIG_ADDR_buffered = TRIG_ADDR;`
116			`end`
117
118
119			`always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin`
120			`if(MASTER_RST == 1'b1) begin`
121			`ADC_RAM_ADDR <= 11'b0;`
122			`end else if(VGA_RAM_ACCESS_OK) begin`
123			`if((hcnt == 10'd640) \|\| !(vcnt == 5'd24))`
124			`ADC_RAM_ADDR <= ADC_RAM_ADDR;`
125			`else`
126			`ADC_RAM_ADDR <= ADC_RAM_ADDR + 1'b1;`
127			`end else begin`
128			`ADC_RAM_ADDR <= TRIG_ADDR_buffered;`
129			`end`
130			`end`
131
132	17	smpickett	`reg[7:0] TESTING_CNT;`
133			`always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin`
134			`if(MASTER_RST == 1'b1) begin`
135			`TESTING_CNT <= 8'd0;`
136			`end else if(VGA_RAM_ACCESS_OK) begin`
137			`if(vcnt == 5'd24)`
138			`TESTING_CNT <= TESTING_CNT+1;`
139			`else`
140			`TESTING_CNT <= TESTING_CNT;`
141			`end else begin`
142			`TESTING_CNT <= 8'b0;`
143			`end`
144			`end`
145
146
147	2	smpickett	`always @ (ADC_RAM_DATA) begin`
148	17	smpickett	`// adc_data_scale = TESTING_CNT + (TESTING_CNT>>1) + (TESTING_CNT>>4) + (TESTING_CNT>>6);`
149			`// adc_data_scale = ADC_RAM_DATA + (ADC_RAM_DATA>>1) + (ADC_RAM_DATA>>4) + (ADC_RAM_DATA>>6);`
150			`adc_data_scale = ADC_RAM_DATA;`
151	2	smpickett	`end`
152
153
154	17	smpickett
155
156	2	smpickett	`always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin`
157			`if(MASTER_RST == 1'b1) begin`
158			`VGA_RAM_ADDR <= 18'b0;`
159			`end else if(VGA_RAM_ACCESS_OK) begin`
160			`if(hcnt == 10'd640)`
161			`VGA_RAM_ADDR <= VGA_RAM_ADDR;`
162			`else`
163			`VGA_RAM_ADDR <= VGA_RAM_ADDR + 1'b1;`
164			`end else begin`
165			`VGA_RAM_ADDR <= 18'b0;`
166			`end`
167			`end`
168			`/*`
169			`always @ (vcnt or VGA_RAM_ACCESS_OK or adc_data_scale) begin`
170			`if(VGA_RAM_ACCESS_OK) begin`
171			`if(vcnt == adc_data_scale[8:4]) begin`
172			`data_to_ram = (adc_data_scale[3:0] == 4'd0) & 16'h0001 \|`
173			`(adc_data_scale[3:0] == 4'd1) & 16'h0002 \|`
174			`(adc_data_scale[3:0] == 4'd2) & 16'h0004 \|`
175			`(adc_data_scale[3:0] == 4'd3) & 16'h0008 \|`
176			`(adc_data_scale[3:0] == 4'd4) & 16'h0010 \|`
177			`(adc_data_scale[3:0] == 4'd5) & 16'h0020 \|`
178			`(adc_data_scale[3:0] == 4'd6) & 16'h0040 \|`
179			`(adc_data_scale[3:0] == 4'd7) & 16'h0080 \|`
180			`(adc_data_scale[3:0] == 4'd8) & 16'h0100 \|`
181			`(adc_data_scale[3:0] == 4'd9) & 16'h0200 \|`
182			`(adc_data_scale[3:0] == 4'd10) & 16'h0400 \|`
183			`(adc_data_scale[3:0] == 4'd11) & 16'h0800 \|`
184			`(adc_data_scale[3:0] == 4'd12) & 16'h1000 \|`
185			`(adc_data_scale[3:0] == 4'd13) & 16'h2000 \|`
186			`(adc_data_scale[3:0] == 4'd14) & 16'h4000 \|`
187			`(adc_data_scale[3:0] == 4'd15) & 16'h8000;`
188			`end else begin`
189			`data_to_ram = 16'b0;`
190			`end`
191			`end else begin`
192			`data_to_ram = 16'bZ;`
193			`end`
194			`end`
195			`*/`
196
197			`always @ (vcnt or VGA_RAM_ACCESS_OK or adc_data_scale) begin`
198			`if(VGA_RAM_ACCESS_OK) begin`
199			`if(vcnt == adc_data_scale[8:4]) begin`
200			`if(adc_data_scale[3:0] == 4'd0)`
201			`data_to_ram = 16'h0001;`
202			`else if(adc_data_scale[3:0] == 4'd1)`
203			`data_to_ram = 16'h0002;`
204			`else if(adc_data_scale[3:0] == 4'd2)`
205			`data_to_ram = 16'h0004;`
206			`else if(adc_data_scale[3:0] == 4'd3)`
207			`data_to_ram = 16'h0008;`
208			`else if(adc_data_scale[3:0] == 4'd4)`
209			`data_to_ram = 16'h0010;`
210			`else if(adc_data_scale[3:0] == 4'd5)`
211			`data_to_ram = 16'h0020;`
212			`else if(adc_data_scale[3:0] == 4'd6)`
213			`data_to_ram = 16'h0040;`
214			`else if(adc_data_scale[3:0] == 4'd7)`
215			`data_to_ram = 16'h0080;`
216			`else if(adc_data_scale[3:0] == 4'd8)`
217			`data_to_ram = 16'h0100;`
218			`else if(adc_data_scale[3:0] == 4'd9)`
219			`data_to_ram = 16'h0200;`
220			`else if(adc_data_scale[3:0] == 4'd10)`
221			`data_to_ram = 16'h0400;`
222			`else if(adc_data_scale[3:0] == 4'd11)`
223			`data_to_ram = 16'h0800;`
224			`else if(adc_data_scale[3:0] == 4'd12)`
225			`data_to_ram = 16'h1000;`
226			`else if(adc_data_scale[3:0] == 4'd13)`
227			`data_to_ram = 16'h2000;`
228			`else if(adc_data_scale[3:0] == 4'd14)`
229			`data_to_ram = 16'h4000;`
230			`else if(adc_data_scale[3:0] == 4'd15)`
231			`data_to_ram = 16'h8000;`
232			`else`
233			`data_to_ram = 16'hFFFF;`
234			`end else //end bigIF`
235			`data_to_ram = 16'b0;`
236			`end else begin`
237			`data_to_ram = 16'bZ;`
238			`end`
239			`end`
240
241			`/*`
242			`always @ (vcnt or VGA_RAM_ACCESS_OK or ADC_RAM_DATA) begin`
243			`if(VGA_RAM_ACCESS_OK) begin`
244			`if((vcnt[3:0] == ADC_RAM_DATA[7:4]) && vcnt[4] != 1'b1) begin`
245			`if(ADC_RAM_DATA[3:0] == 4'd0)`
246			`data_to_ram = 16'h0001;`
247			`else if(ADC_RAM_DATA[3:0] == 4'd1)`
248			`data_to_ram = 16'h0002;`
249			`else if(ADC_RAM_DATA[3:0] == 4'd2)`
250			`data_to_ram = 16'h0004;`
251			`else if(ADC_RAM_DATA[3:0] == 4'd3)`
252			`data_to_ram = 16'h0008;`
253			`else if(ADC_RAM_DATA[3:0] == 4'd4)`
254			`data_to_ram = 16'h0010;`
255			`else if(ADC_RAM_DATA[3:0] == 4'd5)`
256			`data_to_ram = 16'h0020;`
257			`else if(ADC_RAM_DATA[3:0] == 4'd6)`
258			`data_to_ram = 16'h0040;`
259			`else if(ADC_RAM_DATA[3:0] == 4'd7)`
260			`data_to_ram = 16'h0080;`
261			`else if(ADC_RAM_DATA[3:0] == 4'd8)`
262			`data_to_ram = 16'h0100;`
263			`else if(ADC_RAM_DATA[3:0] == 4'd9)`
264			`data_to_ram = 16'h0200;`
265			`else if(ADC_RAM_DATA[3:0] == 4'd10)`
266			`data_to_ram = 16'h0400;`
267			`else if(ADC_RAM_DATA[3:0] == 4'd11)`
268			`data_to_ram = 16'h0800;`
269			`else if(ADC_RAM_DATA[3:0] == 4'd12)`
270			`data_to_ram = 16'h1000;`
271			`else if(ADC_RAM_DATA[3:0] == 4'd13)`
272			`data_to_ram = 16'h2000;`
273			`else if(ADC_RAM_DATA[3:0] == 4'd14)`
274			`data_to_ram = 16'h4000;`
275			`else if(ADC_RAM_DATA[3:0] == 4'd15)`
276			`data_to_ram = 16'h8000;`
277			`else`
278			`data_to_ram = 16'hFFFF;`
279			`end else //end bigIF`
280			`data_to_ram = 16'b0;`
281			`end else begin`
282			`data_to_ram = 16'bZ;`
283			`end`
284			`end`
285			`*/`
286			`/*`
287			`always @ (vcnt) begin`
288			`if(vcnt == 5'd00 && hcnt <= 10'd319)`
289			`data_to_ram = 16'h000F;`
290			`else`
291			`data_to_ram = 16'b0;`
292			`end`
293			`*/`
294
295			`assign ADC_RAM_CLK = CLK_50MHZ;`
296
297			`assign VGA_RAM_DATA = data_to_ram;`
298
299			`always begin`
300			`VGA_RAM_OE = 1'b1;`
301			`VGA_RAM_WE = 1'b0;`
302			`VGA_RAM_CS = 1'b0;`
303			`end`
304
305
306
307
308
309
310
311
312
313
314
315
316			`endmodule`