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[/] [alternascope/] [trunk/] [VGA/] [d_VgaRamBuffer.v] - Blame information for rev 21

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//==================================================================
// File:    d_VgaRamBuffer.v
// Version: 0.01
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Copyright Stephen Pickett
//   April 28, 2005
//------------------------------------------------------------------
// Revisions:
// Ver 0.01     Apr 28, 2005    Initial Release
//
//==================================================================
module VGADataBuffer(
    CLK_50MHZ, MASTER_RST,
    VGA_RAM_DATA, VGA_RAM_ADDR, VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS,
    VGA_RAM_ACCESS_OK,
    ADC_RAM_DATA, ADC_RAM_ADDR, ADC_RAM_CLK,
    TIME_BASE
    );
//==================================================================//
// VARIABLE DEFINITIONS                                             //
//==================================================================//
//----------------------//
// INPUTS / OUTPUTS     //
//----------------------//
input CLK_50MHZ;                // System wide clock
input MASTER_RST;               // System wide reset
 
output[15:0] VGA_RAM_DATA;
output[17:0] VGA_RAM_ADDR;
output       VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
input        VGA_RAM_ACCESS_OK;
 
input[8:0]   ADC_RAM_DATA;
output[10:0] ADC_RAM_ADDR;
output       ADC_RAM_CLK;
 
input[5:0] TIME_BASE;
 
//----------------------//
// WIRES / NODES        //
//----------------------//
wire CLK_50MHZ;                // System wide clock
wire MASTER_RST;               // System wide reset
wire[15:0] VGA_RAM_DATA;
reg[17:0] VGA_RAM_ADDR;
reg VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
wire  VGA_RAM_ACCESS_OK;
wire[8:0] ADC_RAM_DATA;
reg[10:0] ADC_RAM_ADDR;
wire ADC_RAM_CLK;
wire[5:0] TIME_BASE;
 
 
//----------------------//
// REGISTERS            //
//----------------------//
reg[4:0]  vcnt;
reg[9:0]  hcnt;
reg[15:0] data_to_ram;
reg[8:0]  adc_data_scale;
reg[10:0] TRIG_ADDR_buffered;
 
 
//==================================================================//
// FUNCTIONAL DEFINITIONS                                           //
//==================================================================//
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
    if(MASTER_RST == 1'b1) begin
        vcnt <= 5'd0;
    end else if(VGA_RAM_ACCESS_OK && hcnt != 10'd640) begin
        if(vcnt == 5'd24)
            vcnt <= 5'b0;
        else
            vcnt <= vcnt + 1'b1;
    end else begin
        vcnt <= 5'd0;
    end
end
 
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
    if(MASTER_RST == 1'b1) begin
        hcnt <= 10'd0;
    end else if(VGA_RAM_ACCESS_OK) begin
        if(hcnt == 10'd640)
            hcnt <= hcnt;
        else if(vcnt == 5'd24)
            hcnt <= hcnt + 1'b1;
        else
            hcnt <= hcnt;
    end else begin
        hcnt <= 10'b0;
    end
end
 
 
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
    if(MASTER_RST == 1'b1) begin
        ADC_RAM_ADDR <= 11'b0;
    end else if(VGA_RAM_ACCESS_OK) begin
        if((hcnt == 10'd640) || !(vcnt == 5'd24))
            ADC_RAM_ADDR <= ADC_RAM_ADDR;
        else
            ADC_RAM_ADDR <= ADC_RAM_ADDR + 1'b1;
    end else begin
        ADC_RAM_ADDR <= 11'd1727;
    end
end
 
reg[7:0] TESTING_CNT;
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
    if(MASTER_RST == 1'b1) begin
        TESTING_CNT <= 8'd0;
    end else if(VGA_RAM_ACCESS_OK) begin
        if(vcnt == 5'd24)
            TESTING_CNT <= TESTING_CNT+1;
        else
            TESTING_CNT <= TESTING_CNT;
    end else begin
        TESTING_CNT <= 8'b0;
    end
end
 
 
always @ (ADC_RAM_DATA) begin
//      adc_data_scale = TESTING_CNT + (TESTING_CNT>>1) + (TESTING_CNT>>4) + (TESTING_CNT>>6);
//      adc_data_scale = ADC_RAM_DATA + (ADC_RAM_DATA>>1) + (ADC_RAM_DATA>>4) + (ADC_RAM_DATA>>6);
      adc_data_scale = ADC_RAM_DATA;
end
 
 
 
 
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
    if(MASTER_RST == 1'b1) begin
        VGA_RAM_ADDR <= 18'b0;
    end else if(VGA_RAM_ACCESS_OK) begin
        if(hcnt == 10'd640)
            VGA_RAM_ADDR <= VGA_RAM_ADDR;
        else
            VGA_RAM_ADDR <= VGA_RAM_ADDR + 1'b1;
    end else begin
        VGA_RAM_ADDR <= 18'b0;
    end
end
/*
always @ (vcnt or VGA_RAM_ACCESS_OK or adc_data_scale) begin
    if(VGA_RAM_ACCESS_OK) begin
        if(vcnt == adc_data_scale[8:4]) begin
            data_to_ram = (adc_data_scale[3:0] == 4'd0)  & 16'h0001 |
                          (adc_data_scale[3:0] == 4'd1)  & 16'h0002 |
                          (adc_data_scale[3:0] == 4'd2)  & 16'h0004 |
                          (adc_data_scale[3:0] == 4'd3)  & 16'h0008 |
                          (adc_data_scale[3:0] == 4'd4)  & 16'h0010 |
                          (adc_data_scale[3:0] == 4'd5)  & 16'h0020 |
                          (adc_data_scale[3:0] == 4'd6)  & 16'h0040 |
                          (adc_data_scale[3:0] == 4'd7)  & 16'h0080 |
                          (adc_data_scale[3:0] == 4'd8)  & 16'h0100 |
                          (adc_data_scale[3:0] == 4'd9)  & 16'h0200 |
                          (adc_data_scale[3:0] == 4'd10) & 16'h0400 |
                          (adc_data_scale[3:0] == 4'd11) & 16'h0800 |
                          (adc_data_scale[3:0] == 4'd12) & 16'h1000 |
                          (adc_data_scale[3:0] == 4'd13) & 16'h2000 |
                          (adc_data_scale[3:0] == 4'd14) & 16'h4000 |
                          (adc_data_scale[3:0] == 4'd15) & 16'h8000;
        end else begin
            data_to_ram = 16'b0;
        end
    end else begin
        data_to_ram = 16'bZ;
    end
end
*/
 
always @ (vcnt or VGA_RAM_ACCESS_OK or adc_data_scale) begin
    if(VGA_RAM_ACCESS_OK) begin
        if(vcnt == adc_data_scale[8:4]) begin
            if(adc_data_scale[3:0] == 4'd0)
                data_to_ram = 16'h0001;
            else if(adc_data_scale[3:0] == 4'd1)
                data_to_ram = 16'h0002;
            else if(adc_data_scale[3:0] == 4'd2)
                data_to_ram = 16'h0004;
            else if(adc_data_scale[3:0] == 4'd3)
                data_to_ram = 16'h0008;
            else if(adc_data_scale[3:0] == 4'd4)
                data_to_ram = 16'h0010;
            else if(adc_data_scale[3:0] == 4'd5)
                data_to_ram = 16'h0020;
            else if(adc_data_scale[3:0] == 4'd6)
                data_to_ram = 16'h0040;
            else if(adc_data_scale[3:0] == 4'd7)
                data_to_ram = 16'h0080;
            else if(adc_data_scale[3:0] == 4'd8)
                data_to_ram = 16'h0100;
            else if(adc_data_scale[3:0] == 4'd9)
                data_to_ram = 16'h0200;
            else if(adc_data_scale[3:0] == 4'd10)
                data_to_ram = 16'h0400;
            else if(adc_data_scale[3:0] == 4'd11)
                data_to_ram = 16'h0800;
            else if(adc_data_scale[3:0] == 4'd12)
                data_to_ram = 16'h1000;
            else if(adc_data_scale[3:0] == 4'd13)
                data_to_ram = 16'h2000;
            else if(adc_data_scale[3:0] == 4'd14)
                data_to_ram = 16'h4000;
            else if(adc_data_scale[3:0] == 4'd15)
                data_to_ram = 16'h8000;
            else
                data_to_ram = 16'hFFFF;
        end else //end bigIF
            data_to_ram = 16'b0;
    end else begin
        data_to_ram = 16'bZ;
    end
end
 
/*
always @ (vcnt or VGA_RAM_ACCESS_OK or ADC_RAM_DATA) begin
    if(VGA_RAM_ACCESS_OK) begin
        if((vcnt[3:0] == ADC_RAM_DATA[7:4]) && vcnt[4] != 1'b1) begin
            if(ADC_RAM_DATA[3:0] == 4'd0)
                data_to_ram = 16'h0001;
            else if(ADC_RAM_DATA[3:0] == 4'd1)
                data_to_ram = 16'h0002;
            else if(ADC_RAM_DATA[3:0] == 4'd2)
                data_to_ram = 16'h0004;
            else if(ADC_RAM_DATA[3:0] == 4'd3)
                data_to_ram = 16'h0008;
            else if(ADC_RAM_DATA[3:0] == 4'd4)
                data_to_ram = 16'h0010;
            else if(ADC_RAM_DATA[3:0] == 4'd5)
                data_to_ram = 16'h0020;
            else if(ADC_RAM_DATA[3:0] == 4'd6)
                data_to_ram = 16'h0040;
            else if(ADC_RAM_DATA[3:0] == 4'd7)
                data_to_ram = 16'h0080;
            else if(ADC_RAM_DATA[3:0] == 4'd8)
                data_to_ram = 16'h0100;
            else if(ADC_RAM_DATA[3:0] == 4'd9)
                data_to_ram = 16'h0200;
            else if(ADC_RAM_DATA[3:0] == 4'd10)
                data_to_ram = 16'h0400;
            else if(ADC_RAM_DATA[3:0] == 4'd11)
                data_to_ram = 16'h0800;
            else if(ADC_RAM_DATA[3:0] == 4'd12)
                data_to_ram = 16'h1000;
            else if(ADC_RAM_DATA[3:0] == 4'd13)
                data_to_ram = 16'h2000;
            else if(ADC_RAM_DATA[3:0] == 4'd14)
                data_to_ram = 16'h4000;
            else if(ADC_RAM_DATA[3:0] == 4'd15)
                data_to_ram = 16'h8000;
            else
                data_to_ram = 16'hFFFF;
        end else //end bigIF
            data_to_ram = 16'b0;
    end else begin
        data_to_ram = 16'bZ;
    end
end
*/
/*
always @ (vcnt) begin
    if(vcnt == 5'd00 && hcnt <= 10'd319)
        data_to_ram = 16'h000F;
    else
        data_to_ram = 16'b0;
end
*/
 
assign ADC_RAM_CLK = CLK_50MHZ;
 
assign VGA_RAM_DATA = data_to_ram;
 
always begin
    VGA_RAM_OE = 1'b1;
    VGA_RAM_WE = 1'b0;
    VGA_RAM_CS = 1'b0;
end
 
 
 
 
 
 
 
 
 
 
 
 
endmodule

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[/] [alternascope/] [trunk/] [VGA/] [d_VgaRamBuffer.v] - Blame information for rev 21

Line No.	Rev	Author	Line
1	2	smpickett	`//==================================================================`
2			`// File: d_VgaRamBuffer.v`
3			`// Version: 0.01`
4			`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
5			`// Copyright Stephen Pickett`
6			`// April 28, 2005`
7			`//------------------------------------------------------------------`
8			`// Revisions:`
9			`// Ver 0.01 Apr 28, 2005 Initial Release`
10			`//`
11			`//==================================================================`
12			`module VGADataBuffer(`
13			`CLK_50MHZ, MASTER_RST,`
14			`VGA_RAM_DATA, VGA_RAM_ADDR, VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS,`
15			`VGA_RAM_ACCESS_OK,`
16			`ADC_RAM_DATA, ADC_RAM_ADDR, ADC_RAM_CLK,`
17	21	smpickett	`TIME_BASE`
18	2	smpickett	`);`
19			`//==================================================================//`
20			`// VARIABLE DEFINITIONS //`
21			`//==================================================================//`
22			`//----------------------//`
23			`// INPUTS / OUTPUTS //`
24			`//----------------------//`
25			`input CLK_50MHZ; // System wide clock`
26			`input MASTER_RST; // System wide reset`
27
28			`output[15:0] VGA_RAM_DATA;`
29			`output[17:0] VGA_RAM_ADDR;`
30			`output VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;`
31			`input VGA_RAM_ACCESS_OK;`
32
33	21	smpickett	`input[8:0] ADC_RAM_DATA;`
34	2	smpickett	`output[10:0] ADC_RAM_ADDR;`
35			`output ADC_RAM_CLK;`
36
37			`input[5:0] TIME_BASE;`
38
39			`//----------------------//`
40			`// WIRES / NODES //`
41			`//----------------------//`
42			`wire CLK_50MHZ; // System wide clock`
43			`wire MASTER_RST; // System wide reset`
44			`wire[15:0] VGA_RAM_DATA;`
45			`reg[17:0] VGA_RAM_ADDR;`
46			`reg VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;`
47			`wire VGA_RAM_ACCESS_OK;`
48	21	smpickett	`wire[8:0] ADC_RAM_DATA;`
49	2	smpickett	`reg[10:0] ADC_RAM_ADDR;`
50			`wire ADC_RAM_CLK;`
51			`wire[5:0] TIME_BASE;`
52
53
54			`//----------------------//`
55			`// REGISTERS //`
56			`//----------------------//`
57			`reg[4:0] vcnt;`
58			`reg[9:0] hcnt;`
59			`reg[15:0] data_to_ram;`
60			`reg[8:0] adc_data_scale;`
61			`reg[10:0] TRIG_ADDR_buffered;`
62
63
64			`//==================================================================//`
65			`// FUNCTIONAL DEFINITIONS //`
66			`//==================================================================//`
67			`always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin`
68			`if(MASTER_RST == 1'b1) begin`
69			`vcnt <= 5'd0;`
70			`end else if(VGA_RAM_ACCESS_OK && hcnt != 10'd640) begin`
71			`if(vcnt == 5'd24)`
72			`vcnt <= 5'b0;`
73			`else`
74			`vcnt <= vcnt + 1'b1;`
75			`end else begin`
76			`vcnt <= 5'd0;`
77			`end`
78			`end`
79
80			`always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin`
81			`if(MASTER_RST == 1'b1) begin`
82			`hcnt <= 10'd0;`
83			`end else if(VGA_RAM_ACCESS_OK) begin`
84			`if(hcnt == 10'd640)`
85			`hcnt <= hcnt;`
86			`else if(vcnt == 5'd24)`
87			`hcnt <= hcnt + 1'b1;`
88			`else`
89			`hcnt <= hcnt;`
90			`end else begin`
91			`hcnt <= 10'b0;`
92			`end`
93			`end`
94
95
96			`always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin`
97			`if(MASTER_RST == 1'b1) begin`
98			`ADC_RAM_ADDR <= 11'b0;`
99			`end else if(VGA_RAM_ACCESS_OK) begin`
100			`if((hcnt == 10'd640) \|\| !(vcnt == 5'd24))`
101			`ADC_RAM_ADDR <= ADC_RAM_ADDR;`
102			`else`
103			`ADC_RAM_ADDR <= ADC_RAM_ADDR + 1'b1;`
104			`end else begin`
105	21	smpickett	`ADC_RAM_ADDR <= 11'd1727;`
106	2	smpickett	`end`
107			`end`
108
109	17	smpickett	`reg[7:0] TESTING_CNT;`
110			`always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin`
111			`if(MASTER_RST == 1'b1) begin`
112			`TESTING_CNT <= 8'd0;`
113			`end else if(VGA_RAM_ACCESS_OK) begin`
114			`if(vcnt == 5'd24)`
115			`TESTING_CNT <= TESTING_CNT+1;`
116			`else`
117			`TESTING_CNT <= TESTING_CNT;`
118			`end else begin`
119			`TESTING_CNT <= 8'b0;`
120			`end`
121			`end`
122
123
124	2	smpickett	`always @ (ADC_RAM_DATA) begin`
125	17	smpickett	`// adc_data_scale = TESTING_CNT + (TESTING_CNT>>1) + (TESTING_CNT>>4) + (TESTING_CNT>>6);`
126			`// adc_data_scale = ADC_RAM_DATA + (ADC_RAM_DATA>>1) + (ADC_RAM_DATA>>4) + (ADC_RAM_DATA>>6);`
127			`adc_data_scale = ADC_RAM_DATA;`
128	2	smpickett	`end`
129
130
131	17	smpickett
132
133	2	smpickett	`always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin`
134			`if(MASTER_RST == 1'b1) begin`
135			`VGA_RAM_ADDR <= 18'b0;`
136			`end else if(VGA_RAM_ACCESS_OK) begin`
137			`if(hcnt == 10'd640)`
138			`VGA_RAM_ADDR <= VGA_RAM_ADDR;`
139			`else`
140			`VGA_RAM_ADDR <= VGA_RAM_ADDR + 1'b1;`
141			`end else begin`
142			`VGA_RAM_ADDR <= 18'b0;`
143			`end`
144			`end`
145			`/*`
146			`always @ (vcnt or VGA_RAM_ACCESS_OK or adc_data_scale) begin`
147			`if(VGA_RAM_ACCESS_OK) begin`
148			`if(vcnt == adc_data_scale[8:4]) begin`
149			`data_to_ram = (adc_data_scale[3:0] == 4'd0) & 16'h0001 \|`
150			`(adc_data_scale[3:0] == 4'd1) & 16'h0002 \|`
151			`(adc_data_scale[3:0] == 4'd2) & 16'h0004 \|`
152			`(adc_data_scale[3:0] == 4'd3) & 16'h0008 \|`
153			`(adc_data_scale[3:0] == 4'd4) & 16'h0010 \|`
154			`(adc_data_scale[3:0] == 4'd5) & 16'h0020 \|`
155			`(adc_data_scale[3:0] == 4'd6) & 16'h0040 \|`
156			`(adc_data_scale[3:0] == 4'd7) & 16'h0080 \|`
157			`(adc_data_scale[3:0] == 4'd8) & 16'h0100 \|`
158			`(adc_data_scale[3:0] == 4'd9) & 16'h0200 \|`
159			`(adc_data_scale[3:0] == 4'd10) & 16'h0400 \|`
160			`(adc_data_scale[3:0] == 4'd11) & 16'h0800 \|`
161			`(adc_data_scale[3:0] == 4'd12) & 16'h1000 \|`
162			`(adc_data_scale[3:0] == 4'd13) & 16'h2000 \|`
163			`(adc_data_scale[3:0] == 4'd14) & 16'h4000 \|`
164			`(adc_data_scale[3:0] == 4'd15) & 16'h8000;`
165			`end else begin`
166			`data_to_ram = 16'b0;`
167			`end`
168			`end else begin`
169			`data_to_ram = 16'bZ;`
170			`end`
171			`end`
172			`*/`
173
174			`always @ (vcnt or VGA_RAM_ACCESS_OK or adc_data_scale) begin`
175			`if(VGA_RAM_ACCESS_OK) begin`
176			`if(vcnt == adc_data_scale[8:4]) begin`
177			`if(adc_data_scale[3:0] == 4'd0)`
178			`data_to_ram = 16'h0001;`
179			`else if(adc_data_scale[3:0] == 4'd1)`
180			`data_to_ram = 16'h0002;`
181			`else if(adc_data_scale[3:0] == 4'd2)`
182			`data_to_ram = 16'h0004;`
183			`else if(adc_data_scale[3:0] == 4'd3)`
184			`data_to_ram = 16'h0008;`
185			`else if(adc_data_scale[3:0] == 4'd4)`
186			`data_to_ram = 16'h0010;`
187			`else if(adc_data_scale[3:0] == 4'd5)`
188			`data_to_ram = 16'h0020;`
189			`else if(adc_data_scale[3:0] == 4'd6)`
190			`data_to_ram = 16'h0040;`
191			`else if(adc_data_scale[3:0] == 4'd7)`
192			`data_to_ram = 16'h0080;`
193			`else if(adc_data_scale[3:0] == 4'd8)`
194			`data_to_ram = 16'h0100;`
195			`else if(adc_data_scale[3:0] == 4'd9)`
196			`data_to_ram = 16'h0200;`
197			`else if(adc_data_scale[3:0] == 4'd10)`
198			`data_to_ram = 16'h0400;`
199			`else if(adc_data_scale[3:0] == 4'd11)`
200			`data_to_ram = 16'h0800;`
201			`else if(adc_data_scale[3:0] == 4'd12)`
202			`data_to_ram = 16'h1000;`
203			`else if(adc_data_scale[3:0] == 4'd13)`
204			`data_to_ram = 16'h2000;`
205			`else if(adc_data_scale[3:0] == 4'd14)`
206			`data_to_ram = 16'h4000;`
207			`else if(adc_data_scale[3:0] == 4'd15)`
208			`data_to_ram = 16'h8000;`
209			`else`
210			`data_to_ram = 16'hFFFF;`
211			`end else //end bigIF`
212			`data_to_ram = 16'b0;`
213			`end else begin`
214			`data_to_ram = 16'bZ;`
215			`end`
216			`end`
217
218			`/*`
219			`always @ (vcnt or VGA_RAM_ACCESS_OK or ADC_RAM_DATA) begin`
220			`if(VGA_RAM_ACCESS_OK) begin`
221			`if((vcnt[3:0] == ADC_RAM_DATA[7:4]) && vcnt[4] != 1'b1) begin`
222			`if(ADC_RAM_DATA[3:0] == 4'd0)`
223			`data_to_ram = 16'h0001;`
224			`else if(ADC_RAM_DATA[3:0] == 4'd1)`
225			`data_to_ram = 16'h0002;`
226			`else if(ADC_RAM_DATA[3:0] == 4'd2)`
227			`data_to_ram = 16'h0004;`
228			`else if(ADC_RAM_DATA[3:0] == 4'd3)`
229			`data_to_ram = 16'h0008;`
230			`else if(ADC_RAM_DATA[3:0] == 4'd4)`
231			`data_to_ram = 16'h0010;`
232			`else if(ADC_RAM_DATA[3:0] == 4'd5)`
233			`data_to_ram = 16'h0020;`
234			`else if(ADC_RAM_DATA[3:0] == 4'd6)`
235			`data_to_ram = 16'h0040;`
236			`else if(ADC_RAM_DATA[3:0] == 4'd7)`
237			`data_to_ram = 16'h0080;`
238			`else if(ADC_RAM_DATA[3:0] == 4'd8)`
239			`data_to_ram = 16'h0100;`
240			`else if(ADC_RAM_DATA[3:0] == 4'd9)`
241			`data_to_ram = 16'h0200;`
242			`else if(ADC_RAM_DATA[3:0] == 4'd10)`
243			`data_to_ram = 16'h0400;`
244			`else if(ADC_RAM_DATA[3:0] == 4'd11)`
245			`data_to_ram = 16'h0800;`
246			`else if(ADC_RAM_DATA[3:0] == 4'd12)`
247			`data_to_ram = 16'h1000;`
248			`else if(ADC_RAM_DATA[3:0] == 4'd13)`
249			`data_to_ram = 16'h2000;`
250			`else if(ADC_RAM_DATA[3:0] == 4'd14)`
251			`data_to_ram = 16'h4000;`
252			`else if(ADC_RAM_DATA[3:0] == 4'd15)`
253			`data_to_ram = 16'h8000;`
254			`else`
255			`data_to_ram = 16'hFFFF;`
256			`end else //end bigIF`
257			`data_to_ram = 16'b0;`
258			`end else begin`
259			`data_to_ram = 16'bZ;`
260			`end`
261			`end`
262			`*/`
263			`/*`
264			`always @ (vcnt) begin`
265			`if(vcnt == 5'd00 && hcnt <= 10'd319)`
266			`data_to_ram = 16'h000F;`
267			`else`
268			`data_to_ram = 16'b0;`
269			`end`
270			`*/`
271
272			`assign ADC_RAM_CLK = CLK_50MHZ;`
273
274			`assign VGA_RAM_DATA = data_to_ram;`
275
276			`always begin`
277			`VGA_RAM_OE = 1'b1;`
278			`VGA_RAM_WE = 1'b0;`
279			`VGA_RAM_CS = 1'b0;`
280			`end`
281
282
283
284
285
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287
288
289
290
291
292
293			`endmodule`