1 |
35 |
ultra_embe |
/* Generated automatically by gengenrtl from rtl.def. */
|
2 |
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|
3 |
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#ifndef GCC_GENRTL_H
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4 |
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#define GCC_GENRTL_H
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5 |
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|
6 |
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#include "statistics.h"
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7 |
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|
8 |
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static inline rtx
|
9 |
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gen_rtx_fmt_0_stat (RTX_CODE code, enum machine_mode mode MEM_STAT_DECL)
|
10 |
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|
{
|
11 |
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|
rtx rt;
|
12 |
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rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
13 |
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|
|
14 |
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|
PUT_MODE (rt, mode);
|
15 |
|
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X0EXP (rt, 0) = NULL_RTX;
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16 |
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|
|
17 |
|
|
return rt;
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18 |
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}
|
19 |
|
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|
20 |
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#define gen_rtx_fmt_0(c, m)\
|
21 |
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gen_rtx_fmt_0_stat (c, m MEM_STAT_INFO)
|
22 |
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|
23 |
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static inline rtx
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24 |
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gen_rtx_fmt_ee_stat (RTX_CODE code, enum machine_mode mode,
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25 |
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rtx arg0,
|
26 |
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rtx arg1 MEM_STAT_DECL)
|
27 |
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{
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28 |
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rtx rt;
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29 |
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rt = rtx_alloc_stat (code PASS_MEM_STAT);
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30 |
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|
31 |
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PUT_MODE (rt, mode);
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32 |
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XEXP (rt, 0) = arg0;
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33 |
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XEXP (rt, 1) = arg1;
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34 |
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|
35 |
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return rt;
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36 |
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}
|
37 |
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|
38 |
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#define gen_rtx_fmt_ee(c, m, p0, p1)\
|
39 |
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gen_rtx_fmt_ee_stat (c, m, p0, p1 MEM_STAT_INFO)
|
40 |
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|
41 |
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static inline rtx
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42 |
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gen_rtx_fmt_ue_stat (RTX_CODE code, enum machine_mode mode,
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43 |
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rtx arg0,
|
44 |
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rtx arg1 MEM_STAT_DECL)
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45 |
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{
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46 |
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rtx rt;
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47 |
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rt = rtx_alloc_stat (code PASS_MEM_STAT);
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48 |
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|
49 |
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PUT_MODE (rt, mode);
|
50 |
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XEXP (rt, 0) = arg0;
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51 |
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XEXP (rt, 1) = arg1;
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52 |
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|
53 |
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return rt;
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54 |
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}
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55 |
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|
56 |
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#define gen_rtx_fmt_ue(c, m, p0, p1)\
|
57 |
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gen_rtx_fmt_ue_stat (c, m, p0, p1 MEM_STAT_INFO)
|
58 |
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|
59 |
|
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static inline rtx
|
60 |
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gen_rtx_fmt_E_stat (RTX_CODE code, enum machine_mode mode,
|
61 |
|
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rtvec arg0 MEM_STAT_DECL)
|
62 |
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{
|
63 |
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rtx rt;
|
64 |
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rt = rtx_alloc_stat (code PASS_MEM_STAT);
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65 |
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|
66 |
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PUT_MODE (rt, mode);
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67 |
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XVEC (rt, 0) = arg0;
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68 |
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|
|
69 |
|
|
return rt;
|
70 |
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}
|
71 |
|
|
|
72 |
|
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#define gen_rtx_fmt_E(c, m, p0)\
|
73 |
|
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gen_rtx_fmt_E_stat (c, m, p0 MEM_STAT_INFO)
|
74 |
|
|
|
75 |
|
|
static inline rtx
|
76 |
|
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gen_rtx_fmt_i_stat (RTX_CODE code, enum machine_mode mode,
|
77 |
|
|
int arg0 MEM_STAT_DECL)
|
78 |
|
|
{
|
79 |
|
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rtx rt;
|
80 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
81 |
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|
|
82 |
|
|
PUT_MODE (rt, mode);
|
83 |
|
|
XINT (rt, 0) = arg0;
|
84 |
|
|
|
85 |
|
|
return rt;
|
86 |
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|
}
|
87 |
|
|
|
88 |
|
|
#define gen_rtx_fmt_i(c, m, p0)\
|
89 |
|
|
gen_rtx_fmt_i_stat (c, m, p0 MEM_STAT_INFO)
|
90 |
|
|
|
91 |
|
|
static inline rtx
|
92 |
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gen_rtx_fmt_iuuBeiie_stat (RTX_CODE code, enum machine_mode mode,
|
93 |
|
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int arg0,
|
94 |
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rtx arg1,
|
95 |
|
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rtx arg2,
|
96 |
|
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basic_block arg3,
|
97 |
|
|
rtx arg4,
|
98 |
|
|
int arg5,
|
99 |
|
|
int arg6,
|
100 |
|
|
rtx arg7 MEM_STAT_DECL)
|
101 |
|
|
{
|
102 |
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|
rtx rt;
|
103 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
104 |
|
|
|
105 |
|
|
PUT_MODE (rt, mode);
|
106 |
|
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XINT (rt, 0) = arg0;
|
107 |
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XEXP (rt, 1) = arg1;
|
108 |
|
|
XEXP (rt, 2) = arg2;
|
109 |
|
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XBBDEF (rt, 3) = arg3;
|
110 |
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XEXP (rt, 4) = arg4;
|
111 |
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XINT (rt, 5) = arg5;
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112 |
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XINT (rt, 6) = arg6;
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113 |
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XEXP (rt, 7) = arg7;
|
114 |
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|
|
115 |
|
|
return rt;
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116 |
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}
|
117 |
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|
118 |
|
|
#define gen_rtx_fmt_iuuBeiie(c, m, p0, p1, p2, p3, p4, p5, p6, p7)\
|
119 |
|
|
gen_rtx_fmt_iuuBeiie_stat (c, m, p0, p1, p2, p3, p4, p5, p6, p7 MEM_STAT_INFO)
|
120 |
|
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|
121 |
|
|
static inline rtx
|
122 |
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gen_rtx_fmt_iuuBeiie0_stat (RTX_CODE code, enum machine_mode mode,
|
123 |
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int arg0,
|
124 |
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rtx arg1,
|
125 |
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rtx arg2,
|
126 |
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basic_block arg3,
|
127 |
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rtx arg4,
|
128 |
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int arg5,
|
129 |
|
|
int arg6,
|
130 |
|
|
rtx arg7 MEM_STAT_DECL)
|
131 |
|
|
{
|
132 |
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|
rtx rt;
|
133 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
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134 |
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|
135 |
|
|
PUT_MODE (rt, mode);
|
136 |
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|
XINT (rt, 0) = arg0;
|
137 |
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XEXP (rt, 1) = arg1;
|
138 |
|
|
XEXP (rt, 2) = arg2;
|
139 |
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|
XBBDEF (rt, 3) = arg3;
|
140 |
|
|
XEXP (rt, 4) = arg4;
|
141 |
|
|
XINT (rt, 5) = arg5;
|
142 |
|
|
XINT (rt, 6) = arg6;
|
143 |
|
|
XEXP (rt, 7) = arg7;
|
144 |
|
|
X0EXP (rt, 8) = NULL_RTX;
|
145 |
|
|
|
146 |
|
|
return rt;
|
147 |
|
|
}
|
148 |
|
|
|
149 |
|
|
#define gen_rtx_fmt_iuuBeiie0(c, m, p0, p1, p2, p3, p4, p5, p6, p7)\
|
150 |
|
|
gen_rtx_fmt_iuuBeiie0_stat (c, m, p0, p1, p2, p3, p4, p5, p6, p7 MEM_STAT_INFO)
|
151 |
|
|
|
152 |
|
|
static inline rtx
|
153 |
|
|
gen_rtx_fmt_iuuBeiiee_stat (RTX_CODE code, enum machine_mode mode,
|
154 |
|
|
int arg0,
|
155 |
|
|
rtx arg1,
|
156 |
|
|
rtx arg2,
|
157 |
|
|
basic_block arg3,
|
158 |
|
|
rtx arg4,
|
159 |
|
|
int arg5,
|
160 |
|
|
int arg6,
|
161 |
|
|
rtx arg7,
|
162 |
|
|
rtx arg8 MEM_STAT_DECL)
|
163 |
|
|
{
|
164 |
|
|
rtx rt;
|
165 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
166 |
|
|
|
167 |
|
|
PUT_MODE (rt, mode);
|
168 |
|
|
XINT (rt, 0) = arg0;
|
169 |
|
|
XEXP (rt, 1) = arg1;
|
170 |
|
|
XEXP (rt, 2) = arg2;
|
171 |
|
|
XBBDEF (rt, 3) = arg3;
|
172 |
|
|
XEXP (rt, 4) = arg4;
|
173 |
|
|
XINT (rt, 5) = arg5;
|
174 |
|
|
XINT (rt, 6) = arg6;
|
175 |
|
|
XEXP (rt, 7) = arg7;
|
176 |
|
|
XEXP (rt, 8) = arg8;
|
177 |
|
|
|
178 |
|
|
return rt;
|
179 |
|
|
}
|
180 |
|
|
|
181 |
|
|
#define gen_rtx_fmt_iuuBeiiee(c, m, p0, p1, p2, p3, p4, p5, p6, p7, p8)\
|
182 |
|
|
gen_rtx_fmt_iuuBeiiee_stat (c, m, p0, p1, p2, p3, p4, p5, p6, p7, p8 MEM_STAT_INFO)
|
183 |
|
|
|
184 |
|
|
static inline rtx
|
185 |
|
|
gen_rtx_fmt_iuu00000_stat (RTX_CODE code, enum machine_mode mode,
|
186 |
|
|
int arg0,
|
187 |
|
|
rtx arg1,
|
188 |
|
|
rtx arg2 MEM_STAT_DECL)
|
189 |
|
|
{
|
190 |
|
|
rtx rt;
|
191 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
192 |
|
|
|
193 |
|
|
PUT_MODE (rt, mode);
|
194 |
|
|
XINT (rt, 0) = arg0;
|
195 |
|
|
XEXP (rt, 1) = arg1;
|
196 |
|
|
XEXP (rt, 2) = arg2;
|
197 |
|
|
X0EXP (rt, 3) = NULL_RTX;
|
198 |
|
|
X0EXP (rt, 4) = NULL_RTX;
|
199 |
|
|
X0EXP (rt, 5) = NULL_RTX;
|
200 |
|
|
X0EXP (rt, 6) = NULL_RTX;
|
201 |
|
|
X0EXP (rt, 7) = NULL_RTX;
|
202 |
|
|
|
203 |
|
|
return rt;
|
204 |
|
|
}
|
205 |
|
|
|
206 |
|
|
#define gen_rtx_fmt_iuu00000(c, m, p0, p1, p2)\
|
207 |
|
|
gen_rtx_fmt_iuu00000_stat (c, m, p0, p1, p2 MEM_STAT_INFO)
|
208 |
|
|
|
209 |
|
|
static inline rtx
|
210 |
|
|
gen_rtx_fmt_iuuB00is_stat (RTX_CODE code, enum machine_mode mode,
|
211 |
|
|
int arg0,
|
212 |
|
|
rtx arg1,
|
213 |
|
|
rtx arg2,
|
214 |
|
|
basic_block arg3,
|
215 |
|
|
int arg4,
|
216 |
|
|
const char *arg5 MEM_STAT_DECL)
|
217 |
|
|
{
|
218 |
|
|
rtx rt;
|
219 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
220 |
|
|
|
221 |
|
|
PUT_MODE (rt, mode);
|
222 |
|
|
XINT (rt, 0) = arg0;
|
223 |
|
|
XEXP (rt, 1) = arg1;
|
224 |
|
|
XEXP (rt, 2) = arg2;
|
225 |
|
|
XBBDEF (rt, 3) = arg3;
|
226 |
|
|
X0EXP (rt, 4) = NULL_RTX;
|
227 |
|
|
X0EXP (rt, 5) = NULL_RTX;
|
228 |
|
|
XINT (rt, 6) = arg4;
|
229 |
|
|
XSTR (rt, 7) = arg5;
|
230 |
|
|
|
231 |
|
|
return rt;
|
232 |
|
|
}
|
233 |
|
|
|
234 |
|
|
#define gen_rtx_fmt_iuuB00is(c, m, p0, p1, p2, p3, p4, p5)\
|
235 |
|
|
gen_rtx_fmt_iuuB00is_stat (c, m, p0, p1, p2, p3, p4, p5 MEM_STAT_INFO)
|
236 |
|
|
|
237 |
|
|
static inline rtx
|
238 |
|
|
gen_rtx_fmt_si_stat (RTX_CODE code, enum machine_mode mode,
|
239 |
|
|
const char *arg0,
|
240 |
|
|
int arg1 MEM_STAT_DECL)
|
241 |
|
|
{
|
242 |
|
|
rtx rt;
|
243 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
244 |
|
|
|
245 |
|
|
PUT_MODE (rt, mode);
|
246 |
|
|
XSTR (rt, 0) = arg0;
|
247 |
|
|
XINT (rt, 1) = arg1;
|
248 |
|
|
|
249 |
|
|
return rt;
|
250 |
|
|
}
|
251 |
|
|
|
252 |
|
|
#define gen_rtx_fmt_si(c, m, p0, p1)\
|
253 |
|
|
gen_rtx_fmt_si_stat (c, m, p0, p1 MEM_STAT_INFO)
|
254 |
|
|
|
255 |
|
|
static inline rtx
|
256 |
|
|
gen_rtx_fmt_ssiEEEi_stat (RTX_CODE code, enum machine_mode mode,
|
257 |
|
|
const char *arg0,
|
258 |
|
|
const char *arg1,
|
259 |
|
|
int arg2,
|
260 |
|
|
rtvec arg3,
|
261 |
|
|
rtvec arg4,
|
262 |
|
|
rtvec arg5,
|
263 |
|
|
int arg6 MEM_STAT_DECL)
|
264 |
|
|
{
|
265 |
|
|
rtx rt;
|
266 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
267 |
|
|
|
268 |
|
|
PUT_MODE (rt, mode);
|
269 |
|
|
XSTR (rt, 0) = arg0;
|
270 |
|
|
XSTR (rt, 1) = arg1;
|
271 |
|
|
XINT (rt, 2) = arg2;
|
272 |
|
|
XVEC (rt, 3) = arg3;
|
273 |
|
|
XVEC (rt, 4) = arg4;
|
274 |
|
|
XVEC (rt, 5) = arg5;
|
275 |
|
|
XINT (rt, 6) = arg6;
|
276 |
|
|
|
277 |
|
|
return rt;
|
278 |
|
|
}
|
279 |
|
|
|
280 |
|
|
#define gen_rtx_fmt_ssiEEEi(c, m, p0, p1, p2, p3, p4, p5, p6)\
|
281 |
|
|
gen_rtx_fmt_ssiEEEi_stat (c, m, p0, p1, p2, p3, p4, p5, p6 MEM_STAT_INFO)
|
282 |
|
|
|
283 |
|
|
static inline rtx
|
284 |
|
|
gen_rtx_fmt_Ei_stat (RTX_CODE code, enum machine_mode mode,
|
285 |
|
|
rtvec arg0,
|
286 |
|
|
int arg1 MEM_STAT_DECL)
|
287 |
|
|
{
|
288 |
|
|
rtx rt;
|
289 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
290 |
|
|
|
291 |
|
|
PUT_MODE (rt, mode);
|
292 |
|
|
XVEC (rt, 0) = arg0;
|
293 |
|
|
XINT (rt, 1) = arg1;
|
294 |
|
|
|
295 |
|
|
return rt;
|
296 |
|
|
}
|
297 |
|
|
|
298 |
|
|
#define gen_rtx_fmt_Ei(c, m, p0, p1)\
|
299 |
|
|
gen_rtx_fmt_Ei_stat (c, m, p0, p1 MEM_STAT_INFO)
|
300 |
|
|
|
301 |
|
|
static inline rtx
|
302 |
|
|
gen_rtx_fmt_eEee0_stat (RTX_CODE code, enum machine_mode mode,
|
303 |
|
|
rtx arg0,
|
304 |
|
|
rtvec arg1,
|
305 |
|
|
rtx arg2,
|
306 |
|
|
rtx arg3 MEM_STAT_DECL)
|
307 |
|
|
{
|
308 |
|
|
rtx rt;
|
309 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
310 |
|
|
|
311 |
|
|
PUT_MODE (rt, mode);
|
312 |
|
|
XEXP (rt, 0) = arg0;
|
313 |
|
|
XVEC (rt, 1) = arg1;
|
314 |
|
|
XEXP (rt, 2) = arg2;
|
315 |
|
|
XEXP (rt, 3) = arg3;
|
316 |
|
|
X0EXP (rt, 4) = NULL_RTX;
|
317 |
|
|
|
318 |
|
|
return rt;
|
319 |
|
|
}
|
320 |
|
|
|
321 |
|
|
#define gen_rtx_fmt_eEee0(c, m, p0, p1, p2, p3)\
|
322 |
|
|
gen_rtx_fmt_eEee0_stat (c, m, p0, p1, p2, p3 MEM_STAT_INFO)
|
323 |
|
|
|
324 |
|
|
static inline rtx
|
325 |
|
|
gen_rtx_fmt_eee_stat (RTX_CODE code, enum machine_mode mode,
|
326 |
|
|
rtx arg0,
|
327 |
|
|
rtx arg1,
|
328 |
|
|
rtx arg2 MEM_STAT_DECL)
|
329 |
|
|
{
|
330 |
|
|
rtx rt;
|
331 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
332 |
|
|
|
333 |
|
|
PUT_MODE (rt, mode);
|
334 |
|
|
XEXP (rt, 0) = arg0;
|
335 |
|
|
XEXP (rt, 1) = arg1;
|
336 |
|
|
XEXP (rt, 2) = arg2;
|
337 |
|
|
|
338 |
|
|
return rt;
|
339 |
|
|
}
|
340 |
|
|
|
341 |
|
|
#define gen_rtx_fmt_eee(c, m, p0, p1, p2)\
|
342 |
|
|
gen_rtx_fmt_eee_stat (c, m, p0, p1, p2 MEM_STAT_INFO)
|
343 |
|
|
|
344 |
|
|
static inline rtx
|
345 |
|
|
gen_rtx_fmt_e_stat (RTX_CODE code, enum machine_mode mode,
|
346 |
|
|
rtx arg0 MEM_STAT_DECL)
|
347 |
|
|
{
|
348 |
|
|
rtx rt;
|
349 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
350 |
|
|
|
351 |
|
|
PUT_MODE (rt, mode);
|
352 |
|
|
XEXP (rt, 0) = arg0;
|
353 |
|
|
|
354 |
|
|
return rt;
|
355 |
|
|
}
|
356 |
|
|
|
357 |
|
|
#define gen_rtx_fmt_e(c, m, p0)\
|
358 |
|
|
gen_rtx_fmt_e_stat (c, m, p0 MEM_STAT_INFO)
|
359 |
|
|
|
360 |
|
|
static inline rtx
|
361 |
|
|
gen_rtx_fmt__stat (RTX_CODE code, enum machine_mode mode MEM_STAT_DECL)
|
362 |
|
|
{
|
363 |
|
|
rtx rt;
|
364 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
365 |
|
|
|
366 |
|
|
PUT_MODE (rt, mode);
|
367 |
|
|
|
368 |
|
|
return rt;
|
369 |
|
|
}
|
370 |
|
|
|
371 |
|
|
#define gen_rtx_fmt_(c, m)\
|
372 |
|
|
gen_rtx_fmt__stat (c, m MEM_STAT_INFO)
|
373 |
|
|
|
374 |
|
|
static inline rtx
|
375 |
|
|
gen_rtx_fmt_w_stat (RTX_CODE code, enum machine_mode mode,
|
376 |
|
|
HOST_WIDE_INT arg0 MEM_STAT_DECL)
|
377 |
|
|
{
|
378 |
|
|
rtx rt;
|
379 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
380 |
|
|
|
381 |
|
|
PUT_MODE (rt, mode);
|
382 |
|
|
XWINT (rt, 0) = arg0;
|
383 |
|
|
|
384 |
|
|
return rt;
|
385 |
|
|
}
|
386 |
|
|
|
387 |
|
|
#define gen_rtx_fmt_w(c, m, p0)\
|
388 |
|
|
gen_rtx_fmt_w_stat (c, m, p0 MEM_STAT_INFO)
|
389 |
|
|
|
390 |
|
|
static inline rtx
|
391 |
|
|
gen_rtx_fmt_www_stat (RTX_CODE code, enum machine_mode mode,
|
392 |
|
|
HOST_WIDE_INT arg0,
|
393 |
|
|
HOST_WIDE_INT arg1,
|
394 |
|
|
HOST_WIDE_INT arg2 MEM_STAT_DECL)
|
395 |
|
|
{
|
396 |
|
|
rtx rt;
|
397 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
398 |
|
|
|
399 |
|
|
PUT_MODE (rt, mode);
|
400 |
|
|
XWINT (rt, 0) = arg0;
|
401 |
|
|
XWINT (rt, 1) = arg1;
|
402 |
|
|
XWINT (rt, 2) = arg2;
|
403 |
|
|
|
404 |
|
|
return rt;
|
405 |
|
|
}
|
406 |
|
|
|
407 |
|
|
#define gen_rtx_fmt_www(c, m, p0, p1, p2)\
|
408 |
|
|
gen_rtx_fmt_www_stat (c, m, p0, p1, p2 MEM_STAT_INFO)
|
409 |
|
|
|
410 |
|
|
static inline rtx
|
411 |
|
|
gen_rtx_fmt_s_stat (RTX_CODE code, enum machine_mode mode,
|
412 |
|
|
const char *arg0 MEM_STAT_DECL)
|
413 |
|
|
{
|
414 |
|
|
rtx rt;
|
415 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
416 |
|
|
|
417 |
|
|
PUT_MODE (rt, mode);
|
418 |
|
|
XSTR (rt, 0) = arg0;
|
419 |
|
|
|
420 |
|
|
return rt;
|
421 |
|
|
}
|
422 |
|
|
|
423 |
|
|
#define gen_rtx_fmt_s(c, m, p0)\
|
424 |
|
|
gen_rtx_fmt_s_stat (c, m, p0 MEM_STAT_INFO)
|
425 |
|
|
|
426 |
|
|
static inline rtx
|
427 |
|
|
gen_rtx_fmt_i00_stat (RTX_CODE code, enum machine_mode mode,
|
428 |
|
|
int arg0 MEM_STAT_DECL)
|
429 |
|
|
{
|
430 |
|
|
rtx rt;
|
431 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
432 |
|
|
|
433 |
|
|
PUT_MODE (rt, mode);
|
434 |
|
|
XINT (rt, 0) = arg0;
|
435 |
|
|
X0EXP (rt, 1) = NULL_RTX;
|
436 |
|
|
X0EXP (rt, 2) = NULL_RTX;
|
437 |
|
|
|
438 |
|
|
return rt;
|
439 |
|
|
}
|
440 |
|
|
|
441 |
|
|
#define gen_rtx_fmt_i00(c, m, p0)\
|
442 |
|
|
gen_rtx_fmt_i00_stat (c, m, p0 MEM_STAT_INFO)
|
443 |
|
|
|
444 |
|
|
static inline rtx
|
445 |
|
|
gen_rtx_fmt_ei_stat (RTX_CODE code, enum machine_mode mode,
|
446 |
|
|
rtx arg0,
|
447 |
|
|
int arg1 MEM_STAT_DECL)
|
448 |
|
|
{
|
449 |
|
|
rtx rt;
|
450 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
451 |
|
|
|
452 |
|
|
PUT_MODE (rt, mode);
|
453 |
|
|
XEXP (rt, 0) = arg0;
|
454 |
|
|
XINT (rt, 1) = arg1;
|
455 |
|
|
|
456 |
|
|
return rt;
|
457 |
|
|
}
|
458 |
|
|
|
459 |
|
|
#define gen_rtx_fmt_ei(c, m, p0, p1)\
|
460 |
|
|
gen_rtx_fmt_ei_stat (c, m, p0, p1 MEM_STAT_INFO)
|
461 |
|
|
|
462 |
|
|
static inline rtx
|
463 |
|
|
gen_rtx_fmt_e0_stat (RTX_CODE code, enum machine_mode mode,
|
464 |
|
|
rtx arg0 MEM_STAT_DECL)
|
465 |
|
|
{
|
466 |
|
|
rtx rt;
|
467 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
468 |
|
|
|
469 |
|
|
PUT_MODE (rt, mode);
|
470 |
|
|
XEXP (rt, 0) = arg0;
|
471 |
|
|
X0EXP (rt, 1) = NULL_RTX;
|
472 |
|
|
|
473 |
|
|
return rt;
|
474 |
|
|
}
|
475 |
|
|
|
476 |
|
|
#define gen_rtx_fmt_e0(c, m, p0)\
|
477 |
|
|
gen_rtx_fmt_e0_stat (c, m, p0 MEM_STAT_INFO)
|
478 |
|
|
|
479 |
|
|
static inline rtx
|
480 |
|
|
gen_rtx_fmt_u_stat (RTX_CODE code, enum machine_mode mode,
|
481 |
|
|
rtx arg0 MEM_STAT_DECL)
|
482 |
|
|
{
|
483 |
|
|
rtx rt;
|
484 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
485 |
|
|
|
486 |
|
|
PUT_MODE (rt, mode);
|
487 |
|
|
XEXP (rt, 0) = arg0;
|
488 |
|
|
|
489 |
|
|
return rt;
|
490 |
|
|
}
|
491 |
|
|
|
492 |
|
|
#define gen_rtx_fmt_u(c, m, p0)\
|
493 |
|
|
gen_rtx_fmt_u_stat (c, m, p0 MEM_STAT_INFO)
|
494 |
|
|
|
495 |
|
|
static inline rtx
|
496 |
|
|
gen_rtx_fmt_s00_stat (RTX_CODE code, enum machine_mode mode,
|
497 |
|
|
const char *arg0 MEM_STAT_DECL)
|
498 |
|
|
{
|
499 |
|
|
rtx rt;
|
500 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
501 |
|
|
|
502 |
|
|
PUT_MODE (rt, mode);
|
503 |
|
|
XSTR (rt, 0) = arg0;
|
504 |
|
|
X0EXP (rt, 1) = NULL_RTX;
|
505 |
|
|
X0EXP (rt, 2) = NULL_RTX;
|
506 |
|
|
|
507 |
|
|
return rt;
|
508 |
|
|
}
|
509 |
|
|
|
510 |
|
|
#define gen_rtx_fmt_s00(c, m, p0)\
|
511 |
|
|
gen_rtx_fmt_s00_stat (c, m, p0 MEM_STAT_INFO)
|
512 |
|
|
|
513 |
|
|
static inline rtx
|
514 |
|
|
gen_rtx_fmt_tei_stat (RTX_CODE code, enum machine_mode mode,
|
515 |
|
|
tree arg0,
|
516 |
|
|
rtx arg1,
|
517 |
|
|
int arg2 MEM_STAT_DECL)
|
518 |
|
|
{
|
519 |
|
|
rtx rt;
|
520 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
521 |
|
|
|
522 |
|
|
PUT_MODE (rt, mode);
|
523 |
|
|
XTREE (rt, 0) = arg0;
|
524 |
|
|
XEXP (rt, 1) = arg1;
|
525 |
|
|
XINT (rt, 2) = arg2;
|
526 |
|
|
|
527 |
|
|
return rt;
|
528 |
|
|
}
|
529 |
|
|
|
530 |
|
|
#define gen_rtx_fmt_tei(c, m, p0, p1, p2)\
|
531 |
|
|
gen_rtx_fmt_tei_stat (c, m, p0, p1, p2 MEM_STAT_INFO)
|
532 |
|
|
|
533 |
|
|
static inline rtx
|
534 |
|
|
gen_rtx_fmt_t_stat (RTX_CODE code, enum machine_mode mode,
|
535 |
|
|
tree arg0 MEM_STAT_DECL)
|
536 |
|
|
{
|
537 |
|
|
rtx rt;
|
538 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
539 |
|
|
|
540 |
|
|
PUT_MODE (rt, mode);
|
541 |
|
|
XTREE (rt, 0) = arg0;
|
542 |
|
|
|
543 |
|
|
return rt;
|
544 |
|
|
}
|
545 |
|
|
|
546 |
|
|
#define gen_rtx_fmt_t(c, m, p0)\
|
547 |
|
|
gen_rtx_fmt_t_stat (c, m, p0 MEM_STAT_INFO)
|
548 |
|
|
|
549 |
|
|
static inline rtx
|
550 |
|
|
gen_rtx_fmt_iss_stat (RTX_CODE code, enum machine_mode mode,
|
551 |
|
|
int arg0,
|
552 |
|
|
const char *arg1,
|
553 |
|
|
const char *arg2 MEM_STAT_DECL)
|
554 |
|
|
{
|
555 |
|
|
rtx rt;
|
556 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
557 |
|
|
|
558 |
|
|
PUT_MODE (rt, mode);
|
559 |
|
|
XINT (rt, 0) = arg0;
|
560 |
|
|
XSTR (rt, 1) = arg1;
|
561 |
|
|
XSTR (rt, 2) = arg2;
|
562 |
|
|
|
563 |
|
|
return rt;
|
564 |
|
|
}
|
565 |
|
|
|
566 |
|
|
#define gen_rtx_fmt_iss(c, m, p0, p1, p2)\
|
567 |
|
|
gen_rtx_fmt_iss_stat (c, m, p0, p1, p2 MEM_STAT_INFO)
|
568 |
|
|
|
569 |
|
|
static inline rtx
|
570 |
|
|
gen_rtx_fmt_is_stat (RTX_CODE code, enum machine_mode mode,
|
571 |
|
|
int arg0,
|
572 |
|
|
const char *arg1 MEM_STAT_DECL)
|
573 |
|
|
{
|
574 |
|
|
rtx rt;
|
575 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
576 |
|
|
|
577 |
|
|
PUT_MODE (rt, mode);
|
578 |
|
|
XINT (rt, 0) = arg0;
|
579 |
|
|
XSTR (rt, 1) = arg1;
|
580 |
|
|
|
581 |
|
|
return rt;
|
582 |
|
|
}
|
583 |
|
|
|
584 |
|
|
#define gen_rtx_fmt_is(c, m, p0, p1)\
|
585 |
|
|
gen_rtx_fmt_is_stat (c, m, p0, p1 MEM_STAT_INFO)
|
586 |
|
|
|
587 |
|
|
static inline rtx
|
588 |
|
|
gen_rtx_fmt_isE_stat (RTX_CODE code, enum machine_mode mode,
|
589 |
|
|
int arg0,
|
590 |
|
|
const char *arg1,
|
591 |
|
|
rtvec arg2 MEM_STAT_DECL)
|
592 |
|
|
{
|
593 |
|
|
rtx rt;
|
594 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
595 |
|
|
|
596 |
|
|
PUT_MODE (rt, mode);
|
597 |
|
|
XINT (rt, 0) = arg0;
|
598 |
|
|
XSTR (rt, 1) = arg1;
|
599 |
|
|
XVEC (rt, 2) = arg2;
|
600 |
|
|
|
601 |
|
|
return rt;
|
602 |
|
|
}
|
603 |
|
|
|
604 |
|
|
#define gen_rtx_fmt_isE(c, m, p0, p1, p2)\
|
605 |
|
|
gen_rtx_fmt_isE_stat (c, m, p0, p1, p2 MEM_STAT_INFO)
|
606 |
|
|
|
607 |
|
|
static inline rtx
|
608 |
|
|
gen_rtx_fmt_iE_stat (RTX_CODE code, enum machine_mode mode,
|
609 |
|
|
int arg0,
|
610 |
|
|
rtvec arg1 MEM_STAT_DECL)
|
611 |
|
|
{
|
612 |
|
|
rtx rt;
|
613 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
614 |
|
|
|
615 |
|
|
PUT_MODE (rt, mode);
|
616 |
|
|
XINT (rt, 0) = arg0;
|
617 |
|
|
XVEC (rt, 1) = arg1;
|
618 |
|
|
|
619 |
|
|
return rt;
|
620 |
|
|
}
|
621 |
|
|
|
622 |
|
|
#define gen_rtx_fmt_iE(c, m, p0, p1)\
|
623 |
|
|
gen_rtx_fmt_iE_stat (c, m, p0, p1 MEM_STAT_INFO)
|
624 |
|
|
|
625 |
|
|
static inline rtx
|
626 |
|
|
gen_rtx_fmt_ss_stat (RTX_CODE code, enum machine_mode mode,
|
627 |
|
|
const char *arg0,
|
628 |
|
|
const char *arg1 MEM_STAT_DECL)
|
629 |
|
|
{
|
630 |
|
|
rtx rt;
|
631 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
632 |
|
|
|
633 |
|
|
PUT_MODE (rt, mode);
|
634 |
|
|
XSTR (rt, 0) = arg0;
|
635 |
|
|
XSTR (rt, 1) = arg1;
|
636 |
|
|
|
637 |
|
|
return rt;
|
638 |
|
|
}
|
639 |
|
|
|
640 |
|
|
#define gen_rtx_fmt_ss(c, m, p0, p1)\
|
641 |
|
|
gen_rtx_fmt_ss_stat (c, m, p0, p1 MEM_STAT_INFO)
|
642 |
|
|
|
643 |
|
|
static inline rtx
|
644 |
|
|
gen_rtx_fmt_eE_stat (RTX_CODE code, enum machine_mode mode,
|
645 |
|
|
rtx arg0,
|
646 |
|
|
rtvec arg1 MEM_STAT_DECL)
|
647 |
|
|
{
|
648 |
|
|
rtx rt;
|
649 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
650 |
|
|
|
651 |
|
|
PUT_MODE (rt, mode);
|
652 |
|
|
XEXP (rt, 0) = arg0;
|
653 |
|
|
XVEC (rt, 1) = arg1;
|
654 |
|
|
|
655 |
|
|
return rt;
|
656 |
|
|
}
|
657 |
|
|
|
658 |
|
|
#define gen_rtx_fmt_eE(c, m, p0, p1)\
|
659 |
|
|
gen_rtx_fmt_eE_stat (c, m, p0, p1 MEM_STAT_INFO)
|
660 |
|
|
|
661 |
|
|
static inline rtx
|
662 |
|
|
gen_rtx_fmt_Ess_stat (RTX_CODE code, enum machine_mode mode,
|
663 |
|
|
rtvec arg0,
|
664 |
|
|
const char *arg1,
|
665 |
|
|
const char *arg2 MEM_STAT_DECL)
|
666 |
|
|
{
|
667 |
|
|
rtx rt;
|
668 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
669 |
|
|
|
670 |
|
|
PUT_MODE (rt, mode);
|
671 |
|
|
XVEC (rt, 0) = arg0;
|
672 |
|
|
XSTR (rt, 1) = arg1;
|
673 |
|
|
XSTR (rt, 2) = arg2;
|
674 |
|
|
|
675 |
|
|
return rt;
|
676 |
|
|
}
|
677 |
|
|
|
678 |
|
|
#define gen_rtx_fmt_Ess(c, m, p0, p1, p2)\
|
679 |
|
|
gen_rtx_fmt_Ess_stat (c, m, p0, p1, p2 MEM_STAT_INFO)
|
680 |
|
|
|
681 |
|
|
static inline rtx
|
682 |
|
|
gen_rtx_fmt_ses_stat (RTX_CODE code, enum machine_mode mode,
|
683 |
|
|
const char *arg0,
|
684 |
|
|
rtx arg1,
|
685 |
|
|
const char *arg2 MEM_STAT_DECL)
|
686 |
|
|
{
|
687 |
|
|
rtx rt;
|
688 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
689 |
|
|
|
690 |
|
|
PUT_MODE (rt, mode);
|
691 |
|
|
XSTR (rt, 0) = arg0;
|
692 |
|
|
XEXP (rt, 1) = arg1;
|
693 |
|
|
XSTR (rt, 2) = arg2;
|
694 |
|
|
|
695 |
|
|
return rt;
|
696 |
|
|
}
|
697 |
|
|
|
698 |
|
|
#define gen_rtx_fmt_ses(c, m, p0, p1, p2)\
|
699 |
|
|
gen_rtx_fmt_ses_stat (c, m, p0, p1, p2 MEM_STAT_INFO)
|
700 |
|
|
|
701 |
|
|
static inline rtx
|
702 |
|
|
gen_rtx_fmt_sss_stat (RTX_CODE code, enum machine_mode mode,
|
703 |
|
|
const char *arg0,
|
704 |
|
|
const char *arg1,
|
705 |
|
|
const char *arg2 MEM_STAT_DECL)
|
706 |
|
|
{
|
707 |
|
|
rtx rt;
|
708 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
709 |
|
|
|
710 |
|
|
PUT_MODE (rt, mode);
|
711 |
|
|
XSTR (rt, 0) = arg0;
|
712 |
|
|
XSTR (rt, 1) = arg1;
|
713 |
|
|
XSTR (rt, 2) = arg2;
|
714 |
|
|
|
715 |
|
|
return rt;
|
716 |
|
|
}
|
717 |
|
|
|
718 |
|
|
#define gen_rtx_fmt_sss(c, m, p0, p1, p2)\
|
719 |
|
|
gen_rtx_fmt_sss_stat (c, m, p0, p1, p2 MEM_STAT_INFO)
|
720 |
|
|
|
721 |
|
|
static inline rtx
|
722 |
|
|
gen_rtx_fmt_sse_stat (RTX_CODE code, enum machine_mode mode,
|
723 |
|
|
const char *arg0,
|
724 |
|
|
const char *arg1,
|
725 |
|
|
rtx arg2 MEM_STAT_DECL)
|
726 |
|
|
{
|
727 |
|
|
rtx rt;
|
728 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
729 |
|
|
|
730 |
|
|
PUT_MODE (rt, mode);
|
731 |
|
|
XSTR (rt, 0) = arg0;
|
732 |
|
|
XSTR (rt, 1) = arg1;
|
733 |
|
|
XEXP (rt, 2) = arg2;
|
734 |
|
|
|
735 |
|
|
return rt;
|
736 |
|
|
}
|
737 |
|
|
|
738 |
|
|
#define gen_rtx_fmt_sse(c, m, p0, p1, p2)\
|
739 |
|
|
gen_rtx_fmt_sse_stat (c, m, p0, p1, p2 MEM_STAT_INFO)
|
740 |
|
|
|
741 |
|
|
static inline rtx
|
742 |
|
|
gen_rtx_fmt_sies_stat (RTX_CODE code, enum machine_mode mode,
|
743 |
|
|
const char *arg0,
|
744 |
|
|
int arg1,
|
745 |
|
|
rtx arg2,
|
746 |
|
|
const char *arg3 MEM_STAT_DECL)
|
747 |
|
|
{
|
748 |
|
|
rtx rt;
|
749 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
750 |
|
|
|
751 |
|
|
PUT_MODE (rt, mode);
|
752 |
|
|
XSTR (rt, 0) = arg0;
|
753 |
|
|
XINT (rt, 1) = arg1;
|
754 |
|
|
XEXP (rt, 2) = arg2;
|
755 |
|
|
XSTR (rt, 3) = arg3;
|
756 |
|
|
|
757 |
|
|
return rt;
|
758 |
|
|
}
|
759 |
|
|
|
760 |
|
|
#define gen_rtx_fmt_sies(c, m, p0, p1, p2, p3)\
|
761 |
|
|
gen_rtx_fmt_sies_stat (c, m, p0, p1, p2, p3 MEM_STAT_INFO)
|
762 |
|
|
|
763 |
|
|
static inline rtx
|
764 |
|
|
gen_rtx_fmt_sE_stat (RTX_CODE code, enum machine_mode mode,
|
765 |
|
|
const char *arg0,
|
766 |
|
|
rtvec arg1 MEM_STAT_DECL)
|
767 |
|
|
{
|
768 |
|
|
rtx rt;
|
769 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
770 |
|
|
|
771 |
|
|
PUT_MODE (rt, mode);
|
772 |
|
|
XSTR (rt, 0) = arg0;
|
773 |
|
|
XVEC (rt, 1) = arg1;
|
774 |
|
|
|
775 |
|
|
return rt;
|
776 |
|
|
}
|
777 |
|
|
|
778 |
|
|
#define gen_rtx_fmt_sE(c, m, p0, p1)\
|
779 |
|
|
gen_rtx_fmt_sE_stat (c, m, p0, p1 MEM_STAT_INFO)
|
780 |
|
|
|
781 |
|
|
static inline rtx
|
782 |
|
|
gen_rtx_fmt_ii_stat (RTX_CODE code, enum machine_mode mode,
|
783 |
|
|
int arg0,
|
784 |
|
|
int arg1 MEM_STAT_DECL)
|
785 |
|
|
{
|
786 |
|
|
rtx rt;
|
787 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
788 |
|
|
|
789 |
|
|
PUT_MODE (rt, mode);
|
790 |
|
|
XINT (rt, 0) = arg0;
|
791 |
|
|
XINT (rt, 1) = arg1;
|
792 |
|
|
|
793 |
|
|
return rt;
|
794 |
|
|
}
|
795 |
|
|
|
796 |
|
|
#define gen_rtx_fmt_ii(c, m, p0, p1)\
|
797 |
|
|
gen_rtx_fmt_ii_stat (c, m, p0, p1 MEM_STAT_INFO)
|
798 |
|
|
|
799 |
|
|
static inline rtx
|
800 |
|
|
gen_rtx_fmt_Ee_stat (RTX_CODE code, enum machine_mode mode,
|
801 |
|
|
rtvec arg0,
|
802 |
|
|
rtx arg1 MEM_STAT_DECL)
|
803 |
|
|
{
|
804 |
|
|
rtx rt;
|
805 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
806 |
|
|
|
807 |
|
|
PUT_MODE (rt, mode);
|
808 |
|
|
XVEC (rt, 0) = arg0;
|
809 |
|
|
XEXP (rt, 1) = arg1;
|
810 |
|
|
|
811 |
|
|
return rt;
|
812 |
|
|
}
|
813 |
|
|
|
814 |
|
|
#define gen_rtx_fmt_Ee(c, m, p0, p1)\
|
815 |
|
|
gen_rtx_fmt_Ee_stat (c, m, p0, p1 MEM_STAT_INFO)
|
816 |
|
|
|
817 |
|
|
static inline rtx
|
818 |
|
|
gen_rtx_fmt_sEsE_stat (RTX_CODE code, enum machine_mode mode,
|
819 |
|
|
const char *arg0,
|
820 |
|
|
rtvec arg1,
|
821 |
|
|
const char *arg2,
|
822 |
|
|
rtvec arg3 MEM_STAT_DECL)
|
823 |
|
|
{
|
824 |
|
|
rtx rt;
|
825 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
826 |
|
|
|
827 |
|
|
PUT_MODE (rt, mode);
|
828 |
|
|
XSTR (rt, 0) = arg0;
|
829 |
|
|
XVEC (rt, 1) = arg1;
|
830 |
|
|
XSTR (rt, 2) = arg2;
|
831 |
|
|
XVEC (rt, 3) = arg3;
|
832 |
|
|
|
833 |
|
|
return rt;
|
834 |
|
|
}
|
835 |
|
|
|
836 |
|
|
#define gen_rtx_fmt_sEsE(c, m, p0, p1, p2, p3)\
|
837 |
|
|
gen_rtx_fmt_sEsE_stat (c, m, p0, p1, p2, p3 MEM_STAT_INFO)
|
838 |
|
|
|
839 |
|
|
static inline rtx
|
840 |
|
|
gen_rtx_fmt_ssss_stat (RTX_CODE code, enum machine_mode mode,
|
841 |
|
|
const char *arg0,
|
842 |
|
|
const char *arg1,
|
843 |
|
|
const char *arg2,
|
844 |
|
|
const char *arg3 MEM_STAT_DECL)
|
845 |
|
|
{
|
846 |
|
|
rtx rt;
|
847 |
|
|
rt = rtx_alloc_stat (code PASS_MEM_STAT);
|
848 |
|
|
|
849 |
|
|
PUT_MODE (rt, mode);
|
850 |
|
|
XSTR (rt, 0) = arg0;
|
851 |
|
|
XSTR (rt, 1) = arg1;
|
852 |
|
|
XSTR (rt, 2) = arg2;
|
853 |
|
|
XSTR (rt, 3) = arg3;
|
854 |
|
|
|
855 |
|
|
return rt;
|
856 |
|
|
}
|
857 |
|
|
|
858 |
|
|
#define gen_rtx_fmt_ssss(c, m, p0, p1, p2, p3)\
|
859 |
|
|
gen_rtx_fmt_ssss_stat (c, m, p0, p1, p2, p3 MEM_STAT_INFO)
|
860 |
|
|
|
861 |
|
|
|
862 |
|
|
#define gen_rtx_VALUE(MODE) \
|
863 |
|
|
gen_rtx_fmt_0 (VALUE, (MODE))
|
864 |
|
|
#define gen_rtx_DEBUG_EXPR(MODE) \
|
865 |
|
|
gen_rtx_fmt_0 (DEBUG_EXPR, (MODE))
|
866 |
|
|
#define gen_rtx_EXPR_LIST(MODE, ARG0, ARG1) \
|
867 |
|
|
gen_rtx_fmt_ee (EXPR_LIST, (MODE), (ARG0), (ARG1))
|
868 |
|
|
#define gen_rtx_INSN_LIST(MODE, ARG0, ARG1) \
|
869 |
|
|
gen_rtx_fmt_ue (INSN_LIST, (MODE), (ARG0), (ARG1))
|
870 |
|
|
#define gen_rtx_SEQUENCE(MODE, ARG0) \
|
871 |
|
|
gen_rtx_fmt_E (SEQUENCE, (MODE), (ARG0))
|
872 |
|
|
#define gen_rtx_ADDRESS(MODE, ARG0) \
|
873 |
|
|
gen_rtx_fmt_i (ADDRESS, (MODE), (ARG0))
|
874 |
|
|
#define gen_rtx_DEBUG_INSN(MODE, ARG0, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6, ARG7) \
|
875 |
|
|
gen_rtx_fmt_iuuBeiie (DEBUG_INSN, (MODE), (ARG0), (ARG1), (ARG2), (ARG3), (ARG4), (ARG5), (ARG6), (ARG7))
|
876 |
|
|
#define gen_rtx_INSN(MODE, ARG0, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6, ARG7) \
|
877 |
|
|
gen_rtx_fmt_iuuBeiie (INSN, (MODE), (ARG0), (ARG1), (ARG2), (ARG3), (ARG4), (ARG5), (ARG6), (ARG7))
|
878 |
|
|
#define gen_rtx_JUMP_INSN(MODE, ARG0, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6, ARG7) \
|
879 |
|
|
gen_rtx_fmt_iuuBeiie0 (JUMP_INSN, (MODE), (ARG0), (ARG1), (ARG2), (ARG3), (ARG4), (ARG5), (ARG6), (ARG7))
|
880 |
|
|
#define gen_rtx_CALL_INSN(MODE, ARG0, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6, ARG7, ARG8) \
|
881 |
|
|
gen_rtx_fmt_iuuBeiiee (CALL_INSN, (MODE), (ARG0), (ARG1), (ARG2), (ARG3), (ARG4), (ARG5), (ARG6), (ARG7), (ARG8))
|
882 |
|
|
#define gen_rtx_BARRIER(MODE, ARG0, ARG1, ARG2) \
|
883 |
|
|
gen_rtx_fmt_iuu00000 (BARRIER, (MODE), (ARG0), (ARG1), (ARG2))
|
884 |
|
|
#define gen_rtx_CODE_LABEL(MODE, ARG0, ARG1, ARG2, ARG3, ARG4, ARG5) \
|
885 |
|
|
gen_rtx_fmt_iuuB00is (CODE_LABEL, (MODE), (ARG0), (ARG1), (ARG2), (ARG3), (ARG4), (ARG5))
|
886 |
|
|
#define gen_rtx_COND_EXEC(MODE, ARG0, ARG1) \
|
887 |
|
|
gen_rtx_fmt_ee (COND_EXEC, (MODE), (ARG0), (ARG1))
|
888 |
|
|
#define gen_rtx_PARALLEL(MODE, ARG0) \
|
889 |
|
|
gen_rtx_fmt_E (PARALLEL, (MODE), (ARG0))
|
890 |
|
|
#define gen_rtx_ASM_INPUT(MODE, ARG0, ARG1) \
|
891 |
|
|
gen_rtx_fmt_si (ASM_INPUT, (MODE), (ARG0), (ARG1))
|
892 |
|
|
#define gen_rtx_ASM_OPERANDS(MODE, ARG0, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \
|
893 |
|
|
gen_rtx_fmt_ssiEEEi (ASM_OPERANDS, (MODE), (ARG0), (ARG1), (ARG2), (ARG3), (ARG4), (ARG5), (ARG6))
|
894 |
|
|
#define gen_rtx_UNSPEC(MODE, ARG0, ARG1) \
|
895 |
|
|
gen_rtx_fmt_Ei (UNSPEC, (MODE), (ARG0), (ARG1))
|
896 |
|
|
#define gen_rtx_UNSPEC_VOLATILE(MODE, ARG0, ARG1) \
|
897 |
|
|
gen_rtx_fmt_Ei (UNSPEC_VOLATILE, (MODE), (ARG0), (ARG1))
|
898 |
|
|
#define gen_rtx_ADDR_VEC(MODE, ARG0) \
|
899 |
|
|
gen_rtx_fmt_E (ADDR_VEC, (MODE), (ARG0))
|
900 |
|
|
#define gen_rtx_ADDR_DIFF_VEC(MODE, ARG0, ARG1, ARG2, ARG3) \
|
901 |
|
|
gen_rtx_fmt_eEee0 (ADDR_DIFF_VEC, (MODE), (ARG0), (ARG1), (ARG2), (ARG3))
|
902 |
|
|
#define gen_rtx_PREFETCH(MODE, ARG0, ARG1, ARG2) \
|
903 |
|
|
gen_rtx_fmt_eee (PREFETCH, (MODE), (ARG0), (ARG1), (ARG2))
|
904 |
|
|
#define gen_rtx_SET(MODE, ARG0, ARG1) \
|
905 |
|
|
gen_rtx_fmt_ee (SET, (MODE), (ARG0), (ARG1))
|
906 |
|
|
#define gen_rtx_USE(MODE, ARG0) \
|
907 |
|
|
gen_rtx_fmt_e (USE, (MODE), (ARG0))
|
908 |
|
|
#define gen_rtx_CLOBBER(MODE, ARG0) \
|
909 |
|
|
gen_rtx_fmt_e (CLOBBER, (MODE), (ARG0))
|
910 |
|
|
#define gen_rtx_CALL(MODE, ARG0, ARG1) \
|
911 |
|
|
gen_rtx_fmt_ee (CALL, (MODE), (ARG0), (ARG1))
|
912 |
|
|
#define gen_rtx_raw_RETURN(MODE) \
|
913 |
|
|
gen_rtx_fmt_ (RETURN, (MODE))
|
914 |
|
|
#define gen_rtx_raw_SIMPLE_RETURN(MODE) \
|
915 |
|
|
gen_rtx_fmt_ (SIMPLE_RETURN, (MODE))
|
916 |
|
|
#define gen_rtx_EH_RETURN(MODE) \
|
917 |
|
|
gen_rtx_fmt_ (EH_RETURN, (MODE))
|
918 |
|
|
#define gen_rtx_TRAP_IF(MODE, ARG0, ARG1) \
|
919 |
|
|
gen_rtx_fmt_ee (TRAP_IF, (MODE), (ARG0), (ARG1))
|
920 |
|
|
#define gen_rtx_raw_CONST_INT(MODE, ARG0) \
|
921 |
|
|
gen_rtx_fmt_w (CONST_INT, (MODE), (ARG0))
|
922 |
|
|
#define gen_rtx_raw_CONST_VECTOR(MODE, ARG0) \
|
923 |
|
|
gen_rtx_fmt_E (CONST_VECTOR, (MODE), (ARG0))
|
924 |
|
|
#define gen_rtx_CONST_STRING(MODE, ARG0) \
|
925 |
|
|
gen_rtx_fmt_s (CONST_STRING, (MODE), (ARG0))
|
926 |
|
|
#define gen_rtx_CONST(MODE, ARG0) \
|
927 |
|
|
gen_rtx_fmt_e (CONST, (MODE), (ARG0))
|
928 |
|
|
#define gen_rtx_raw_PC(MODE) \
|
929 |
|
|
gen_rtx_fmt_ (PC, (MODE))
|
930 |
|
|
#define gen_rtx_raw_REG(MODE, ARG0) \
|
931 |
|
|
gen_rtx_fmt_i00 (REG, (MODE), (ARG0))
|
932 |
|
|
#define gen_rtx_SCRATCH(MODE) \
|
933 |
|
|
gen_rtx_fmt_0 (SCRATCH, (MODE))
|
934 |
|
|
#define gen_rtx_raw_SUBREG(MODE, ARG0, ARG1) \
|
935 |
|
|
gen_rtx_fmt_ei (SUBREG, (MODE), (ARG0), (ARG1))
|
936 |
|
|
#define gen_rtx_STRICT_LOW_PART(MODE, ARG0) \
|
937 |
|
|
gen_rtx_fmt_e (STRICT_LOW_PART, (MODE), (ARG0))
|
938 |
|
|
#define gen_rtx_CONCAT(MODE, ARG0, ARG1) \
|
939 |
|
|
gen_rtx_fmt_ee (CONCAT, (MODE), (ARG0), (ARG1))
|
940 |
|
|
#define gen_rtx_CONCATN(MODE, ARG0) \
|
941 |
|
|
gen_rtx_fmt_E (CONCATN, (MODE), (ARG0))
|
942 |
|
|
#define gen_rtx_raw_MEM(MODE, ARG0) \
|
943 |
|
|
gen_rtx_fmt_e0 (MEM, (MODE), (ARG0))
|
944 |
|
|
#define gen_rtx_LABEL_REF(MODE, ARG0) \
|
945 |
|
|
gen_rtx_fmt_u (LABEL_REF, (MODE), (ARG0))
|
946 |
|
|
#define gen_rtx_SYMBOL_REF(MODE, ARG0) \
|
947 |
|
|
gen_rtx_fmt_s00 (SYMBOL_REF, (MODE), (ARG0))
|
948 |
|
|
#define gen_rtx_raw_CC0(MODE) \
|
949 |
|
|
gen_rtx_fmt_ (CC0, (MODE))
|
950 |
|
|
#define gen_rtx_IF_THEN_ELSE(MODE, ARG0, ARG1, ARG2) \
|
951 |
|
|
gen_rtx_fmt_eee (IF_THEN_ELSE, (MODE), (ARG0), (ARG1), (ARG2))
|
952 |
|
|
#define gen_rtx_COMPARE(MODE, ARG0, ARG1) \
|
953 |
|
|
gen_rtx_fmt_ee (COMPARE, (MODE), (ARG0), (ARG1))
|
954 |
|
|
#define gen_rtx_PLUS(MODE, ARG0, ARG1) \
|
955 |
|
|
gen_rtx_fmt_ee (PLUS, (MODE), (ARG0), (ARG1))
|
956 |
|
|
#define gen_rtx_MINUS(MODE, ARG0, ARG1) \
|
957 |
|
|
gen_rtx_fmt_ee (MINUS, (MODE), (ARG0), (ARG1))
|
958 |
|
|
#define gen_rtx_NEG(MODE, ARG0) \
|
959 |
|
|
gen_rtx_fmt_e (NEG, (MODE), (ARG0))
|
960 |
|
|
#define gen_rtx_MULT(MODE, ARG0, ARG1) \
|
961 |
|
|
gen_rtx_fmt_ee (MULT, (MODE), (ARG0), (ARG1))
|
962 |
|
|
#define gen_rtx_SS_MULT(MODE, ARG0, ARG1) \
|
963 |
|
|
gen_rtx_fmt_ee (SS_MULT, (MODE), (ARG0), (ARG1))
|
964 |
|
|
#define gen_rtx_US_MULT(MODE, ARG0, ARG1) \
|
965 |
|
|
gen_rtx_fmt_ee (US_MULT, (MODE), (ARG0), (ARG1))
|
966 |
|
|
#define gen_rtx_DIV(MODE, ARG0, ARG1) \
|
967 |
|
|
gen_rtx_fmt_ee (DIV, (MODE), (ARG0), (ARG1))
|
968 |
|
|
#define gen_rtx_SS_DIV(MODE, ARG0, ARG1) \
|
969 |
|
|
gen_rtx_fmt_ee (SS_DIV, (MODE), (ARG0), (ARG1))
|
970 |
|
|
#define gen_rtx_US_DIV(MODE, ARG0, ARG1) \
|
971 |
|
|
gen_rtx_fmt_ee (US_DIV, (MODE), (ARG0), (ARG1))
|
972 |
|
|
#define gen_rtx_MOD(MODE, ARG0, ARG1) \
|
973 |
|
|
gen_rtx_fmt_ee (MOD, (MODE), (ARG0), (ARG1))
|
974 |
|
|
#define gen_rtx_UDIV(MODE, ARG0, ARG1) \
|
975 |
|
|
gen_rtx_fmt_ee (UDIV, (MODE), (ARG0), (ARG1))
|
976 |
|
|
#define gen_rtx_UMOD(MODE, ARG0, ARG1) \
|
977 |
|
|
gen_rtx_fmt_ee (UMOD, (MODE), (ARG0), (ARG1))
|
978 |
|
|
#define gen_rtx_AND(MODE, ARG0, ARG1) \
|
979 |
|
|
gen_rtx_fmt_ee (AND, (MODE), (ARG0), (ARG1))
|
980 |
|
|
#define gen_rtx_IOR(MODE, ARG0, ARG1) \
|
981 |
|
|
gen_rtx_fmt_ee (IOR, (MODE), (ARG0), (ARG1))
|
982 |
|
|
#define gen_rtx_XOR(MODE, ARG0, ARG1) \
|
983 |
|
|
gen_rtx_fmt_ee (XOR, (MODE), (ARG0), (ARG1))
|
984 |
|
|
#define gen_rtx_NOT(MODE, ARG0) \
|
985 |
|
|
gen_rtx_fmt_e (NOT, (MODE), (ARG0))
|
986 |
|
|
#define gen_rtx_ASHIFT(MODE, ARG0, ARG1) \
|
987 |
|
|
gen_rtx_fmt_ee (ASHIFT, (MODE), (ARG0), (ARG1))
|
988 |
|
|
#define gen_rtx_ROTATE(MODE, ARG0, ARG1) \
|
989 |
|
|
gen_rtx_fmt_ee (ROTATE, (MODE), (ARG0), (ARG1))
|
990 |
|
|
#define gen_rtx_ASHIFTRT(MODE, ARG0, ARG1) \
|
991 |
|
|
gen_rtx_fmt_ee (ASHIFTRT, (MODE), (ARG0), (ARG1))
|
992 |
|
|
#define gen_rtx_LSHIFTRT(MODE, ARG0, ARG1) \
|
993 |
|
|
gen_rtx_fmt_ee (LSHIFTRT, (MODE), (ARG0), (ARG1))
|
994 |
|
|
#define gen_rtx_ROTATERT(MODE, ARG0, ARG1) \
|
995 |
|
|
gen_rtx_fmt_ee (ROTATERT, (MODE), (ARG0), (ARG1))
|
996 |
|
|
#define gen_rtx_SMIN(MODE, ARG0, ARG1) \
|
997 |
|
|
gen_rtx_fmt_ee (SMIN, (MODE), (ARG0), (ARG1))
|
998 |
|
|
#define gen_rtx_SMAX(MODE, ARG0, ARG1) \
|
999 |
|
|
gen_rtx_fmt_ee (SMAX, (MODE), (ARG0), (ARG1))
|
1000 |
|
|
#define gen_rtx_UMIN(MODE, ARG0, ARG1) \
|
1001 |
|
|
gen_rtx_fmt_ee (UMIN, (MODE), (ARG0), (ARG1))
|
1002 |
|
|
#define gen_rtx_UMAX(MODE, ARG0, ARG1) \
|
1003 |
|
|
gen_rtx_fmt_ee (UMAX, (MODE), (ARG0), (ARG1))
|
1004 |
|
|
#define gen_rtx_PRE_DEC(MODE, ARG0) \
|
1005 |
|
|
gen_rtx_fmt_e (PRE_DEC, (MODE), (ARG0))
|
1006 |
|
|
#define gen_rtx_PRE_INC(MODE, ARG0) \
|
1007 |
|
|
gen_rtx_fmt_e (PRE_INC, (MODE), (ARG0))
|
1008 |
|
|
#define gen_rtx_POST_DEC(MODE, ARG0) \
|
1009 |
|
|
gen_rtx_fmt_e (POST_DEC, (MODE), (ARG0))
|
1010 |
|
|
#define gen_rtx_POST_INC(MODE, ARG0) \
|
1011 |
|
|
gen_rtx_fmt_e (POST_INC, (MODE), (ARG0))
|
1012 |
|
|
#define gen_rtx_PRE_MODIFY(MODE, ARG0, ARG1) \
|
1013 |
|
|
gen_rtx_fmt_ee (PRE_MODIFY, (MODE), (ARG0), (ARG1))
|
1014 |
|
|
#define gen_rtx_POST_MODIFY(MODE, ARG0, ARG1) \
|
1015 |
|
|
gen_rtx_fmt_ee (POST_MODIFY, (MODE), (ARG0), (ARG1))
|
1016 |
|
|
#define gen_rtx_NE(MODE, ARG0, ARG1) \
|
1017 |
|
|
gen_rtx_fmt_ee (NE, (MODE), (ARG0), (ARG1))
|
1018 |
|
|
#define gen_rtx_EQ(MODE, ARG0, ARG1) \
|
1019 |
|
|
gen_rtx_fmt_ee (EQ, (MODE), (ARG0), (ARG1))
|
1020 |
|
|
#define gen_rtx_GE(MODE, ARG0, ARG1) \
|
1021 |
|
|
gen_rtx_fmt_ee (GE, (MODE), (ARG0), (ARG1))
|
1022 |
|
|
#define gen_rtx_GT(MODE, ARG0, ARG1) \
|
1023 |
|
|
gen_rtx_fmt_ee (GT, (MODE), (ARG0), (ARG1))
|
1024 |
|
|
#define gen_rtx_LE(MODE, ARG0, ARG1) \
|
1025 |
|
|
gen_rtx_fmt_ee (LE, (MODE), (ARG0), (ARG1))
|
1026 |
|
|
#define gen_rtx_LT(MODE, ARG0, ARG1) \
|
1027 |
|
|
gen_rtx_fmt_ee (LT, (MODE), (ARG0), (ARG1))
|
1028 |
|
|
#define gen_rtx_GEU(MODE, ARG0, ARG1) \
|
1029 |
|
|
gen_rtx_fmt_ee (GEU, (MODE), (ARG0), (ARG1))
|
1030 |
|
|
#define gen_rtx_GTU(MODE, ARG0, ARG1) \
|
1031 |
|
|
gen_rtx_fmt_ee (GTU, (MODE), (ARG0), (ARG1))
|
1032 |
|
|
#define gen_rtx_LEU(MODE, ARG0, ARG1) \
|
1033 |
|
|
gen_rtx_fmt_ee (LEU, (MODE), (ARG0), (ARG1))
|
1034 |
|
|
#define gen_rtx_LTU(MODE, ARG0, ARG1) \
|
1035 |
|
|
gen_rtx_fmt_ee (LTU, (MODE), (ARG0), (ARG1))
|
1036 |
|
|
#define gen_rtx_UNORDERED(MODE, ARG0, ARG1) \
|
1037 |
|
|
gen_rtx_fmt_ee (UNORDERED, (MODE), (ARG0), (ARG1))
|
1038 |
|
|
#define gen_rtx_ORDERED(MODE, ARG0, ARG1) \
|
1039 |
|
|
gen_rtx_fmt_ee (ORDERED, (MODE), (ARG0), (ARG1))
|
1040 |
|
|
#define gen_rtx_UNEQ(MODE, ARG0, ARG1) \
|
1041 |
|
|
gen_rtx_fmt_ee (UNEQ, (MODE), (ARG0), (ARG1))
|
1042 |
|
|
#define gen_rtx_UNGE(MODE, ARG0, ARG1) \
|
1043 |
|
|
gen_rtx_fmt_ee (UNGE, (MODE), (ARG0), (ARG1))
|
1044 |
|
|
#define gen_rtx_UNGT(MODE, ARG0, ARG1) \
|
1045 |
|
|
gen_rtx_fmt_ee (UNGT, (MODE), (ARG0), (ARG1))
|
1046 |
|
|
#define gen_rtx_UNLE(MODE, ARG0, ARG1) \
|
1047 |
|
|
gen_rtx_fmt_ee (UNLE, (MODE), (ARG0), (ARG1))
|
1048 |
|
|
#define gen_rtx_UNLT(MODE, ARG0, ARG1) \
|
1049 |
|
|
gen_rtx_fmt_ee (UNLT, (MODE), (ARG0), (ARG1))
|
1050 |
|
|
#define gen_rtx_LTGT(MODE, ARG0, ARG1) \
|
1051 |
|
|
gen_rtx_fmt_ee (LTGT, (MODE), (ARG0), (ARG1))
|
1052 |
|
|
#define gen_rtx_SIGN_EXTEND(MODE, ARG0) \
|
1053 |
|
|
gen_rtx_fmt_e (SIGN_EXTEND, (MODE), (ARG0))
|
1054 |
|
|
#define gen_rtx_ZERO_EXTEND(MODE, ARG0) \
|
1055 |
|
|
gen_rtx_fmt_e (ZERO_EXTEND, (MODE), (ARG0))
|
1056 |
|
|
#define gen_rtx_TRUNCATE(MODE, ARG0) \
|
1057 |
|
|
gen_rtx_fmt_e (TRUNCATE, (MODE), (ARG0))
|
1058 |
|
|
#define gen_rtx_FLOAT_EXTEND(MODE, ARG0) \
|
1059 |
|
|
gen_rtx_fmt_e (FLOAT_EXTEND, (MODE), (ARG0))
|
1060 |
|
|
#define gen_rtx_FLOAT_TRUNCATE(MODE, ARG0) \
|
1061 |
|
|
gen_rtx_fmt_e (FLOAT_TRUNCATE, (MODE), (ARG0))
|
1062 |
|
|
#define gen_rtx_FLOAT(MODE, ARG0) \
|
1063 |
|
|
gen_rtx_fmt_e (FLOAT, (MODE), (ARG0))
|
1064 |
|
|
#define gen_rtx_FIX(MODE, ARG0) \
|
1065 |
|
|
gen_rtx_fmt_e (FIX, (MODE), (ARG0))
|
1066 |
|
|
#define gen_rtx_UNSIGNED_FLOAT(MODE, ARG0) \
|
1067 |
|
|
gen_rtx_fmt_e (UNSIGNED_FLOAT, (MODE), (ARG0))
|
1068 |
|
|
#define gen_rtx_UNSIGNED_FIX(MODE, ARG0) \
|
1069 |
|
|
gen_rtx_fmt_e (UNSIGNED_FIX, (MODE), (ARG0))
|
1070 |
|
|
#define gen_rtx_FRACT_CONVERT(MODE, ARG0) \
|
1071 |
|
|
gen_rtx_fmt_e (FRACT_CONVERT, (MODE), (ARG0))
|
1072 |
|
|
#define gen_rtx_UNSIGNED_FRACT_CONVERT(MODE, ARG0) \
|
1073 |
|
|
gen_rtx_fmt_e (UNSIGNED_FRACT_CONVERT, (MODE), (ARG0))
|
1074 |
|
|
#define gen_rtx_SAT_FRACT(MODE, ARG0) \
|
1075 |
|
|
gen_rtx_fmt_e (SAT_FRACT, (MODE), (ARG0))
|
1076 |
|
|
#define gen_rtx_UNSIGNED_SAT_FRACT(MODE, ARG0) \
|
1077 |
|
|
gen_rtx_fmt_e (UNSIGNED_SAT_FRACT, (MODE), (ARG0))
|
1078 |
|
|
#define gen_rtx_ABS(MODE, ARG0) \
|
1079 |
|
|
gen_rtx_fmt_e (ABS, (MODE), (ARG0))
|
1080 |
|
|
#define gen_rtx_SQRT(MODE, ARG0) \
|
1081 |
|
|
gen_rtx_fmt_e (SQRT, (MODE), (ARG0))
|
1082 |
|
|
#define gen_rtx_BSWAP(MODE, ARG0) \
|
1083 |
|
|
gen_rtx_fmt_e (BSWAP, (MODE), (ARG0))
|
1084 |
|
|
#define gen_rtx_FFS(MODE, ARG0) \
|
1085 |
|
|
gen_rtx_fmt_e (FFS, (MODE), (ARG0))
|
1086 |
|
|
#define gen_rtx_CLRSB(MODE, ARG0) \
|
1087 |
|
|
gen_rtx_fmt_e (CLRSB, (MODE), (ARG0))
|
1088 |
|
|
#define gen_rtx_CLZ(MODE, ARG0) \
|
1089 |
|
|
gen_rtx_fmt_e (CLZ, (MODE), (ARG0))
|
1090 |
|
|
#define gen_rtx_CTZ(MODE, ARG0) \
|
1091 |
|
|
gen_rtx_fmt_e (CTZ, (MODE), (ARG0))
|
1092 |
|
|
#define gen_rtx_POPCOUNT(MODE, ARG0) \
|
1093 |
|
|
gen_rtx_fmt_e (POPCOUNT, (MODE), (ARG0))
|
1094 |
|
|
#define gen_rtx_PARITY(MODE, ARG0) \
|
1095 |
|
|
gen_rtx_fmt_e (PARITY, (MODE), (ARG0))
|
1096 |
|
|
#define gen_rtx_SIGN_EXTRACT(MODE, ARG0, ARG1, ARG2) \
|
1097 |
|
|
gen_rtx_fmt_eee (SIGN_EXTRACT, (MODE), (ARG0), (ARG1), (ARG2))
|
1098 |
|
|
#define gen_rtx_ZERO_EXTRACT(MODE, ARG0, ARG1, ARG2) \
|
1099 |
|
|
gen_rtx_fmt_eee (ZERO_EXTRACT, (MODE), (ARG0), (ARG1), (ARG2))
|
1100 |
|
|
#define gen_rtx_HIGH(MODE, ARG0) \
|
1101 |
|
|
gen_rtx_fmt_e (HIGH, (MODE), (ARG0))
|
1102 |
|
|
#define gen_rtx_LO_SUM(MODE, ARG0, ARG1) \
|
1103 |
|
|
gen_rtx_fmt_ee (LO_SUM, (MODE), (ARG0), (ARG1))
|
1104 |
|
|
#define gen_rtx_VEC_MERGE(MODE, ARG0, ARG1, ARG2) \
|
1105 |
|
|
gen_rtx_fmt_eee (VEC_MERGE, (MODE), (ARG0), (ARG1), (ARG2))
|
1106 |
|
|
#define gen_rtx_VEC_SELECT(MODE, ARG0, ARG1) \
|
1107 |
|
|
gen_rtx_fmt_ee (VEC_SELECT, (MODE), (ARG0), (ARG1))
|
1108 |
|
|
#define gen_rtx_VEC_CONCAT(MODE, ARG0, ARG1) \
|
1109 |
|
|
gen_rtx_fmt_ee (VEC_CONCAT, (MODE), (ARG0), (ARG1))
|
1110 |
|
|
#define gen_rtx_VEC_DUPLICATE(MODE, ARG0) \
|
1111 |
|
|
gen_rtx_fmt_e (VEC_DUPLICATE, (MODE), (ARG0))
|
1112 |
|
|
#define gen_rtx_SS_PLUS(MODE, ARG0, ARG1) \
|
1113 |
|
|
gen_rtx_fmt_ee (SS_PLUS, (MODE), (ARG0), (ARG1))
|
1114 |
|
|
#define gen_rtx_US_PLUS(MODE, ARG0, ARG1) \
|
1115 |
|
|
gen_rtx_fmt_ee (US_PLUS, (MODE), (ARG0), (ARG1))
|
1116 |
|
|
#define gen_rtx_SS_MINUS(MODE, ARG0, ARG1) \
|
1117 |
|
|
gen_rtx_fmt_ee (SS_MINUS, (MODE), (ARG0), (ARG1))
|
1118 |
|
|
#define gen_rtx_SS_NEG(MODE, ARG0) \
|
1119 |
|
|
gen_rtx_fmt_e (SS_NEG, (MODE), (ARG0))
|
1120 |
|
|
#define gen_rtx_US_NEG(MODE, ARG0) \
|
1121 |
|
|
gen_rtx_fmt_e (US_NEG, (MODE), (ARG0))
|
1122 |
|
|
#define gen_rtx_SS_ABS(MODE, ARG0) \
|
1123 |
|
|
gen_rtx_fmt_e (SS_ABS, (MODE), (ARG0))
|
1124 |
|
|
#define gen_rtx_SS_ASHIFT(MODE, ARG0, ARG1) \
|
1125 |
|
|
gen_rtx_fmt_ee (SS_ASHIFT, (MODE), (ARG0), (ARG1))
|
1126 |
|
|
#define gen_rtx_US_ASHIFT(MODE, ARG0, ARG1) \
|
1127 |
|
|
gen_rtx_fmt_ee (US_ASHIFT, (MODE), (ARG0), (ARG1))
|
1128 |
|
|
#define gen_rtx_US_MINUS(MODE, ARG0, ARG1) \
|
1129 |
|
|
gen_rtx_fmt_ee (US_MINUS, (MODE), (ARG0), (ARG1))
|
1130 |
|
|
#define gen_rtx_SS_TRUNCATE(MODE, ARG0) \
|
1131 |
|
|
gen_rtx_fmt_e (SS_TRUNCATE, (MODE), (ARG0))
|
1132 |
|
|
#define gen_rtx_US_TRUNCATE(MODE, ARG0) \
|
1133 |
|
|
gen_rtx_fmt_e (US_TRUNCATE, (MODE), (ARG0))
|
1134 |
|
|
#define gen_rtx_FMA(MODE, ARG0, ARG1, ARG2) \
|
1135 |
|
|
gen_rtx_fmt_eee (FMA, (MODE), (ARG0), (ARG1), (ARG2))
|
1136 |
|
|
#define gen_rtx_VAR_LOCATION(MODE, ARG0, ARG1, ARG2) \
|
1137 |
|
|
gen_rtx_fmt_tei (VAR_LOCATION, (MODE), (ARG0), (ARG1), (ARG2))
|
1138 |
|
|
#define gen_rtx_DEBUG_IMPLICIT_PTR(MODE, ARG0) \
|
1139 |
|
|
gen_rtx_fmt_t (DEBUG_IMPLICIT_PTR, (MODE), (ARG0))
|
1140 |
|
|
#define gen_rtx_ENTRY_VALUE(MODE) \
|
1141 |
|
|
gen_rtx_fmt_0 (ENTRY_VALUE, (MODE))
|
1142 |
|
|
#define gen_rtx_DEBUG_PARAMETER_REF(MODE, ARG0) \
|
1143 |
|
|
gen_rtx_fmt_t (DEBUG_PARAMETER_REF, (MODE), (ARG0))
|
1144 |
|
|
#define gen_rtx_MATCH_OPERAND(MODE, ARG0, ARG1, ARG2) \
|
1145 |
|
|
gen_rtx_fmt_iss (MATCH_OPERAND, (MODE), (ARG0), (ARG1), (ARG2))
|
1146 |
|
|
#define gen_rtx_MATCH_SCRATCH(MODE, ARG0, ARG1) \
|
1147 |
|
|
gen_rtx_fmt_is (MATCH_SCRATCH, (MODE), (ARG0), (ARG1))
|
1148 |
|
|
#define gen_rtx_MATCH_OPERATOR(MODE, ARG0, ARG1, ARG2) \
|
1149 |
|
|
gen_rtx_fmt_isE (MATCH_OPERATOR, (MODE), (ARG0), (ARG1), (ARG2))
|
1150 |
|
|
#define gen_rtx_MATCH_PARALLEL(MODE, ARG0, ARG1, ARG2) \
|
1151 |
|
|
gen_rtx_fmt_isE (MATCH_PARALLEL, (MODE), (ARG0), (ARG1), (ARG2))
|
1152 |
|
|
#define gen_rtx_MATCH_DUP(MODE, ARG0) \
|
1153 |
|
|
gen_rtx_fmt_i (MATCH_DUP, (MODE), (ARG0))
|
1154 |
|
|
#define gen_rtx_MATCH_OP_DUP(MODE, ARG0, ARG1) \
|
1155 |
|
|
gen_rtx_fmt_iE (MATCH_OP_DUP, (MODE), (ARG0), (ARG1))
|
1156 |
|
|
#define gen_rtx_MATCH_PAR_DUP(MODE, ARG0, ARG1) \
|
1157 |
|
|
gen_rtx_fmt_iE (MATCH_PAR_DUP, (MODE), (ARG0), (ARG1))
|
1158 |
|
|
#define gen_rtx_MATCH_CODE(MODE, ARG0, ARG1) \
|
1159 |
|
|
gen_rtx_fmt_ss (MATCH_CODE, (MODE), (ARG0), (ARG1))
|
1160 |
|
|
#define gen_rtx_MATCH_TEST(MODE, ARG0) \
|
1161 |
|
|
gen_rtx_fmt_s (MATCH_TEST, (MODE), (ARG0))
|
1162 |
|
|
#define gen_rtx_DEFINE_DELAY(MODE, ARG0, ARG1) \
|
1163 |
|
|
gen_rtx_fmt_eE (DEFINE_DELAY, (MODE), (ARG0), (ARG1))
|
1164 |
|
|
#define gen_rtx_DEFINE_COND_EXEC(MODE, ARG0, ARG1, ARG2) \
|
1165 |
|
|
gen_rtx_fmt_Ess (DEFINE_COND_EXEC, (MODE), (ARG0), (ARG1), (ARG2))
|
1166 |
|
|
#define gen_rtx_DEFINE_PREDICATE(MODE, ARG0, ARG1, ARG2) \
|
1167 |
|
|
gen_rtx_fmt_ses (DEFINE_PREDICATE, (MODE), (ARG0), (ARG1), (ARG2))
|
1168 |
|
|
#define gen_rtx_DEFINE_SPECIAL_PREDICATE(MODE, ARG0, ARG1, ARG2) \
|
1169 |
|
|
gen_rtx_fmt_ses (DEFINE_SPECIAL_PREDICATE, (MODE), (ARG0), (ARG1), (ARG2))
|
1170 |
|
|
#define gen_rtx_DEFINE_REGISTER_CONSTRAINT(MODE, ARG0, ARG1, ARG2) \
|
1171 |
|
|
gen_rtx_fmt_sss (DEFINE_REGISTER_CONSTRAINT, (MODE), (ARG0), (ARG1), (ARG2))
|
1172 |
|
|
#define gen_rtx_DEFINE_CONSTRAINT(MODE, ARG0, ARG1, ARG2) \
|
1173 |
|
|
gen_rtx_fmt_sse (DEFINE_CONSTRAINT, (MODE), (ARG0), (ARG1), (ARG2))
|
1174 |
|
|
#define gen_rtx_DEFINE_MEMORY_CONSTRAINT(MODE, ARG0, ARG1, ARG2) \
|
1175 |
|
|
gen_rtx_fmt_sse (DEFINE_MEMORY_CONSTRAINT, (MODE), (ARG0), (ARG1), (ARG2))
|
1176 |
|
|
#define gen_rtx_DEFINE_ADDRESS_CONSTRAINT(MODE, ARG0, ARG1, ARG2) \
|
1177 |
|
|
gen_rtx_fmt_sse (DEFINE_ADDRESS_CONSTRAINT, (MODE), (ARG0), (ARG1), (ARG2))
|
1178 |
|
|
#define gen_rtx_EXCLUSION_SET(MODE, ARG0, ARG1) \
|
1179 |
|
|
gen_rtx_fmt_ss (EXCLUSION_SET, (MODE), (ARG0), (ARG1))
|
1180 |
|
|
#define gen_rtx_PRESENCE_SET(MODE, ARG0, ARG1) \
|
1181 |
|
|
gen_rtx_fmt_ss (PRESENCE_SET, (MODE), (ARG0), (ARG1))
|
1182 |
|
|
#define gen_rtx_FINAL_PRESENCE_SET(MODE, ARG0, ARG1) \
|
1183 |
|
|
gen_rtx_fmt_ss (FINAL_PRESENCE_SET, (MODE), (ARG0), (ARG1))
|
1184 |
|
|
#define gen_rtx_ABSENCE_SET(MODE, ARG0, ARG1) \
|
1185 |
|
|
gen_rtx_fmt_ss (ABSENCE_SET, (MODE), (ARG0), (ARG1))
|
1186 |
|
|
#define gen_rtx_FINAL_ABSENCE_SET(MODE, ARG0, ARG1) \
|
1187 |
|
|
gen_rtx_fmt_ss (FINAL_ABSENCE_SET, (MODE), (ARG0), (ARG1))
|
1188 |
|
|
#define gen_rtx_DEFINE_AUTOMATON(MODE, ARG0) \
|
1189 |
|
|
gen_rtx_fmt_s (DEFINE_AUTOMATON, (MODE), (ARG0))
|
1190 |
|
|
#define gen_rtx_AUTOMATA_OPTION(MODE, ARG0) \
|
1191 |
|
|
gen_rtx_fmt_s (AUTOMATA_OPTION, (MODE), (ARG0))
|
1192 |
|
|
#define gen_rtx_DEFINE_RESERVATION(MODE, ARG0, ARG1) \
|
1193 |
|
|
gen_rtx_fmt_ss (DEFINE_RESERVATION, (MODE), (ARG0), (ARG1))
|
1194 |
|
|
#define gen_rtx_DEFINE_INSN_RESERVATION(MODE, ARG0, ARG1, ARG2, ARG3) \
|
1195 |
|
|
gen_rtx_fmt_sies (DEFINE_INSN_RESERVATION, (MODE), (ARG0), (ARG1), (ARG2), (ARG3))
|
1196 |
|
|
#define gen_rtx_DEFINE_ATTR(MODE, ARG0, ARG1, ARG2) \
|
1197 |
|
|
gen_rtx_fmt_sse (DEFINE_ATTR, (MODE), (ARG0), (ARG1), (ARG2))
|
1198 |
|
|
#define gen_rtx_DEFINE_ENUM_ATTR(MODE, ARG0, ARG1, ARG2) \
|
1199 |
|
|
gen_rtx_fmt_sse (DEFINE_ENUM_ATTR, (MODE), (ARG0), (ARG1), (ARG2))
|
1200 |
|
|
#define gen_rtx_ATTR(MODE, ARG0) \
|
1201 |
|
|
gen_rtx_fmt_s (ATTR, (MODE), (ARG0))
|
1202 |
|
|
#define gen_rtx_SET_ATTR(MODE, ARG0, ARG1) \
|
1203 |
|
|
gen_rtx_fmt_ss (SET_ATTR, (MODE), (ARG0), (ARG1))
|
1204 |
|
|
#define gen_rtx_SET_ATTR_ALTERNATIVE(MODE, ARG0, ARG1) \
|
1205 |
|
|
gen_rtx_fmt_sE (SET_ATTR_ALTERNATIVE, (MODE), (ARG0), (ARG1))
|
1206 |
|
|
#define gen_rtx_EQ_ATTR(MODE, ARG0, ARG1) \
|
1207 |
|
|
gen_rtx_fmt_ss (EQ_ATTR, (MODE), (ARG0), (ARG1))
|
1208 |
|
|
#define gen_rtx_EQ_ATTR_ALT(MODE, ARG0, ARG1) \
|
1209 |
|
|
gen_rtx_fmt_ii (EQ_ATTR_ALT, (MODE), (ARG0), (ARG1))
|
1210 |
|
|
#define gen_rtx_ATTR_FLAG(MODE, ARG0) \
|
1211 |
|
|
gen_rtx_fmt_s (ATTR_FLAG, (MODE), (ARG0))
|
1212 |
|
|
#define gen_rtx_COND(MODE, ARG0, ARG1) \
|
1213 |
|
|
gen_rtx_fmt_Ee (COND, (MODE), (ARG0), (ARG1))
|
1214 |
|
|
#define gen_rtx_DEFINE_SUBST(MODE, ARG0, ARG1, ARG2, ARG3) \
|
1215 |
|
|
gen_rtx_fmt_sEsE (DEFINE_SUBST, (MODE), (ARG0), (ARG1), (ARG2), (ARG3))
|
1216 |
|
|
#define gen_rtx_DEFINE_SUBST_ATTR(MODE, ARG0, ARG1, ARG2, ARG3) \
|
1217 |
|
|
gen_rtx_fmt_ssss (DEFINE_SUBST_ATTR, (MODE), (ARG0), (ARG1), (ARG2), (ARG3))
|
1218 |
|
|
|
1219 |
|
|
#endif /* GCC_GENRTL_H */
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