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.\" ========================================================================

.\"

.IX Title "AS 1"

.TH AS 1 "2013-04-24" "binutils-2.23.51" "GNU Development Tools"

.\" For nroff, turn off justification.  Always turn off hyphenation; it makes

.\" way too many mistakes in technical documents.

.if n .ad l

.nh

.SH "NAME"

AS \- the portable GNU assembler.

.SH "SYNOPSIS"

.IX Header "SYNOPSIS"

as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-D\fR]

 [\fB\-\-compress\-debug\-sections\fR]  [\fB\-\-nocompress\-debug\-sections\fR]

 [\fB\-\-debug\-prefix\-map\fR \fIold\fR=\fInew\fR]

 [\fB\-\-defsym\fR \fIsym\fR=\fIval\fR] [\fB\-f\fR] [\fB\-g\fR] [\fB\-\-gstabs\fR]

 [\fB\-\-gstabs+\fR] [\fB\-\-gdwarf\-2\fR] [\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR] [\fB\-J\fR]

 [\fB\-K\fR] [\fB\-L\fR] [\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR]

 [\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR]

 [\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR] [\fB\-\-keep\-locals\fR] [\fB\-o\fR

 \fIobjfile\fR] [\fB\-R\fR] [\fB\-\-reduce\-memory\-overheads\fR] [\fB\-\-statistics\fR]

 [\fB\-v\fR] [\fB\-version\fR] [\fB\-\-version\fR] [\fB\-W\fR] [\fB\-\-warn\fR]

 [\fB\-\-fatal\-warnings\fR] [\fB\-w\fR] [\fB\-x\fR] [\fB\-Z\fR] [\fB@\fR\fI\s-1FILE\s0\fR]

 [\fB\-\-size\-check=[error|warning]\fR]

 [\fB\-\-target\-help\fR] [\fItarget-options\fR]

 [\fB\-\-\fR|\fIfiles\fR ...]

.PP

\&\fITarget AArch64 options:\fR

   [\fB\-EB\fR|\fB\-EL\fR]

.PP

\&\fITarget Alpha options:\fR

   [\fB\-m\fR\fIcpu\fR]

   [\fB\-mdebug\fR | \fB\-no\-mdebug\fR]

   [\fB\-replace\fR | \fB\-noreplace\fR]

   [\fB\-relax\fR] [\fB\-g\fR] [\fB\-G\fR\fIsize\fR]

   [\fB\-F\fR] [\fB\-32addr\fR]

.PP

\&\fITarget \s-1ARC\s0 options:\fR

   [\fB\-marc[5|6|7|8]\fR]

   [\fB\-EB\fR|\fB\-EL\fR]

.PP

\&\fITarget \s-1ARM\s0 options:\fR

   [\fB\-mcpu\fR=\fIprocessor\fR[+\fIextension\fR...]]

   [\fB\-march\fR=\fIarchitecture\fR[+\fIextension\fR...]]

   [\fB\-mfpu\fR=\fIfloating-point-format\fR]

   [\fB\-mfloat\-abi\fR=\fIabi\fR]

   [\fB\-meabi\fR=\fIver\fR]

   [\fB\-mthumb\fR]

   [\fB\-EB\fR|\fB\-EL\fR]

   [\fB\-mapcs\-32\fR|\fB\-mapcs\-26\fR|\fB\-mapcs\-float\fR|

    \fB\-mapcs\-reentrant\fR]

   [\fB\-mthumb\-interwork\fR] [\fB\-k\fR]

.PP

\&\fITarget Blackfin options:\fR

   [\fB\-mcpu\fR=\fIprocessor\fR[\-\fIsirevision\fR]]

   [\fB\-mfdpic\fR]

   [\fB\-mno\-fdpic\fR]

   [\fB\-mnopic\fR]

.PP

\&\fITarget \s-1CRIS\s0 options:\fR

   [\fB\-\-underscore\fR | \fB\-\-no\-underscore\fR]

   [\fB\-\-pic\fR] [\fB\-N\fR]

   [\fB\-\-emulation=criself\fR | \fB\-\-emulation=crisaout\fR]

   [\fB\-\-march=v0_v10\fR | \fB\-\-march=v10\fR | \fB\-\-march=v32\fR | \fB\-\-march=common_v10_v32\fR]

.PP

\&\fITarget D10V options:\fR

   [\fB\-O\fR]

.PP

\&\fITarget D30V options:\fR

   [\fB\-O\fR|\fB\-n\fR|\fB\-N\fR]

.PP

\&\fITarget \s-1EPIPHANY\s0 options:\fR

   [\fB\-mepiphany\fR|\fB\-mepiphany16\fR]

.PP

\&\fITarget H8/300 options:\fR

   [\-h\-tick\-hex]

.PP

\&\fITarget i386 options:\fR

   [\fB\-\-32\fR|\fB\-\-x32\fR|\fB\-\-64\fR] [\fB\-n\fR]

   [\fB\-march\fR=\fI\s-1CPU\s0\fR[+\fI\s-1EXTENSION\s0\fR...]] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR]

.PP

\&\fITarget i960 options:\fR

   [\fB\-ACA\fR|\fB\-ACA_A\fR|\fB\-ACB\fR|\fB\-ACC\fR|\fB\-AKA\fR|\fB\-AKB\fR|

    \fB\-AKC\fR|\fB\-AMC\fR]

   [\fB\-b\fR] [\fB\-no\-relax\fR]

.PP

\&\fITarget \s-1IA\-64\s0 options:\fR

   [\fB\-mconstant\-gp\fR|\fB\-mauto\-pic\fR]

   [\fB\-milp32\fR|\fB\-milp64\fR|\fB\-mlp64\fR|\fB\-mp64\fR]

   [\fB\-mle\fR|\fBmbe\fR]

   [\fB\-mtune=itanium1\fR|\fB\-mtune=itanium2\fR]

   [\fB\-munwind\-check=warning\fR|\fB\-munwind\-check=error\fR]

   [\fB\-mhint.b=ok\fR|\fB\-mhint.b=warning\fR|\fB\-mhint.b=error\fR]

   [\fB\-x\fR|\fB\-xexplicit\fR] [\fB\-xauto\fR] [\fB\-xdebug\fR]

.PP

\&\fITarget \s-1IP2K\s0 options:\fR

   [\fB\-mip2022\fR|\fB\-mip2022ext\fR]

.PP

\&\fITarget M32C options:\fR

   [\fB\-m32c\fR|\fB\-m16c\fR] [\-relax] [\-h\-tick\-hex]

.PP

\&\fITarget M32R options:\fR

   [\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR|

   \fB\-\-W[n]p\fR]

.PP

\&\fITarget M680X0 options:\fR

   [\fB\-l\fR] [\fB\-m68000\fR|\fB\-m68010\fR|\fB\-m68020\fR|...]

.PP

\&\fITarget M68HC11 options:\fR

   [\fB\-m68hc11\fR|\fB\-m68hc12\fR|\fB\-m68hcs12\fR|\fB\-mm9s12x\fR|\fB\-mm9s12xg\fR]

   [\fB\-mshort\fR|\fB\-mlong\fR]

   [\fB\-mshort\-double\fR|\fB\-mlong\-double\fR]

   [\fB\-\-force\-long\-branches\fR] [\fB\-\-short\-branches\fR]

   [\fB\-\-strict\-direct\-mode\fR] [\fB\-\-print\-insn\-syntax\fR]

   [\fB\-\-print\-opcodes\fR] [\fB\-\-generate\-example\fR]

.PP

\&\fITarget \s-1MCORE\s0 options:\fR

   [\fB\-jsri2bsr\fR] [\fB\-sifilter\fR] [\fB\-relax\fR]

   [\fB\-mcpu=[210|340]\fR]

\&\fITarget \s-1MICROBLAZE\s0 options:\fR

.PP

\&\fITarget \s-1MIPS\s0 options:\fR

   [\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR[\fIoptimization level\fR]]

   [\fB\-g\fR[\fIdebug level\fR]] [\fB\-G\fR \fInum\fR] [\fB\-KPIC\fR] [\fB\-call_shared\fR]

   [\fB\-non_shared\fR] [\fB\-xgot\fR [\fB\-mvxworks\-pic\fR]

   [\fB\-mabi\fR=\fI\s-1ABI\s0\fR] [\fB\-32\fR] [\fB\-n32\fR] [\fB\-64\fR] [\fB\-mfp32\fR] [\fB\-mgp32\fR]

   [\fB\-march\fR=\fI\s-1CPU\s0\fR] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] [\fB\-mips1\fR] [\fB\-mips2\fR]

   [\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR] [\fB\-mips32\fR] [\fB\-mips32r2\fR]

   [\fB\-mips64\fR] [\fB\-mips64r2\fR]

   [\fB\-construct\-floats\fR] [\fB\-no\-construct\-floats\fR]

   [\fB\-trap\fR] [\fB\-no\-break\fR] [\fB\-break\fR] [\fB\-no\-trap\fR]

   [\fB\-mips16\fR] [\fB\-no\-mips16\fR]

   [\fB\-mmicromips\fR] [\fB\-mno\-micromips\fR]

   [\fB\-msmartmips\fR] [\fB\-mno\-smartmips\fR]

   [\fB\-mips3d\fR] [\fB\-no\-mips3d\fR]

   [\fB\-mdmx\fR] [\fB\-no\-mdmx\fR]

   [\fB\-mdsp\fR] [\fB\-mno\-dsp\fR]

   [\fB\-mdspr2\fR] [\fB\-mno\-dspr2\fR]

   [\fB\-mmt\fR] [\fB\-mno\-mt\fR]

   [\fB\-mmcu\fR] [\fB\-mno\-mcu\fR]

   [\fB\-mfix7000\fR] [\fB\-mno\-fix7000\fR]

   [\fB\-mfix\-vr4120\fR] [\fB\-mno\-fix\-vr4120\fR]

   [\fB\-mfix\-vr4130\fR] [\fB\-mno\-fix\-vr4130\fR]

   [\fB\-mdebug\fR] [\fB\-no\-mdebug\fR]

   [\fB\-mpdr\fR] [\fB\-mno\-pdr\fR]

.PP

\&\fITarget \s-1MMIX\s0 options:\fR

   [\fB\-\-fixed\-special\-register\-names\fR] [\fB\-\-globalize\-symbols\fR]

   [\fB\-\-gnu\-syntax\fR] [\fB\-\-relax\fR] [\fB\-\-no\-predefined\-symbols\fR]

   [\fB\-\-no\-expand\fR] [\fB\-\-no\-merge\-gregs\fR] [\fB\-x\fR]

   [\fB\-\-linker\-allocated\-gregs\fR]

.PP

\&\fITarget \s-1PDP11\s0 options:\fR

   [\fB\-mpic\fR|\fB\-mno\-pic\fR] [\fB\-mall\fR] [\fB\-mno\-extensions\fR]

   [\fB\-m\fR\fIextension\fR|\fB\-mno\-\fR\fIextension\fR]

   [\fB\-m\fR\fIcpu\fR] [\fB\-m\fR\fImachine\fR]

.PP

\&\fITarget picoJava options:\fR

   [\fB\-mb\fR|\fB\-me\fR]

.PP

\&\fITarget PowerPC options:\fR

   [\fB\-a32\fR|\fB\-a64\fR]

   [\fB\-mpwrx\fR|\fB\-mpwr2\fR|\fB\-mpwr\fR|\fB\-m601\fR|\fB\-mppc\fR|\fB\-mppc32\fR|\fB\-m603\fR|\fB\-m604\fR|\fB\-m403\fR|\fB\-m405\fR|

    \fB\-m440\fR|\fB\-m464\fR|\fB\-m476\fR|\fB\-m7400\fR|\fB\-m7410\fR|\fB\-m7450\fR|\fB\-m7455\fR|\fB\-m750cl\fR|\fB\-mppc64\fR|

    \fB\-m620\fR|\fB\-me500\fR|\fB\-e500x2\fR|\fB\-me500mc\fR|\fB\-me500mc64\fR|\fB\-me5500\fR|\fB\-me6500\fR|\fB\-mppc64bridge\fR|

    \fB\-mbooke\fR|\fB\-mpower4\fR|\fB\-mpwr4\fR|\fB\-mpower5\fR|\fB\-mpwr5\fR|\fB\-mpwr5x\fR|\fB\-mpower6\fR|\fB\-mpwr6\fR|

    \fB\-mpower7\fR|\fB\-mpwr7\fR|\fB\-ma2\fR|\fB\-mcell\fR|\fB\-mspe\fR|\fB\-mtitan\fR|\fB\-me300\fR|\fB\-mvle\fR|\fB\-mcom\fR]

   [\fB\-many\fR] [\fB\-maltivec\fR|\fB\-mvsx\fR]

   [\fB\-mregnames\fR|\fB\-mno\-regnames\fR]

   [\fB\-mrelocatable\fR|\fB\-mrelocatable\-lib\fR|\fB\-K \s-1PIC\s0\fR] [\fB\-memb\fR]

   [\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-le\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR|\fB\-be\fR]

   [\fB\-msolaris\fR|\fB\-mno\-solaris\fR]

   [\fB\-nops=\fR\fIcount\fR]

.PP

\&\fITarget \s-1RX\s0 options:\fR

   [\fB\-mlittle\-endian\fR|\fB\-mbig\-endian\fR]

   [\fB\-m32bit\-doubles\fR|\fB\-m64bit\-doubles\fR]

   [\fB\-muse\-conventional\-section\-names\fR]

   [\fB\-msmall\-data\-limit\fR]

   [\fB\-mpid\fR]

   [\fB\-mrelax\fR]

   [\fB\-mint\-register=\fR\fInumber\fR]

   [\fB\-mgcc\-abi\fR|\fB\-mrx\-abi\fR]

.PP

\&\fITarget s390 options:\fR

   [\fB\-m31\fR|\fB\-m64\fR] [\fB\-mesa\fR|\fB\-mzarch\fR] [\fB\-march\fR=\fI\s-1CPU\s0\fR]

   [\fB\-mregnames\fR|\fB\-mno\-regnames\fR]

   [\fB\-mwarn\-areg\-zero\fR]

.PP

\&\fITarget \s-1SCORE\s0 options:\fR

   [\fB\-EB\fR][\fB\-EL\fR][\fB\-FIXDD\fR][\fB\-NWARN\fR]

   [\fB\-SCORE5\fR][\fB\-SCORE5U\fR][\fB\-SCORE7\fR][\fB\-SCORE3\fR]

   [\fB\-march=score7\fR][\fB\-march=score3\fR]

   [\fB\-USE_R1\fR][\fB\-KPIC\fR][\fB\-O0\fR][\fB\-G\fR \fInum\fR][\fB\-V\fR]

.PP

\&\fITarget \s-1SPARC\s0 options:\fR

   [\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR

    \fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av9\fR|\fB\-Av9a\fR]

   [\fB\-xarch=v8plus\fR|\fB\-xarch=v8plusa\fR] [\fB\-bump\fR]

   [\fB\-32\fR|\fB\-64\fR]

.PP

\&\fITarget \s-1TIC54X\s0 options:\fR

 [\fB\-mcpu=54[123589]\fR|\fB\-mcpu=54[56]lp\fR] [\fB\-mfar\-mode\fR|\fB\-mf\fR]

 [\fB\-merrors\-to\-file\fR \fI\fR|\fB\-me\fR \fI\fR]

.PP

\&\fITarget \s-1TIC6X\s0 options:\fR

   [\fB\-march=\fR\fIarch\fR] [\fB\-mbig\-endian\fR|\fB\-mlittle\-endian\fR]

   [\fB\-mdsbt\fR|\fB\-mno\-dsbt\fR] [\fB\-mpid=no\fR|\fB\-mpid=near\fR|\fB\-mpid=far\fR]

   [\fB\-mpic\fR|\fB\-mno\-pic\fR]

.PP

\&\fITarget TILE-Gx options:\fR

   [\fB\-m32\fR|\fB\-m64\fR][\fB\-EB\fR][\fB\-EL\fR]

.PP

\&\fITarget Xtensa options:\fR

 [\fB\-\-[no\-]text\-section\-literals\fR] [\fB\-\-[no\-]absolute\-literals\fR]

 [\fB\-\-[no\-]target\-align\fR] [\fB\-\-[no\-]longcalls\fR]

 [\fB\-\-[no\-]transform\fR]

 [\fB\-\-rename\-section\fR \fIoldname\fR=\fInewname\fR]

.PP

\&\fITarget Z80 options:\fR

  [\fB\-z80\fR] [\fB\-r800\fR]

  [ \fB\-ignore\-undocumented\-instructions\fR] [\fB\-Wnud\fR]

  [ \fB\-ignore\-unportable\-instructions\fR] [\fB\-Wnup\fR]

  [ \fB\-warn\-undocumented\-instructions\fR] [\fB\-Wud\fR]

  [ \fB\-warn\-unportable\-instructions\fR] [\fB\-Wup\fR]

  [ \fB\-forbid\-undocumented\-instructions\fR] [\fB\-Fud\fR]

  [ \fB\-forbid\-unportable\-instructions\fR] [\fB\-Fup\fR]

.SH "DESCRIPTION"

.IX Header "DESCRIPTION"

\&\s-1GNU\s0 \fBas\fR is really a family of assemblers.

If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you

should find a fairly similar environment when you use it on another

architecture.  Each version has much in common with the others,

including object file formats, most assembler directives (often called

\&\fIpseudo-ops\fR) and assembler syntax.

.PP

\&\fBas\fR is primarily intended to assemble the output of the

\&\s-1GNU\s0 C compiler \f(CW\*(C`gcc\*(C'\fR for use by the linker

\&\f(CW\*(C`ld\*(C'\fR.  Nevertheless, we've tried to make \fBas\fR

assemble correctly everything that other assemblers for the same

machine would assemble.

Any exceptions are documented explicitly.

This doesn't mean \fBas\fR always uses the same syntax as another

assembler for the same architecture; for example, we know of several

incompatible versions of 680x0 assembly language syntax.

.PP

Each time you run \fBas\fR it assembles exactly one source

program.  The source program is made up of one or more files.

(The standard input is also a file.)

.PP

You give \fBas\fR a command line that has zero or more input file

names.  The input files are read (from left file name to right).  A

command line argument (in any position) that has no special meaning

is taken to be an input file name.

.PP

If you give \fBas\fR no file names it attempts to read one input file

from the \fBas\fR standard input, which is normally your terminal.  You

may have to type \fBctl-D\fR to tell \fBas\fR there is no more program

to assemble.

.PP

Use \fB\-\-\fR if you need to explicitly name the standard input file

in your command line.

.PP

If the source is empty, \fBas\fR produces a small, empty object

file.

.PP

\&\fBas\fR may write warnings and error messages to the standard error

file (usually your terminal).  This should not happen when  a compiler

runs \fBas\fR automatically.  Warnings report an assumption made so

that \fBas\fR could keep assembling a flawed program; errors report a

grave problem that stops the assembly.

.PP

If you are invoking \fBas\fR via the \s-1GNU\s0 C compiler,

you can use the \fB\-Wa\fR option to pass arguments through to the assembler.

The assembler arguments must be separated from each other (and the \fB\-Wa\fR)

by commas.  For example:

.PP

.Vb 1

\&        gcc \-c \-g \-O \-Wa,\-alh,\-L file.c

.Ve

.PP

This passes two options to the assembler: \fB\-alh\fR (emit a listing to

standard output with high-level and assembly source) and \fB\-L\fR (retain

local symbols in the symbol table).

.PP

Usually you do not need to use this \fB\-Wa\fR mechanism, since many compiler

command-line options are automatically passed to the assembler by the compiler.

(You can call the \s-1GNU\s0 compiler driver with the \fB\-v\fR option to see

precisely what options it passes to each compilation pass, including the

assembler.)

.SH "OPTIONS"

.IX Header "OPTIONS"

.IP "\fB@\fR\fIfile\fR" 4

.IX Item "@file"

Read command-line options from \fIfile\fR.  The options read are

inserted in place of the original @\fIfile\fR option.  If \fIfile\fR

does not exist, or cannot be read, then the option will be treated

literally, and not removed.

.Sp

Options in \fIfile\fR are separated by whitespace.  A whitespace

character may be included in an option by surrounding the entire

option in either single or double quotes.  Any character (including a

backslash) may be included by prefixing the character to be included

with a backslash.  The \fIfile\fR may itself contain additional

@\fIfile\fR options; any such options will be processed recursively.

.IP "\fB\-a[cdghlmns]\fR" 4

.IX Item "-a[cdghlmns]"

Turn on listings, in any of a variety of ways:

.RS 4

.IP "\fB\-ac\fR" 4

.IX Item "-ac"

omit false conditionals

.IP "\fB\-ad\fR" 4

.IX Item "-ad"

omit debugging directives

.IP "\fB\-ag\fR" 4

.IX Item "-ag"

include general information, like as version and options passed

.IP "\fB\-ah\fR" 4

.IX Item "-ah"

include high-level source

.IP "\fB\-al\fR" 4

.IX Item "-al"

include assembly

.IP "\fB\-am\fR" 4

.IX Item "-am"

include macro expansions

.IP "\fB\-an\fR" 4

.IX Item "-an"

omit forms processing

.IP "\fB\-as\fR" 4

.IX Item "-as"

include symbols

.IP "\fB=file\fR" 4

.IX Item "=file"

set the name of the listing file

.RE

.RS 4

.Sp

You may combine these options; for example, use \fB\-aln\fR for assembly

listing without forms processing.  The \fB=file\fR option, if used, must be

the last one.  By itself, \fB\-a\fR defaults to \fB\-ahls\fR.

.RE

.IP "\fB\-\-alternate\fR" 4

.IX Item "--alternate"

Begin in alternate macro mode.

.IP "\fB\-\-compress\-debug\-sections\fR" 4

.IX Item "--compress-debug-sections"

Compress \s-1DWARF\s0 debug sections using zlib.  The debug sections are renamed

to begin with \fB.zdebug\fR, and the resulting object file may not be

compatible with older linkers and object file utilities.

.IP "\fB\-\-nocompress\-debug\-sections\fR" 4

.IX Item "--nocompress-debug-sections"

Do not compress \s-1DWARF\s0 debug sections.  This is the default.

.IP "\fB\-D\fR" 4

.IX Item "-D"

Ignored.  This option is accepted for script compatibility with calls to

other assemblers.

.IP "\fB\-\-debug\-prefix\-map\fR \fIold\fR\fB=\fR\fInew\fR" 4

.IX Item "--debug-prefix-map old=new"

When assembling files in directory \fI\fIold\fI\fR, record debugging

information describing them as in \fI\fInew\fI\fR instead.

.IP "\fB\-\-defsym\fR \fIsym\fR\fB=\fR\fIvalue\fR" 4

.IX Item "--defsym sym=value"

Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file.

\&\fIvalue\fR must be an integer constant.  As in C, a leading \fB0x\fR

indicates a hexadecimal value, and a leading \fB0\fR indicates an octal

value.  The value of the symbol can be overridden inside a source file via the

use of a \f(CW\*(C`.set\*(C'\fR pseudo-op.

.IP "\fB\-f\fR" 4

.IX Item "-f"

\&\*(L"fast\*(R"\-\-\-skip whitespace and comment preprocessing (assume source is

compiler output).

.IP "\fB\-g\fR" 4

.IX Item "-g"

.PD 0

.IP "\fB\-\-gen\-debug\fR" 4

.IX Item "--gen-debug"

.PD

Generate debugging information for each assembler source line using whichever

debug format is preferred by the target.  This currently means either \s-1STABS\s0,

\&\s-1ECOFF\s0 or \s-1DWARF2\s0.

.IP "\fB\-\-gstabs\fR" 4

.IX Item "--gstabs"

Generate stabs debugging information for each assembler line.  This

may help debugging assembler code, if the debugger can handle it.

.IP "\fB\-\-gstabs+\fR" 4

.IX Item "--gstabs+"

Generate stabs debugging information for each assembler line, with \s-1GNU\s0

extensions that probably only gdb can handle, and that could make other

debuggers crash or refuse to read your program.  This

may help debugging assembler code.  Currently the only \s-1GNU\s0 extension is

the location of the current working directory at assembling time.

.IP "\fB\-\-gdwarf\-2\fR" 4

.IX Item "--gdwarf-2"

Generate \s-1DWARF2\s0 debugging information for each assembler line.  This

may help debugging assembler code, if the debugger can handle it.  Note\-\-\-this

option is only supported by some targets, not all of them.

.IP "\fB\-\-size\-check=error\fR" 4

.IX Item "--size-check=error"

.PD 0

.IP "\fB\-\-size\-check=warning\fR" 4

.IX Item "--size-check=warning"

.PD

Issue an error or warning for invalid \s-1ELF\s0 .size directive.

.IP "\fB\-\-help\fR" 4

.IX Item "--help"

Print a summary of the command line options and exit.

.IP "\fB\-\-target\-help\fR" 4

.IX Item "--target-help"

Print a summary of all target specific options and exit.

.IP "\fB\-I\fR \fIdir\fR" 4

.IX Item "-I dir"

Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR directives.

.IP "\fB\-J\fR" 4

.IX Item "-J"

Don't warn about signed overflow.

.IP "\fB\-K\fR" 4

.IX Item "-K"

Issue warnings when difference tables altered for long displacements.

.IP "\fB\-L\fR" 4

.IX Item "-L"

.PD 0

.IP "\fB\-\-keep\-locals\fR" 4

.IX Item "--keep-locals"

.PD

Keep (in the symbol table) local symbols.  These symbols start with

system-specific local label prefixes, typically \fB.L\fR for \s-1ELF\s0 systems

or \fBL\fR for traditional a.out systems.

.IP "\fB\-\-listing\-lhs\-width=\fR\fInumber\fR" 4

.IX Item "--listing-lhs-width=number"

Set the maximum width, in words, of the output data column for an assembler

listing to \fInumber\fR.

.IP "\fB\-\-listing\-lhs\-width2=\fR\fInumber\fR" 4

.IX Item "--listing-lhs-width2=number"

Set the maximum width, in words, of the output data column for continuation

lines in an assembler listing to \fInumber\fR.

.IP "\fB\-\-listing\-rhs\-width=\fR\fInumber\fR" 4

.IX Item "--listing-rhs-width=number"

Set the maximum width of an input source line, as displayed in a listing, to

\&\fInumber\fR bytes.

.IP "\fB\-\-listing\-cont\-lines=\fR\fInumber\fR" 4

.IX Item "--listing-cont-lines=number"

Set the maximum number of lines printed in a listing for a single line of input

to \fInumber\fR + 1.

.IP "\fB\-o\fR \fIobjfile\fR" 4

.IX Item "-o objfile"

Name the object-file output from \fBas\fR \fIobjfile\fR.

.IP "\fB\-R\fR" 4

.IX Item "-R"

Fold the data section into the text section.

.Sp

Set the default size of \s-1GAS\s0's hash tables to a prime number close to

\&\fInumber\fR.  Increasing this value can reduce the length of time it takes the

assembler to perform its tasks, at the expense of increasing the assembler's

memory requirements.  Similarly reducing this value can reduce the memory

requirements at the expense of speed.

.IP "\fB\-\-reduce\-memory\-overheads\fR" 4

.IX Item "--reduce-memory-overheads"

This option reduces \s-1GAS\s0's memory requirements, at the expense of making the

assembly processes slower.  Currently this switch is a synonym for

\&\fB\-\-hash\-size=4051\fR, but in the future it may have other effects as well.

.IP "\fB\-\-statistics\fR" 4

.IX Item "--statistics"

Print the maximum space (in bytes) and total time (in seconds) used by

assembly.

.IP "\fB\-\-strip\-local\-absolute\fR" 4

.IX Item "--strip-local-absolute"

Remove local absolute symbols from the outgoing symbol table.

.IP "\fB\-v\fR" 4

.IX Item "-v"

.PD 0

.IP "\fB\-version\fR" 4

.IX Item "-version"

.PD

Print the \fBas\fR version.

.IP "\fB\-\-version\fR" 4

.IX Item "--version"

Print the \fBas\fR version and exit.

.IP "\fB\-W\fR" 4

.IX Item "-W"

.PD 0

.IP "\fB\-\-no\-warn\fR" 4

.IX Item "--no-warn"

.PD

Suppress warning messages.

.IP "\fB\-\-fatal\-warnings\fR" 4

.IX Item "--fatal-warnings"

Treat warnings as errors.

.IP "\fB\-\-warn\fR" 4

.IX Item "--warn"

Don't suppress warning messages or treat them as errors.

.IP "\fB\-w\fR" 4

.IX Item "-w"

Ignored.

.IP "\fB\-x\fR" 4

.IX Item "-x"

Ignored.

.IP "\fB\-Z\fR" 4

.IX Item "-Z"

Generate an object file even after errors.

.IP "\fB\-\- |\fR \fIfiles\fR \fB...\fR" 4

.IX Item "-- | files ..."

Standard input, or source files to assemble.

.PP

The following options are available when as is configured for the

64\-bit mode of the \s-1ARM\s0 Architecture (AArch64).

.IP "\fB\-EB\fR" 4

.IX Item "-EB"

This option specifies that the output generated by the assembler should

be marked as being encoded for a big-endian processor.

.IP "\fB\-EL\fR" 4

.IX Item "-EL"

This option specifies that the output generated by the assembler should

be marked as being encoded for a little-endian processor.

.PP

The following options are available when as is configured for an Alpha

processor.

.IP "\fB\-m\fR\fIcpu\fR" 4

.IX Item "-mcpu"

This option specifies the target processor.  If an attempt is made to

assemble an instruction which will not execute on the target processor,

the assembler may either expand the instruction as a macro or issue an

error message.  This option is equivalent to the \f(CW\*(C`.arch\*(C'\fR directive.

.Sp

The following processor names are recognized:

\&\f(CW21064\fR,

\&\f(CW\*(C`21064a\*(C'\fR,

\&\f(CW21066\fR,

\&\f(CW21068\fR,

\&\f(CW21164\fR,

\&\f(CW\*(C`21164a\*(C'\fR,

\&\f(CW\*(C`21164pc\*(C'\fR,

\&\f(CW21264\fR,

\&\f(CW\*(C`21264a\*(C'\fR,

\&\f(CW\*(C`21264b\*(C'\fR,

\&\f(CW\*(C`ev4\*(C'\fR,

\&\f(CW\*(C`ev5\*(C'\fR,

\&\f(CW\*(C`lca45\*(C'\fR,

\&\f(CW\*(C`ev5\*(C'\fR,

\&\f(CW\*(C`ev56\*(C'\fR,

\&\f(CW\*(C`pca56\*(C'\fR,

\&\f(CW\*(C`ev6\*(C'\fR,

\&\f(CW\*(C`ev67\*(C'\fR,

\&\f(CW\*(C`ev68\*(C'\fR.

The special name \f(CW\*(C`all\*(C'\fR may be used to allow the assembler to accept

instructions valid for any Alpha processor.

.Sp

In order to support existing practice in \s-1OSF/1\s0 with respect to \f(CW\*(C`.arch\*(C'\fR,

and existing practice within \fB\s-1MILO\s0\fR (the Linux \s-1ARC\s0 bootloader), the

numbered processor names (e.g. 21064) enable the processor-specific PALcode

instructions, while the \*(L"electro-vlasic\*(R" names (e.g. \f(CW\*(C`ev4\*(C'\fR) do not.

.IP "\fB\-mdebug\fR" 4

.IX Item "-mdebug"

.PD 0

.IP "\fB\-no\-mdebug\fR" 4

.IX Item "-no-mdebug"

.PD

Enables or disables the generation of \f(CW\*(C`.mdebug\*(C'\fR encapsulation for

stabs directives and procedure descriptors.  The default is to automatically

enable \f(CW\*(C`.mdebug\*(C'\fR when the first stabs directive is seen.

.IP "\fB\-relax\fR" 4

.IX Item "-relax"

This option forces all relocations to be put into the object file, instead

of saving space and resolving some relocations at assembly time.  Note that

this option does not propagate all symbol arithmetic into the object file,

because not all symbol arithmetic can be represented.  However, the option

can still be useful in specific applications.

.IP "\fB\-replace\fR" 4

.IX Item "-replace"

.PD 0

.IP "\fB\-noreplace\fR" 4

.IX Item "-noreplace"

.PD

Enables or disables the optimization of procedure calls, both at assemblage

and at link time.  These options are only available for \s-1VMS\s0 targets and

\&\f(CW\*(C`\-replace\*(C'\fR is the default.  See section 1.4.1 of the OpenVMS Linker

Utility Manual.

.IP "\fB\-g\fR" 4

.IX Item "-g"

This option is used when the compiler generates debug information.  When

\&\fBgcc\fR is using \fBmips-tfile\fR to generate debug

information for \s-1ECOFF\s0, local labels must be passed through to the object

file.  Otherwise this option has no effect.

.IP "\fB\-G\fR\fIsize\fR" 4

.IX Item "-Gsize"

A local common symbol larger than \fIsize\fR is placed in \f(CW\*(C`.bss\*(C'\fR,

while smaller symbols are placed in \f(CW\*(C`.sbss\*(C'\fR.

.IP "\fB\-F\fR" 4

.IX Item "-F"

.PD 0

.IP "\fB\-32addr\fR" 4

.IX Item "-32addr"

.PD

These options are ignored for backward compatibility.

.PP

The following options are available when as is configured for

an \s-1ARC\s0 processor.

.IP "\fB\-marc[5|6|7|8]\fR" 4

.IX Item "-marc[5|6|7|8]"

This option selects the core processor variant.

.IP "\fB\-EB | \-EL\fR" 4

.IX Item "-EB | -EL"

Select either big-endian (\-EB) or little-endian (\-EL) output.

.PP

The following options are available when as is configured for the \s-1ARM\s0

processor family.

.IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4

.IX Item "-mcpu=processor[+extension...]"

Specify which \s-1ARM\s0 processor variant is the target.

.IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4

.IX Item "-march=architecture[+extension...]"

Specify which \s-1ARM\s0 architecture variant is used by the target.

.IP "\fB\-mfpu=\fR\fIfloating-point-format\fR" 4

.IX Item "-mfpu=floating-point-format"

Select which Floating Point architecture is the target.

.IP "\fB\-mfloat\-abi=\fR\fIabi\fR" 4

.IX Item "-mfloat-abi=abi"

Select which floating point \s-1ABI\s0 is in use.

.IP "\fB\-mthumb\fR" 4

.IX Item "-mthumb"

Enable Thumb only instruction decoding.

.IP "\fB\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant\fR" 4

.IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant"

Select which procedure calling convention is in use.

.IP "\fB\-EB | \-EL\fR" 4

.IX Item "-EB | -EL"

Select either big-endian (\-EB) or little-endian (\-EL) output.

.IP "\fB\-mthumb\-interwork\fR" 4

.IX Item "-mthumb-interwork"

Specify that the code has been generated with interworking between Thumb and

\&\s-1ARM\s0 code in mind.

.IP "\fB\-k\fR" 4

.IX Item "-k"

Specify that \s-1PIC\s0 code has been generated.

.PP

The following options are available when as is configured for

the Blackfin processor family.

.IP "\fB\-mcpu=\fR\fIprocessor\fR[\fB\-\fR\fIsirevision\fR]" 4

.IX Item "-mcpu=processor[-sirevision]"

This option specifies the target processor.  The optional \fIsirevision\fR

is not used in assembler.  It's here such that \s-1GCC\s0 can easily pass down its

\&\f(CW\*(C`\-mcpu=\*(C'\fR option.  The assembler will issue an

error message if an attempt is made to assemble an instruction which

will not execute on the target processor.  The following processor names are

recognized:

\&\f(CW\*(C`bf504\*(C'\fR,

\&\f(CW\*(C`bf506\*(C'\fR,

\&\f(CW\*(C`bf512\*(C'\fR,

\&\f(CW\*(C`bf514\*(C'\fR,

\&\f(CW\*(C`bf516\*(C'\fR,

\&\f(CW\*(C`bf518\*(C'\fR,

\&\f(CW\*(C`bf522\*(C'\fR,

\&\f(CW\*(C`bf523\*(C'\fR,

\&\f(CW\*(C`bf524\*(C'\fR,

\&\f(CW\*(C`bf525\*(C'\fR,

\&\f(CW\*(C`bf526\*(C'\fR,

\&\f(CW\*(C`bf527\*(C'\fR,

\&\f(CW\*(C`bf531\*(C'\fR,

\&\f(CW\*(C`bf532\*(C'\fR,

\&\f(CW\*(C`bf533\*(C'\fR,

\&\f(CW\*(C`bf534\*(C'\fR,

\&\f(CW\*(C`bf535\*(C'\fR (not implemented yet),

\&\f(CW\*(C`bf536\*(C'\fR,

\&\f(CW\*(C`bf537\*(C'\fR,

\&\f(CW\*(C`bf538\*(C'\fR,

\&\f(CW\*(C`bf539\*(C'\fR,

\&\f(CW\*(C`bf542\*(C'\fR,

\&\f(CW\*(C`bf542m\*(C'\fR,

\&\f(CW\*(C`bf544\*(C'\fR,

\&\f(CW\*(C`bf544m\*(C'\fR,

\&\f(CW\*(C`bf547\*(C'\fR,

\&\f(CW\*(C`bf547m\*(C'\fR,

\&\f(CW\*(C`bf548\*(C'\fR,

\&\f(CW\*(C`bf548m\*(C'\fR,

\&\f(CW\*(C`bf549\*(C'\fR,

\&\f(CW\*(C`bf549m\*(C'\fR,

\&\f(CW\*(C`bf561\*(C'\fR,

and

\&\f(CW\*(C`bf592\*(C'\fR.

.IP "\fB\-mfdpic\fR" 4

.IX Item "-mfdpic"

Assemble for the \s-1FDPIC\s0 \s-1ABI\s0.

.IP "\fB\-mno\-fdpic\fR" 4

.IX Item "-mno-fdpic"

.PD 0

.IP "\fB\-mnopic\fR" 4

.IX Item "-mnopic"

.PD

Disable \-mfdpic.

.PP

See the info pages for documentation of the CRIS-specific options.

.PP

The following options are available when as is configured for

a D10V processor.

.IP "\fB\-O\fR" 4

.IX Item "-O"

Optimize output by parallelizing instructions.

.PP

The following options are available when as is configured for a D30V

processor.

.IP "\fB\-O\fR" 4

.IX Item "-O"

Optimize output by parallelizing instructions.

.IP "\fB\-n\fR" 4

.IX Item "-n"

Warn when nops are generated.

.IP "\fB\-N\fR" 4

.IX Item "-N"

Warn when a nop after a 32\-bit multiply instruction is generated.

.PP

The following options are available when as is configured for

an Epiphany processor.

.IP "\fB\-mepiphany\fR" 4

.IX Item "-mepiphany"

Specifies that the both 32 and 16 bit instructions are allowed.  This is the

default behavior.

.IP "\fB\-mepiphany16\fR" 4

.IX Item "-mepiphany16"

Restricts the permitted instructions to just the 16 bit set.

.PP

The following options are available when as is configured for

an i386 processor.

.IP "\fB\-\-32 | \-\-x32 | \-\-64\fR" 4

.IX Item "--32 | --x32 | --64"

Select the word size, either 32 bits or 64 bits.  \fB\-\-32\fR

implies Intel i386 architecture, while \fB\-\-x32\fR and \fB\-\-64\fR

imply \s-1AMD\s0 x86\-64 architecture with 32\-bit or 64\-bit word-size

respectively.

.Sp

These options are only available with the \s-1ELF\s0 object file format, and

require that the necessary \s-1BFD\s0 support has been included (on a 32\-bit

platform you have to add \-\-enable\-64\-bit\-bfd to configure enable 64\-bit

usage and use x86\-64 as target platform).

.IP "\fB\-n\fR" 4

.IX Item "-n"

By default, x86 \s-1GAS\s0 replaces multiple nop instructions used for

alignment within code sections with multi-byte nop instructions such

as leal 0(%esi,1),%esi.  This switch disables the optimization.

.IP "\fB\-\-divide\fR" 4

.IX Item "--divide"

On SVR4\-derived platforms, the character \fB/\fR is treated as a comment

character, which means that it cannot be used in expressions.  The

\&\fB\-\-divide\fR option turns \fB/\fR into a normal character.  This does

not disable \fB/\fR at the beginning of a line starting a comment, or

affect using \fB#\fR for starting a comment.

.IP "\fB\-march=\fR\fI\s-1CPU\s0\fR\fB[+\fR\fI\s-1EXTENSION\s0\fR\fB...]\fR" 4

.IX Item "-march=CPU[+EXTENSION...]"

This option specifies the target processor.  The assembler will

issue an error message if an attempt is made to assemble an instruction

which will not execute on the target processor.  The following

processor names are recognized:

\&\f(CW\*(C`i8086\*(C'\fR,

\&\f(CW\*(C`i186\*(C'\fR,

\&\f(CW\*(C`i286\*(C'\fR,

\&\f(CW\*(C`i386\*(C'\fR,

\&\f(CW\*(C`i486\*(C'\fR,

\&\f(CW\*(C`i586\*(C'\fR,

\&\f(CW\*(C`i686\*(C'\fR,

\&\f(CW\*(C`pentium\*(C'\fR,

\&\f(CW\*(C`pentiumpro\*(C'\fR,

\&\f(CW\*(C`pentiumii\*(C'\fR,

\&\f(CW\*(C`pentiumiii\*(C'\fR,

\&\f(CW\*(C`pentium4\*(C'\fR,

\&\f(CW\*(C`prescott\*(C'\fR,

\&\f(CW\*(C`nocona\*(C'\fR,

\&\f(CW\*(C`core\*(C'\fR,

\&\f(CW\*(C`core2\*(C'\fR,

\&\f(CW\*(C`corei7\*(C'\fR,

\&\f(CW\*(C`l1om\*(C'\fR,

\&\f(CW\*(C`k1om\*(C'\fR,

\&\f(CW\*(C`k6\*(C'\fR,

\&\f(CW\*(C`k6_2\*(C'\fR,

\&\f(CW\*(C`athlon\*(C'\fR,

\&\f(CW\*(C`opteron\*(C'\fR,

\&\f(CW\*(C`k8\*(C'\fR,

\&\f(CW\*(C`amdfam10\*(C'\fR,

\&\f(CW\*(C`bdver1\*(C'\fR,

\&\f(CW\*(C`bdver2\*(C'\fR,

\&\f(CW\*(C`bdver3\*(C'\fR,

\&\f(CW\*(C`btver1\*(C'\fR,

\&\f(CW\*(C`btver2\*(C'\fR,

\&\f(CW\*(C`generic32\*(C'\fR and

\&\f(CW\*(C`generic64\*(C'\fR.

.Sp

In addition to the basic instruction set, the assembler can be told to

accept various extension mnemonics.  For example,

\&\f(CW\*(C`\-march=i686+sse4+vmx\*(C'\fR extends \fIi686\fR with \fIsse4\fR and

\&\fIvmx\fR.  The following extensions are currently supported:

\&\f(CW8087\fR,

\&\f(CW287\fR,

\&\f(CW387\fR,

\&\f(CW\*(C`no87\*(C'\fR,

\&\f(CW\*(C`mmx\*(C'\fR,

\&\f(CW\*(C`nommx\*(C'\fR,

\&\f(CW\*(C`sse\*(C'\fR,

\&\f(CW\*(C`sse2\*(C'\fR,

\&\f(CW\*(C`sse3\*(C'\fR,

\&\f(CW\*(C`ssse3\*(C'\fR,

\&\f(CW\*(C`sse4.1\*(C'\fR,

\&\f(CW\*(C`sse4.2\*(C'\fR,

\&\f(CW\*(C`sse4\*(C'\fR,

\&\f(CW\*(C`nosse\*(C'\fR,

\&\f(CW\*(C`avx\*(C'\fR,

\&\f(CW\*(C`avx2\*(C'\fR,

\&\f(CW\*(C`adx\*(C'\fR,

\&\f(CW\*(C`rdseed\*(C'\fR,

\&\f(CW\*(C`prfchw\*(C'\fR,

\&\f(CW\*(C`noavx\*(C'\fR,

\&\f(CW\*(C`vmx\*(C'\fR,

\&\f(CW\*(C`vmfunc\*(C'\fR,

\&\f(CW\*(C`smx\*(C'\fR,

\&\f(CW\*(C`xsave\*(C'\fR,

\&\f(CW\*(C`xsaveopt\*(C'\fR,

\&\f(CW\*(C`aes\*(C'\fR,