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ultra_embe |
//-----------------------------------------------------------------
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// AltOR32
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// Alternative Lightweight OpenRisc
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// V2.0
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// Ultra-Embedded.com
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// Copyright 2011 - 2013
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//
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// Email: admin@ultra-embedded.com
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//
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// License: LGPL
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//-----------------------------------------------------------------
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, write to the
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Boston, MA 02111-1307 USA
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//-----------------------------------------------------------------
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <assert.h>
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#include "or32_isa.h"
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#include "or32_inst_dump.h"
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//-----------------------------------------------------------------
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// or32_instruction_to_string: Decode instruction to string
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//-----------------------------------------------------------------
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int or32_instruction_to_string(TRegister opcode, char *output, int max_len)
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{
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TRegister v_ra = 0;
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TRegister v_rb = 0;
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TRegister v_rd = 0;
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TRegister v_inst = 0;
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TRegister v_op = 0;
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TRegister v_target = 0;
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TRegister v_pc = 0;
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TRegister v_pc_next = 0;
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TRegister v_imm = 0;
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TRegister v_imm_uint32 = 0;
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TRegister v_imm_int32 = 0;
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TRegister v_offset = 0;
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TRegister v_store_imm = 0;
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int v_branch = 0;
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int v_jmp = 0;
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TRegister v_alu_op = 0;
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TRegister v_shift_op = 0;
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TRegister v_sfxx_op = 0;
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// Decode opcode
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v_inst = (opcode >> OR32_OPCODE_SHIFT) & OR32_OPCODE_MASK;
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v_rd = (opcode >> OR32_REG_D_SHIFT) & OR32_REG_D_MASK;
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v_ra = (opcode >> OR32_REG_A_SHIFT) & OR32_REG_A_MASK;
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v_rb = (opcode >> OR32_REG_B_SHIFT) & OR32_REG_B_MASK;
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v_imm = (opcode >> OR32_IMM16_SHIFT) & OR32_IMM16_MASK;
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v_target = (opcode >> OR32_ADDR_SHIFT) & OR32_ADDR_MASK;
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v_sfxx_op = (opcode >> OR32_SFXXX_OP_SHIFT) & OR32_SFXXX_OP_MASK;
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v_alu_op = (opcode >> OR32_ALU_OP_L_SHIFT) & OR32_ALU_OP_L_MASK;
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v_alu_op |= (opcode >> OR32_ALU_OP_H_SHIFT) & OR32_ALU_OP_H_MASK;
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v_shift_op = (opcode >> OR32_SHIFT_OP_SHIFT) & OR32_SHIFT_OP_MASK;
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v_store_imm = (opcode >> OR32_STORE_IMM_L_SHIFT) & OR32_STORE_IMM_L_MASK;
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v_store_imm|= (opcode >> OR32_STORE_IMM_H_SHIFT) & OR32_STORE_IMM_H_MASK;
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// Sign extend store immediate
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v_store_imm = (unsigned int)(signed short)v_store_imm;
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// Sign extend target immediate
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if (v_target & (1 << 25))
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v_target |= ~OR32_ADDR_MASK;
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// Signed & unsigned imm -> 32-bits
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v_imm_int32 = (unsigned int)(signed short)v_imm;
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v_imm_uint32 = v_imm;
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output[0] = 0;
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// Execute instruction
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switch(v_inst)
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{
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case INST_OR32_ALU:
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switch (v_alu_op)
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{
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case INST_OR32_ADD: // l.add
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sprintf(output, "l.add r%d,r%d,r%d", v_rd, v_ra, v_rb);
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break;
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case INST_OR32_ADDC: // l.addc
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sprintf(output, "l.addc r%d,r%d,r%d", v_rd, v_ra, v_rb);
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break;
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case INST_OR32_AND: // l.and
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sprintf(output, "l.and r%d,r%d,r%d", v_rd, v_ra, v_rb);
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break;
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case INST_OR32_OR: // l.or
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sprintf(output, "l.or r%d,r%d,r%d", v_rd, v_ra, v_rb);
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break;
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case INST_OR32_SLL: // l.sll
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sprintf(output, "l.sll r%d,r%d,r%d", v_rd, v_ra, v_rb);
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break;
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case INST_OR32_SRA: // l.sra
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sprintf(output, "l.sra r%d,r%d,r%d", v_rd, v_ra, v_rb);
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break;
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case INST_OR32_SRL: // l.srl
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sprintf(output, "l.srl r%d,r%d,r%d", v_rd, v_ra, v_rb);
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break;
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case INST_OR32_SUB: // l.sub
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sprintf(output, "l.sub r%d,r%d,r%d", v_rd, v_ra, v_rb);
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break;
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case INST_OR32_XOR: // l.xor
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sprintf(output, "l.xor r%d,r%d,r%d", v_rd, v_ra, v_rb);
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break;
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case INST_OR32_MUL: // l.mul
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sprintf(output, "l.mul r%d,r%d,r%d", v_rd, v_ra, v_rb);
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break;
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case INST_OR32_MULU: // l.mulu
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sprintf(output, "l.mulu r%d,r%d,r%d", v_rd, v_ra, v_rb);
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break;
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}
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break;
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case INST_OR32_ADDI: // l.addi
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if ((int)v_imm_int32 < 0)
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sprintf(output, "l.addi r%d,r%d,%d", v_rd, v_ra, v_imm_int32);
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else
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sprintf(output, "l.addi r%d,r%d,0x%x", v_rd, v_ra, v_imm_int32);
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break;
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case INST_OR32_ANDI: // l.andi
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sprintf(output, "l.andi r%d,r%d,0x%x", v_rd, v_ra, v_imm_uint32);
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break;
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case INST_OR32_BF: // l.bf
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if ((int)v_target <= 0)
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sprintf(output, "l.bf %d", (int)v_target);
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else
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sprintf(output, "l.bf 0x%x", (int)v_target);
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break;
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case INST_OR32_BNF: // l.bnf
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if ((int)v_target <= 0)
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sprintf(output, "l.bnf %d", (int)v_target);
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else
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sprintf(output, "l.bnf 0x%x", (int)v_target);
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break;
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case INST_OR32_J: // l.j
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if ((int)v_target <= 0)
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sprintf(output, "l.j %d", (int)v_target);
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else
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sprintf(output, "l.j 0x%x", (int)v_target);
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break;
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case INST_OR32_JAL: // l.jal
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if ((int)v_target <= 0)
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sprintf(output, "l.jal %d", (int)v_target);
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else
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sprintf(output, "l.jal 0x%x", (int)v_target);
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break;
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case INST_OR32_JALR: // l.jalr
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sprintf(output, "l.jalr r%d", v_rb);
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break;
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| 181 |
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case INST_OR32_JR: // l.jr
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sprintf(output, "l.jr r%d", v_rb);
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break;
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case INST_OR32_LBS: // l.lbs
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if ((int)v_imm_int32 < 0)
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sprintf(output, "l.lbs r%d,%d(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
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else
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sprintf(output, "l.lbs r%d,0x%x(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
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break;
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case INST_OR32_LHS: // l.lhs
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if ((int)v_imm_int32 < 0)
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sprintf(output, "l.lhs r%d,%d(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
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else
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sprintf(output, "l.lhs r%d,0x%x(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
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break;
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| 199 |
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case INST_OR32_LWS: // l.lws
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if ((int)v_imm_int32 < 0)
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sprintf(output, "l.lws r%d,%d(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
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else
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sprintf(output, "l.lws r%d,0x%x(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
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break;
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| 206 |
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case INST_OR32_LBZ: // l.lbz
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if ((int)v_imm_int32 < 0)
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sprintf(output, "l.lbz r%d,%d(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
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else
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| 210 |
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sprintf(output, "l.lbz r%d,0x%x(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
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| 211 |
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break;
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| 212 |
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| 213 |
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case INST_OR32_LHZ: // l.lhz
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if ((int)v_imm_int32 < 0)
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sprintf(output, "l.lhz r%d,%d(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
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| 216 |
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else
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| 217 |
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sprintf(output, "l.lhz r%d,0x%x(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
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| 218 |
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break;
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| 219 |
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| 220 |
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case INST_OR32_LWZ: // l.lwz
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| 221 |
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if ((int)v_imm_int32 < 0)
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| 222 |
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sprintf(output, "l.lwz r%d,%d(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
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| 223 |
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else
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| 224 |
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sprintf(output, "l.lwz r%d,0x%x(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
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| 225 |
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break;
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| 226 |
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| 227 |
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case INST_OR32_MFSPR: // l.mfspr
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| 228 |
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break;
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| 229 |
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| 230 |
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case INST_OR32_MOVHI: // l.movhi
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| 231 |
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if (v_imm_uint32 == 0)
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| 232 |
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sprintf(output, "l.movhi r%d,%d", v_rd, v_imm_uint32);
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| 233 |
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else
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| 234 |
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sprintf(output, "l.movhi r%d,0x%x", v_rd, v_imm_uint32);
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| 235 |
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break;
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| 236 |
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| 237 |
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case INST_OR32_MTSPR: // l.mtspr
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| 238 |
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break;
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| 239 |
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| 240 |
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case INST_OR32_NOP: // l.nop
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| 241 |
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if (v_imm != 0)
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| 242 |
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sprintf(output, "l.nop 0x%x", v_imm);
|
| 243 |
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else
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| 244 |
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sprintf(output, "l.nop 0");
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| 245 |
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break;
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| 246 |
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| 247 |
|
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case INST_OR32_ORI: // l.ori
|
| 248 |
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if (v_imm_uint32 == 0)
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| 249 |
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sprintf(output, "l.ori r%d,r%d,%d", v_rd, v_ra, v_imm_uint32);
|
| 250 |
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else
|
| 251 |
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sprintf(output, "l.ori r%d,r%d,0x%x", v_rd, v_ra, v_imm_uint32);
|
| 252 |
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break;
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| 253 |
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| 254 |
|
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case INST_OR32_RFE: // l.rfe
|
| 255 |
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sprintf(output, "l.rfe");
|
| 256 |
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break;
|
| 257 |
|
|
|
| 258 |
|
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case INST_OR32_SHIFTI:
|
| 259 |
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switch (v_shift_op)
|
| 260 |
|
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{
|
| 261 |
|
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case INST_OR32_SLLI: // l.slli
|
| 262 |
|
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sprintf(output, "l.slli r%d,r%d,0x%x", v_rd, v_ra, (opcode & 0x3F));
|
| 263 |
|
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break;
|
| 264 |
|
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case INST_OR32_SRAI: // l.srai
|
| 265 |
|
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sprintf(output, "l.srai r%d,r%d,0x%x", v_rd, v_ra, (opcode & 0x3F));
|
| 266 |
|
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break;
|
| 267 |
|
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case INST_OR32_SRLI: // l.srli
|
| 268 |
|
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sprintf(output, "l.srli r%d,r%d,0x%x", v_rd, v_ra, (opcode & 0x3F));
|
| 269 |
|
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break;
|
| 270 |
|
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}
|
| 271 |
|
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break;
|
| 272 |
|
|
|
| 273 |
|
|
case INST_OR32_SB: // l.sb
|
| 274 |
|
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if ((int)v_store_imm < 0)
|
| 275 |
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sprintf(output, "l.sb %d(r%d),r%d", (int)v_store_imm, v_ra, v_rb);
|
| 276 |
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else
|
| 277 |
|
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sprintf(output, "l.sb 0x%x(r%d),r%d", (int)v_store_imm, v_ra, v_rb);
|
| 278 |
|
|
break;
|
| 279 |
|
|
|
| 280 |
|
|
case INST_OR32_SFXX:
|
| 281 |
|
|
case INST_OR32_SFXXI:
|
| 282 |
|
|
switch (v_sfxx_op)
|
| 283 |
|
|
{
|
| 284 |
|
|
case INST_OR32_SFEQ: // l.sfeq
|
| 285 |
|
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sprintf(output, "l.sfeq r%d,r%d", v_ra, v_rb);
|
| 286 |
|
|
break;
|
| 287 |
|
|
case INST_OR32_SFEQI: // l.sfeqi
|
| 288 |
|
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sprintf(output, "l.sfeqi r%d,0x%x", v_ra, (int)v_imm_int32);
|
| 289 |
|
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break;
|
| 290 |
|
|
case INST_OR32_SFGES: // l.sfges
|
| 291 |
|
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sprintf(output, "l.sfges r%d,r%d", v_ra, v_rb);
|
| 292 |
|
|
break;
|
| 293 |
|
|
case INST_OR32_SFGESI: // l.sfgesi
|
| 294 |
|
|
sprintf(output, "l.sfgesi r%d,0x%x", v_ra, (int)v_imm_int32);
|
| 295 |
|
|
break;
|
| 296 |
|
|
case INST_OR32_SFGEU: // l.sfgeu
|
| 297 |
|
|
sprintf(output, "l.sfgeu r%d,r%d", v_ra, v_rb);
|
| 298 |
|
|
break;
|
| 299 |
|
|
case INST_OR32_SFGEUI: // l.sfgeui
|
| 300 |
|
|
sprintf(output, "l.sfgeui r%d,0x%x", v_ra, v_imm_uint32);
|
| 301 |
|
|
break;
|
| 302 |
|
|
case INST_OR32_SFGTS: // l.sfgts
|
| 303 |
|
|
sprintf(output, "l.sfgts r%d,r%d", v_ra, v_rb);
|
| 304 |
|
|
break;
|
| 305 |
|
|
case INST_OR32_SFGTSI: // l.sfgtsi
|
| 306 |
|
|
sprintf(output, "l.sfgtsi r%d,0x%x", v_ra, (int)v_imm_int32);
|
| 307 |
|
|
break;
|
| 308 |
|
|
case INST_OR32_SFGTU: // l.sfgtu
|
| 309 |
|
|
sprintf(output, "l.sfgtu r%d,r%d", v_ra, v_rb);
|
| 310 |
|
|
break;
|
| 311 |
|
|
case INST_OR32_SFGTUI: // l.sfgtui
|
| 312 |
|
|
sprintf(output, "l.sfgtui r%d,0x%x", v_ra, v_imm_uint32);
|
| 313 |
|
|
break;
|
| 314 |
|
|
case INST_OR32_SFLES: // l.sfles
|
| 315 |
|
|
sprintf(output, "l.sfles r%d,r%d", v_ra, v_rb);
|
| 316 |
|
|
break;
|
| 317 |
|
|
case INST_OR32_SFLESI: // l.sflesi
|
| 318 |
|
|
sprintf(output, "l.sflesi r%d,0x%x", v_ra, (int)v_imm_int32);
|
| 319 |
|
|
break;
|
| 320 |
|
|
case INST_OR32_SFLEU: // l.sfleu
|
| 321 |
|
|
sprintf(output, "l.sfleu r%d,r%d", v_ra, v_rb);
|
| 322 |
|
|
break;
|
| 323 |
|
|
case INST_OR32_SFLEUI: // l.sfleui
|
| 324 |
|
|
sprintf(output, "l.sfleui r%d,0x%x", v_ra, v_imm_uint32);
|
| 325 |
|
|
break;
|
| 326 |
|
|
case INST_OR32_SFLTS: // l.sflts
|
| 327 |
|
|
sprintf(output, "l.sflts r%d,r%d", v_ra, v_rb);
|
| 328 |
|
|
break;
|
| 329 |
|
|
case INST_OR32_SFLTSI: // l.sfltsi
|
| 330 |
|
|
sprintf(output, "l.sfltsi r%d,0x%x", v_ra, (int)v_imm_int32);
|
| 331 |
|
|
break;
|
| 332 |
|
|
case INST_OR32_SFLTU: // l.sfltu
|
| 333 |
|
|
sprintf(output, "l.sfltu r%d,r%d", v_ra, v_rb);
|
| 334 |
|
|
break;
|
| 335 |
|
|
case INST_OR32_SFLTUI: // l.sfltui
|
| 336 |
|
|
sprintf(output, "l.sfltui r%d,0x%x", v_ra, v_imm_uint32);
|
| 337 |
|
|
break;
|
| 338 |
|
|
case INST_OR32_SFNE: // l.sfne
|
| 339 |
|
|
sprintf(output, "l.sfne r%d,r%d", v_ra, v_rb);
|
| 340 |
|
|
break;
|
| 341 |
|
|
case INST_OR32_SFNEI: // l.sfnei
|
| 342 |
|
|
sprintf(output, "l.sfnei r%d,0x%x", v_ra, v_imm_uint32);
|
| 343 |
|
|
break;
|
| 344 |
|
|
}
|
| 345 |
|
|
break;
|
| 346 |
|
|
|
| 347 |
|
|
case INST_OR32_SH: // l.sh
|
| 348 |
|
|
if ((int)v_store_imm < 0)
|
| 349 |
|
|
sprintf(output, "l.sh %d(r%d),r%d", (int)v_store_imm, v_ra, v_rb);
|
| 350 |
|
|
else
|
| 351 |
|
|
sprintf(output, "l.sh 0x%x(r%d),r%d", (int)v_store_imm, v_ra, v_rb);
|
| 352 |
|
|
break;
|
| 353 |
|
|
|
| 354 |
|
|
case INST_OR32_SW: // l.sw
|
| 355 |
|
|
if ((int)v_store_imm < 0)
|
| 356 |
|
|
sprintf(output, "l.sw %d(r%d),r%d", (int)v_store_imm, v_ra, v_rb);
|
| 357 |
|
|
else
|
| 358 |
|
|
sprintf(output, "l.sw 0x%x(r%d),r%d", (int)v_store_imm, v_ra, v_rb);
|
| 359 |
|
|
break;
|
| 360 |
|
|
|
| 361 |
|
|
case INST_OR32_MISC:
|
| 362 |
|
|
switch (opcode >> 24)
|
| 363 |
|
|
{
|
| 364 |
|
|
case INST_OR32_SYS: // l.sys
|
| 365 |
|
|
sprintf(output, "l.sys");
|
| 366 |
|
|
break;
|
| 367 |
|
|
|
| 368 |
|
|
case INST_OR32_TRAP: // l.trap
|
| 369 |
|
|
sprintf(output, "l.trap");
|
| 370 |
|
|
break;
|
| 371 |
|
|
}
|
| 372 |
|
|
break;
|
| 373 |
|
|
|
| 374 |
|
|
case INST_OR32_XORI: // l.xori
|
| 375 |
|
|
if ((int)v_imm_int32 < 0)
|
| 376 |
|
|
sprintf(output, "l.xori r%d,r%d,%d", v_rd, v_ra, v_imm_int32);
|
| 377 |
|
|
else
|
| 378 |
|
|
sprintf(output, "l.xori r%d,r%d,0x%x", v_rd, v_ra, v_imm_int32);
|
| 379 |
|
|
break;
|
| 380 |
|
|
}
|
| 381 |
|
|
|
| 382 |
|
|
return (output[0] != 0);
|
| 383 |
|
|
}
|
| 384 |
|
|
//-----------------------------------------------------------------
|
| 385 |
|
|
// or32_instruction_to_string: Decode instruction to string
|
| 386 |
|
|
//-----------------------------------------------------------------
|
| 387 |
|
|
void or32_instruction_dump(TRegister pc, TRegister opcode, TRegister gpr[REGISTERS], TRegister rd, TRegister result, TRegister sr)
|
| 388 |
|
|
{
|
| 389 |
|
|
char output[1024];
|
| 390 |
|
|
|
| 391 |
|
|
// Decode opcode in-order to perform register reads
|
| 392 |
|
|
TRegister ra = (opcode >> OR32_REG_A_SHIFT) & OR32_REG_A_MASK;
|
| 393 |
|
|
TRegister rb = (opcode >> OR32_REG_B_SHIFT) & OR32_REG_B_MASK;
|
| 394 |
|
|
TRegister v_inst = (opcode >> OR32_OPCODE_SHIFT) & OR32_OPCODE_MASK;
|
| 395 |
|
|
|
| 396 |
|
|
TRegister v_store_imm = (opcode >> OR32_STORE_IMM_L_SHIFT) & OR32_STORE_IMM_L_MASK;
|
| 397 |
|
|
v_store_imm|= (opcode >> OR32_STORE_IMM_H_SHIFT) & OR32_STORE_IMM_H_MASK;
|
| 398 |
|
|
v_store_imm = (unsigned int)(signed short)v_store_imm;
|
| 399 |
|
|
|
| 400 |
|
|
// Decode instruction in or1ksim trace format
|
| 401 |
|
|
or32_instruction_to_string(opcode, output, sizeof(output)-1);
|
| 402 |
|
|
|
| 403 |
|
|
if (rd != 0 && v_inst != INST_OR32_JAL && v_inst != INST_OR32_JALR)
|
| 404 |
|
|
printf("S %08x: %08x %-23s r%d = %08x flag: %d\n", pc, opcode, output, rd, result, sr & OR32_SR_F_BIT ? 1: 0);
|
| 405 |
|
|
else if (v_inst == INST_OR32_SB || v_inst == INST_OR32_SH || v_inst == INST_OR32_SW)
|
| 406 |
|
|
{
|
| 407 |
|
|
if (v_inst == INST_OR32_SB)
|
| 408 |
|
|
printf("S %08x: %08x %-23s [%08x] = %02x flag: %d\n", pc, opcode, output, gpr[ra] + (int)v_store_imm, gpr[rb], sr & OR32_SR_F_BIT ? 1: 0);
|
| 409 |
|
|
else if (v_inst == INST_OR32_SH)
|
| 410 |
|
|
printf("S %08x: %08x %-23s [%08x] = %04x flag: %d\n", pc, opcode, output, gpr[ra] + (int)v_store_imm, gpr[rb], sr & OR32_SR_F_BIT ? 1: 0);
|
| 411 |
|
|
else
|
| 412 |
|
|
printf("S %08x: %08x %-23s [%08x] = %08x flag: %d\n", pc, opcode, output, gpr[ra] + (int)v_store_imm, gpr[rb], sr & OR32_SR_F_BIT ? 1: 0);
|
| 413 |
|
|
}
|
| 414 |
|
|
else
|
| 415 |
|
|
printf("S %08x: %08x %-45s flag: %d\n", pc, opcode, output, sr & OR32_SR_F_BIT ? 1: 0);
|
| 416 |
|
|
}
|
