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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32.v] - Blame information for rev 29

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1 27 ultra_embe
//-----------------------------------------------------------------
2
//                           AltOR32 
3
//                Alternative Lightweight OpenRisc 
4
//                            V2.0
5
//                     Ultra-Embedded.com
6
//                   Copyright 2011 - 2013
7
//
8
//               Email: admin@ultra-embedded.com
9
//
10
//                       License: LGPL
11
//-----------------------------------------------------------------
12
//
13
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
14
//
15
// This source file may be used and distributed without         
16
// restriction provided that this copyright statement is not    
17
// removed from the file and that any derivative work contains  
18
// the original copyright notice and the associated disclaimer. 
19
//
20
// This source file is free software; you can redistribute it   
21
// and/or modify it under the terms of the GNU Lesser General   
22
// Public License as published by the Free Software Foundation; 
23
// either version 2.1 of the License, or (at your option) any   
24
// later version.
25
//
26
// This source is distributed in the hope that it will be       
27
// useful, but WITHOUT ANY WARRANTY; without even the implied   
28
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
29
// PURPOSE.  See the GNU Lesser General Public License for more 
30
// details.
31
//
32
// You should have received a copy of the GNU Lesser General    
33
// Public License along with this source; if not, write to the 
34
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
35
// Boston, MA  02111-1307  USA
36
//-----------------------------------------------------------------
37
 
38
//-----------------------------------------------------------------
39
// Includes
40
//-----------------------------------------------------------------
41
`include "altor32_defs.v"
42
 
43
//-----------------------------------------------------------------
44
// Module - AltOR32 CPU
45
//-----------------------------------------------------------------
46
module cpu
47
(
48
    // General
49
    input               clk_i /*verilator public*/,
50
    input               rst_i /*verilator public*/,
51
 
52
    input               intr_i /*verilator public*/,
53
    input               nmi_i /*verilator public*/,
54
    output              fault_o /*verilator public*/,
55
    output              break_o /*verilator public*/,
56
 
57
    // Instruction memory
58
    output [31:0]       imem_addr_o /*verilator public*/,
59
    output              imem_rd_o /*verilator public*/,
60
    output              imem_burst_o /*verilator public*/,
61
    input [31:0]        imem_data_in_i /*verilator public*/,
62
    input               imem_accept_i /*verilator public*/,
63
    input               imem_ack_i /*verilator public*/,
64
 
65
    // Data memory
66
    output [31:0]       dmem_addr_o /*verilator public*/,
67
    output [31:0]       dmem_data_out_o /*verilator public*/,
68
    input [31:0]        dmem_data_in_i /*verilator public*/,
69
    output [3:0]        dmem_wr_o /*verilator public*/,
70
    output              dmem_rd_o /*verilator public*/,
71
    output              dmem_burst_o /*verilator public*/,
72
    input               dmem_accept_i /*verilator public*/,
73
    input               dmem_ack_i /*verilator public*/
74
);
75
 
76
//-----------------------------------------------------------------
77
// Params
78
//-----------------------------------------------------------------
79
parameter           BOOT_VECTOR         = 32'h00000000;
80
parameter           ISR_VECTOR          = 32'h00000000;
81
parameter           REGISTER_FILE_TYPE  = "SIMULATION";
82
parameter           ENABLE_ICACHE       = "ENABLED";
83
parameter           ENABLE_DCACHE       = "DISABLED";
84
parameter           SUPPORT_32REGS      = "ENABLED";
85
 
86
//-----------------------------------------------------------------
87
// Registers / Wires
88
//-----------------------------------------------------------------
89
 
90
// Register number (rA)
91
wire [4:0]  w_ra;
92
 
93
// Register number (rB)
94
wire [4:0]  w_rb;
95
 
96
// Destination register number (pre execute stage)
97
wire [4:0]  w_rd;
98
 
99
// Destination register number (post execute stage)
100
wire [4:0]  w_e_rd;
101
 
102
// Register value (rA)
103
wire [31:0] w_reg_ra;
104
 
105
// Register value (rB)
106
wire [31:0] w_reg_rb;
107
 
108
// Current opcode
109
wire [31:0] w_d_opcode;
110
wire [31:0] w_d_pc;
111
wire        w_d_valid;
112
 
113
wire [31:0] w_e_opcode;
114
 
115
// Register writeback value
116
wire [4:0]  w_wb_rd;
117
wire [31:0] w_wb_reg_rd;
118
 
119
// Register writeback enable
120
wire        w_wb_write_rd;
121
 
122
// Result from execute
123
wire [31:0] w_e_result;
124
wire        w_e_mult;
125
wire [31:0] w_e_mult_result;
126
 
127
// Branch request
128
wire        w_e_branch;
129
wire [31:0] w_e_branch_pc;
130
wire        w_e_stall;
131
 
132
wire        icache_rd;
133
wire [31:0] icache_pc;
134
wire [31:0] icache_inst;
135
wire        icache_miss;
136
wire        icache_valid;
137
wire        icache_busy;
138
wire        icache_invalidate;
139
 
140
wire [31:0] dcache_addr;
141
wire [31:0] dcache_data_o;
142
wire [31:0] dcache_data_i;
143
wire [3:0]  dcache_wr;
144
wire        dcache_rd;
145
wire        dcache_ack;
146
wire        dcache_accept;
147
wire        dcache_flush;
148
 
149
//-----------------------------------------------------------------
150
// Instantiation
151
//-----------------------------------------------------------------
152
 
153
// Instruction Cache
154
generate
155
if (ENABLE_ICACHE == "ENABLED")
156
begin : ICACHE
157
    // Instruction cache
158
    altor32_icache
159
    #(
160
        .BOOT_VECTOR(BOOT_VECTOR)
161
    )
162
    u_icache
163
    (
164
        .clk_i(clk_i),
165
        .rst_i(rst_i),
166
 
167
        // Processor interface
168
        .rd_i(icache_rd),
169
        .pc_i(icache_pc),
170
        .instruction_o(icache_inst),
171
        .valid_o(icache_valid),
172
        .invalidate_i(icache_invalidate),
173
 
174
        // Status
175
        .miss_o(icache_miss),
176
        .busy_o(icache_busy),
177
 
178
        // Instruction memory
179
        .mem_addr_o(imem_addr_o),
180
        .mem_data_i(imem_data_in_i),
181
        .mem_burst_o(imem_burst_o),
182
        .mem_rd_o(imem_rd_o),
183
        .mem_accept_i(imem_accept_i),
184
        .mem_ack_i(imem_ack_i)
185
    );
186
end
187
else
188
begin
189
    // No instruction cache
190
    altor32_noicache
191
    u_icache
192
    (
193
        .clk_i(clk_i),
194
        .rst_i(rst_i),
195
 
196
        // Processor interface
197
        .rd_i(icache_rd),
198
        .pc_i(icache_pc),
199
        .instruction_o(icache_inst),
200
        .valid_o(icache_valid),
201
 
202
        // Instruction memory
203
        .mem_addr_o(imem_addr_o),
204
        .mem_data_i(imem_data_in_i),
205
        .mem_burst_o(imem_burst_o),
206
        .mem_rd_o(imem_rd_o),
207
        .mem_accept_i(imem_accept_i),
208
        .mem_ack_i(imem_ack_i)
209
    );
210
end
211
endgenerate
212
 
213
// Instruction Fetch
214
altor32_fetch
215
#(
216
    .BOOT_VECTOR(BOOT_VECTOR)
217
)
218
u_fetch
219
(
220
    // General
221
    .clk_i(clk_i),
222
    .rst_i(rst_i),
223
 
224
    // Instruction memory
225
    .pc_o(icache_pc),
226
    .data_i(icache_inst),
227
    .fetch_o(icache_rd),
228
    .data_valid_i(icache_valid),
229
 
230
    // Fetched opcode
231
    .opcode_o(w_d_opcode),
232
    .opcode_pc_o(w_d_pc),
233
    .opcode_valid_o(w_d_valid),
234
 
235
    // Branch target
236
    .branch_i(w_e_branch),
237
    .branch_pc_i(w_e_branch_pc),
238
    .stall_i(w_e_stall),
239
 
240
    // Decoded register details
241
    .ra_o(w_ra),
242
    .rb_o(w_rb),
243
    .rd_o(w_rd)
244
);
245
 
246
// Register file
247
generate
248
if (REGISTER_FILE_TYPE == "XILINX")
249
begin
250
    altor32_regfile_xil
251
    #(
252
        .SUPPORT_32REGS(SUPPORT_32REGS)
253
    )
254
    reg_bank
255
    (
256
        // Clocking
257
        .clk_i(clk_i),
258
        .rst_i(rst_i),
259
        .wr_i(w_wb_write_rd),
260
 
261
        // Tri-port
262
        .rs_i(w_ra),
263
        .rt_i(w_rb),
264
        .rd_i(w_wb_rd),
265
        .reg_rs_o(w_reg_ra),
266
        .reg_rt_o(w_reg_rb),
267
        .reg_rd_i(w_wb_reg_rd)
268
    );
269
end
270
else if (REGISTER_FILE_TYPE == "ALTERA")
271
begin
272
    altor32_regfile_alt
273
    #(
274
        .SUPPORT_32REGS(SUPPORT_32REGS)
275
    )
276
    reg_bank
277
    (
278
        // Clocking
279
        .clk_i(clk_i),
280
        .rst_i(rst_i),
281
        .wr_i(w_wb_write_rd),
282
 
283
        // Tri-port
284
        .rs_i(w_ra),
285
        .rt_i(w_rb),
286
        .rd_i(w_wb_rd),
287
        .reg_rs_o(w_reg_ra),
288
        .reg_rt_o(w_reg_rb),
289
        .reg_rd_i(w_wb_reg_rd)
290
    );
291
end
292
else
293
begin
294
    altor32_regfile_sim
295
    #(
296
        .SUPPORT_32REGS(SUPPORT_32REGS)
297
    )
298
    reg_bank
299
    (
300
        // Clocking
301
        .clk_i(clk_i),
302
        .rst_i(rst_i),
303
        .wr_i(w_wb_write_rd),
304
 
305
        // Tri-port
306
        .rs_i(w_ra),
307
        .rt_i(w_rb),
308
        .rd_i(w_wb_rd),
309
        .reg_rs_o(w_reg_ra),
310
        .reg_rt_o(w_reg_rb),
311
        .reg_rd_i(w_wb_reg_rd)
312
    );
313
end
314
endgenerate
315
 
316
generate
317
if (ENABLE_DCACHE == "ENABLED")
318
begin
319
    // Data cache
320
    altor32_dcache
321
    u_dcache
322
    (
323
        .clk_i(clk_i),
324
        .rst_i(rst_i),
325
 
326
        .flush_i(dcache_flush),
327
 
328
        // Processor interface
329
        .address_i({dcache_addr[31:2], 2'b00}),
330
        .data_o(dcache_data_i),
331
        .data_i(dcache_data_o),
332
        .wr_i(dcache_wr),
333
        .rd_i(dcache_rd),
334
        .accept_o(dcache_accept),
335
        .ack_o(dcache_ack),
336
 
337
        // Memory interface (slave)
338
        .mem_addr_o(dmem_addr_o),
339
        .mem_data_i(dmem_data_in_i),
340
        .mem_data_o(dmem_data_out_o),
341
        .mem_burst_o(dmem_burst_o),
342
        .mem_rd_o(dmem_rd_o),
343
        .mem_wr_o(dmem_wr_o),
344
        .mem_accept_i(dmem_accept_i),
345
        .mem_ack_i(dmem_ack_i)
346
    );
347
end
348
else
349
begin
350
 
351
    // No data cache
352
    assign dmem_addr_o      = {dcache_addr[31:2], 2'b00};
353
    assign dmem_data_out_o  = dcache_data_o;
354
    assign dcache_data_i    = dmem_data_in_i;
355
    assign dmem_rd_o        = dcache_rd;
356
    assign dmem_wr_o        = dcache_wr;
357
    assign dmem_burst_o     = 1'b0;
358
    assign dcache_ack       = dmem_ack_i;
359
    assign dcache_accept    = dmem_accept_i;
360
end
361
endgenerate
362
 
363
// Execution unit
364
altor32_exec
365
#(
366
    .BOOT_VECTOR(BOOT_VECTOR),
367
    .ISR_VECTOR(ISR_VECTOR)
368
)
369
u_exec
370
(
371
    // General
372
    .clk_i(clk_i),
373
    .rst_i(rst_i),
374
 
375
    .intr_i(intr_i),
376
    .nmi_i(nmi_i),
377
 
378
    // Status
379
    .fault_o(fault_o),
380
    .break_o(break_o),
381
 
382
    // Cache control
383
    .icache_flush_o(icache_invalidate),
384
    .dcache_flush_o(dcache_flush),
385
 
386
    // Branch target
387
    .branch_o(w_e_branch),
388
    .branch_pc_o(w_e_branch_pc),
389
    .stall_o(w_e_stall),
390
 
391
    // Opcode & arguments
392
    .opcode_i(w_d_opcode),
393
    .opcode_pc_i(w_d_pc),
394
    .opcode_valid_i(w_d_valid),
395
 
396
    .reg_ra_i(w_ra),
397
    .reg_ra_value_i(w_reg_ra),
398
 
399
    .reg_rb_i(w_rb),
400
    .reg_rb_value_i(w_reg_rb),
401
 
402
    .reg_rd_i(w_rd),
403
 
404
    // Output
405
    .opcode_o(w_e_opcode),
406
    .reg_rd_o(w_e_rd),
407
    .reg_rd_value_o(w_e_result),
408
    .mult_o(w_e_mult),
409
    .mult_res_o(w_e_mult_result),
410
 
411
    // Register write back bypass
412
    .wb_rd_i(w_wb_rd),
413
    .wb_rd_value_i(w_wb_reg_rd),
414
 
415
    // Memory Interface
416
    .dmem_addr_o(dcache_addr),
417
    .dmem_data_out_o(dcache_data_o),
418
    .dmem_data_in_i(dcache_data_i),
419
    .dmem_wr_o(dcache_wr),
420
    .dmem_rd_o(dcache_rd),
421
    .dmem_accept_i(dcache_accept),
422
    .dmem_ack_i(dcache_ack)
423
);
424
 
425
// Register file writeback
426
altor32_writeback
427
u_wb
428
(
429
    // General
430
    .clk_i(clk_i),
431
    .rst_i(rst_i),
432
 
433
    // Opcode
434
    .opcode_i(w_e_opcode),
435
 
436
    // Register target
437
    .rd_i(w_e_rd),
438
 
439
    // ALU result
440
    .alu_result_i(w_e_result),
441
 
442
    // Memory load result
443
    .mem_result_i(dcache_data_i),
444
    .mem_offset_i(dcache_addr[1:0]),
445
    .mem_ready_i(dcache_ack),
446
 
447
    // Multiplier result
448
    .mult_i(w_e_mult),
449
    .mult_result_i(w_e_mult_result),
450
 
451
    // Outputs
452
    .write_enable_o(w_wb_write_rd),
453
    .write_addr_o(w_wb_rd),
454
    .write_data_o(w_wb_reg_rd)
455
);
456
 
457
//-------------------------------------------------------------------
458
// Hooks for debug
459
//-------------------------------------------------------------------
460
`ifdef verilator
461
   function [31:0] get_pc;
462
      // verilator public
463
      get_pc = w_d_pc;
464
   endfunction
465
   function get_fault;
466
      // verilator public
467
      get_fault = fault_o;
468
   endfunction
469
   function get_break;
470
      // verilator public
471
      get_break = break_o;
472
   endfunction
473
`endif
474
 
475
endmodule

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