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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_dcache.v] - Blame information for rev 44

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1 27 ultra_embe
//-----------------------------------------------------------------
2
//                           AltOR32 
3
//                Alternative Lightweight OpenRisc 
4 36 ultra_embe
//                            V2.1
5 27 ultra_embe
//                     Ultra-Embedded.com
6 36 ultra_embe
//                   Copyright 2011 - 2014
7 27 ultra_embe
//
8
//               Email: admin@ultra-embedded.com
9
//
10
//                       License: LGPL
11
//-----------------------------------------------------------------
12
//
13 37 ultra_embe
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
14 27 ultra_embe
//
15
// This source file may be used and distributed without         
16
// restriction provided that this copyright statement is not    
17
// removed from the file and that any derivative work contains  
18
// the original copyright notice and the associated disclaimer. 
19
//
20
// This source file is free software; you can redistribute it   
21
// and/or modify it under the terms of the GNU Lesser General   
22
// Public License as published by the Free Software Foundation; 
23
// either version 2.1 of the License, or (at your option) any   
24
// later version.
25
//
26
// This source is distributed in the hope that it will be       
27
// useful, but WITHOUT ANY WARRANTY; without even the implied   
28
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
29
// PURPOSE.  See the GNU Lesser General Public License for more 
30
// details.
31
//
32
// You should have received a copy of the GNU Lesser General    
33
// Public License along with this source; if not, write to the 
34
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
35
// Boston, MA  02111-1307  USA
36
//-----------------------------------------------------------------
37
 
38
//-----------------------------------------------------------------
39
// Module - Data Cache (write back)
40
//-----------------------------------------------------------------
41
module altor32_dcache
42
(
43
    input           clk_i /*verilator public*/,
44
    input           rst_i /*verilator public*/,
45
 
46
    input           flush_i /*verilator public*/,
47
 
48
    // Input (CPU)
49
    input [31:0]    address_i /*verilator public*/,
50
    output [31:0]   data_o /*verilator public*/,
51
    input [31:0]    data_i /*verilator public*/,
52 32 ultra_embe
    input           we_i /*verilator public*/,
53
    input           stb_i /*verilator public*/,
54
    input [3:0]     sel_i /*verilator public*/,
55
    output          stall_o /*verilator public*/,
56 27 ultra_embe
    output          ack_o /*verilator public*/,
57
 
58
    // Output (Memory)
59
    output [31:0]   mem_addr_o /*verilator public*/,
60
    input [31:0]    mem_data_i /*verilator public*/,
61
    output [31:0]   mem_data_o /*verilator public*/,
62 32 ultra_embe
    output [2:0]    mem_cti_o /*verilator public*/,
63
    output          mem_cyc_o /*verilator public*/,
64
    output          mem_stb_o /*verilator public*/,
65
    output          mem_we_o /*verilator public*/,
66
    output [3:0]    mem_sel_o /*verilator public*/,
67
    input           mem_stall_i/*verilator public*/,
68 27 ultra_embe
    input           mem_ack_i/*verilator public*/
69
);
70
 
71
//-----------------------------------------------------------------
72
// Params
73
//-----------------------------------------------------------------
74
parameter CACHE_LINE_SIZE_WIDTH     = 5; /* 5-bits -> 32 entries */
75
parameter CACHE_LINE_SIZE_BYTES     = 2 ** CACHE_LINE_SIZE_WIDTH; /* 32 bytes / 8 words per line */
76
parameter CACHE_LINE_ADDR_WIDTH     = 8; /* 256 lines */
77
parameter CACHE_LINE_WORDS_IDX_MAX  = CACHE_LINE_SIZE_WIDTH - 2; /* 3-bit = 8 words */
78
parameter CACHE_TAG_ENTRIES         = 2 ** CACHE_LINE_ADDR_WIDTH ; /* 256 tag entries */
79
parameter CACHE_DSIZE               = CACHE_LINE_ADDR_WIDTH * CACHE_LINE_SIZE_BYTES; /* 8KB data */
80
parameter CACHE_DWIDTH              = CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 2; /* 11-bits */
81
 
82
parameter CACHE_TAG_WIDTH           = 16; /* 16-bit tag entry size */
83
parameter CACHE_TAG_LINE_ADDR_WIDTH = CACHE_TAG_WIDTH - 2; /* 14 bits of data (tag entry size minus valid/dirty bit) */
84
 
85
parameter CACHE_TAG_ADDR_LOW        = CACHE_LINE_SIZE_WIDTH + CACHE_LINE_ADDR_WIDTH;
86
parameter CACHE_TAG_ADDR_HIGH       = CACHE_TAG_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH + CACHE_LINE_ADDR_WIDTH - 1;
87
 
88
// Tag fields
89
parameter CACHE_TAG_DIRTY_BIT       = 14;
90
parameter CACHE_TAG_VALID_BIT       = 15;
91
parameter ADDR_NO_CACHE_BIT         = 25;
92
parameter ADDR_CACHE_BYPASS_BIT     = 31;
93
 
94 36 ultra_embe
parameter FLUSH_INITIAL             = 0;
95
 
96 27 ultra_embe
//  31          16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
97
// |--------------|  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
98
//  +--------------------+   +-------------------+   +-----------+      
99
//    Tag entry                     Line address         Address 
100
//       (15-bits)                    (8-bits)           within line 
101
//                                                       (5-bits)
102
 
103
//-----------------------------------------------------------------
104
// Registers / Wires
105
//-----------------------------------------------------------------
106
wire [CACHE_LINE_ADDR_WIDTH-1:0] tag_entry;
107
wire [CACHE_TAG_WIDTH-1:0]       tag_data_out;
108
reg  [CACHE_TAG_WIDTH-1:0]       tag_data_in;
109
reg                              tag_wr;
110
 
111
wire [CACHE_DWIDTH-1:0]          cache_address;
112
wire [31:0]                      cache_data_r;
113
reg [31:0]                       cache_data_w;
114
reg [3:0]                        cache_wr;
115
 
116
wire [31:2]                      cache_update_addr;
117
wire [31:0]                      cache_update_data_w;
118
wire [31:0]                      cache_update_data_r;
119
wire                             cache_update_wr;
120
 
121
reg                              ack;
122
 
123
reg                              fill;
124
reg                              evict;
125
wire                             done;
126
 
127
wire [31:0]                      data_r;
128 32 ultra_embe
reg                              rd_single;
129
reg [3:0]                        wr_single;
130 27 ultra_embe
 
131
reg                              req_rd;
132
reg [3:0]                        req_wr;
133
reg                              req_ack;
134
reg [31:0]                       req_address;
135 32 ultra_embe
reg [31:0]                       req_data;
136 27 ultra_embe
 
137
reg                              req_flush;
138 36 ultra_embe
reg                              req_init;
139 27 ultra_embe
reg                              flush_single;
140
 
141
wire [31:0]                      line_address;
142
 
143
wire [31:0]                      muxed_address = (state == STATE_IDLE) ? address_i : req_address;
144
 
145
// Current state
146
parameter STATE_IDLE        = 0;
147
parameter STATE_SINGLE      = 1;
148
parameter STATE_CHECK       = 2;
149
parameter STATE_FETCH       = 3;
150
parameter STATE_WAIT        = 4;
151
parameter STATE_WAIT2       = 5;
152
parameter STATE_WRITE       = 6;
153
parameter STATE_SINGLE_READY= 7;
154
parameter STATE_EVICTING    = 8;
155
parameter STATE_UPDATE      = 9;
156
parameter STATE_FLUSH1      = 10;
157
parameter STATE_FLUSH2      = 11;
158
parameter STATE_FLUSH3      = 12;
159
parameter STATE_FLUSH4      = 13;
160
reg [3:0] state;
161
 
162
assign tag_entry               = muxed_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH];
163
assign cache_address           = {tag_entry, muxed_address[CACHE_LINE_SIZE_WIDTH-1:2]};
164
 
165
assign data_o                  = (state == STATE_SINGLE_READY) ? data_r : cache_data_r;
166 36 ultra_embe
assign stall_o                 = (state != STATE_IDLE) | req_flush | flush_i;
167 27 ultra_embe
 
168
wire valid                     = tag_data_out[CACHE_TAG_VALID_BIT];
169
wire dirty                     = tag_data_out[CACHE_TAG_DIRTY_BIT];
170
 
171
// Access is cacheable?
172
wire cacheable                 = ~muxed_address[ADDR_NO_CACHE_BIT] & ~muxed_address[ADDR_CACHE_BYPASS_BIT];
173
 
174 32 ultra_embe
// Address matches cache tag
175
wire addr_hit                  = (req_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] == tag_data_out[13:0]);
176
 
177 27 ultra_embe
// Cache hit?
178 32 ultra_embe
wire hit                       = cacheable & valid & addr_hit & (state == STATE_CHECK);
179 27 ultra_embe
 
180
assign ack_o                   = ack | hit;
181
 
182 36 ultra_embe
assign line_address[31:CACHE_TAG_ADDR_HIGH+1] = {(31-CACHE_TAG_ADDR_HIGH){1'b0}};
183 27 ultra_embe
assign line_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] = tag_entry;
184
assign line_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] = tag_data_out[13:0];
185
assign line_address[CACHE_LINE_SIZE_WIDTH-1:0] = {CACHE_LINE_SIZE_WIDTH{1'b0}};
186
 
187 36 ultra_embe
// Only allow cache write when same line present in the write state
188
wire cache_wr_enable           = (state == STATE_WRITE) ? valid & addr_hit : 1'b1;
189 32 ultra_embe
 
190 27 ultra_embe
//-----------------------------------------------------------------
191 32 ultra_embe
// Next State Logic
192 27 ultra_embe
//-----------------------------------------------------------------
193 32 ultra_embe
reg [3:0] next_state_r;
194
always @ *
195
begin
196
    next_state_r = state;
197
 
198
    case (state)
199
    //-----------------------------------------
200
    // IDLE
201
    //-----------------------------------------
202
    STATE_IDLE :
203
    begin
204
        // Cache flush request
205
        if (flush_i | req_flush)
206
            next_state_r    = STATE_FLUSH2;
207
        // Read (uncacheable)
208
        else if (stb_i & ~we_i & ~cacheable)
209
            next_state_r    = STATE_SINGLE;
210
        // Read (cacheable)
211
        else if (stb_i & ~we_i)
212
            next_state_r    = STATE_CHECK;
213
        // Write (uncacheable)
214
        else if (stb_i & we_i & ~cacheable)
215
            next_state_r    = STATE_SINGLE;
216
        // Write (cacheable)
217
        else if (stb_i & we_i)
218
            next_state_r    = STATE_WRITE;
219
    end
220
    //-----------------------------------------
221 36 ultra_embe
    // WRITE
222 32 ultra_embe
    //-----------------------------------------
223
    STATE_WRITE :
224
    begin
225 36 ultra_embe
        // Cache hit (line already dirty)
226
        if (valid & addr_hit & dirty)
227
            next_state_r    = STATE_IDLE;
228
        // Cache hit, make line dirty
229
        else if (valid & addr_hit & ~dirty)
230
            next_state_r    = STATE_WAIT2;
231 32 ultra_embe
        // Cache dirty
232
        else if (valid & dirty)
233
            next_state_r    = STATE_EVICTING;
234
        // Cache miss
235
        else
236
            next_state_r    = STATE_UPDATE;
237
    end
238
    //-----------------------------------------
239
    // EVICTING - Evicting cache line
240
    //-----------------------------------------
241
    STATE_EVICTING:
242
    begin
243
        // Data ready from memory?
244
        if (done)
245
        begin
246
            // Evict for read?
247
            if (req_rd)
248
                next_state_r   = STATE_FETCH;
249
            // Evict for write
250
            else
251
                next_state_r   = STATE_UPDATE;
252
        end
253
    end
254
    //-----------------------------------------
255
    // UPDATE - Update fetched cache line
256
    //-----------------------------------------
257
    STATE_UPDATE:
258
    begin
259
        // Data ready from memory?
260
        if (done)
261
            next_state_r    = STATE_WAIT2;
262
    end
263
    //-----------------------------------------
264
    // CHECK - check cache for hit or miss
265
    //-----------------------------------------
266
    STATE_CHECK :
267
    begin
268
        // Cache hit
269
        if (valid & addr_hit)
270
            next_state_r    = STATE_IDLE;
271
        // Cache dirty
272
        else if (valid & dirty)
273
            next_state_r    = STATE_EVICTING;
274
        // Cache miss
275
        else
276
            next_state_r    = STATE_FETCH;
277
    end
278
    //-----------------------------------------
279
    // FETCH_SINGLE - Single access to memory
280
    //-----------------------------------------
281
    STATE_SINGLE:
282
    begin
283
        // Data ready from memory?
284
        if (done)
285
        begin
286
            // Single WRITE?
287
            if (~req_rd)
288
                next_state_r    = STATE_SINGLE_READY;
289
            // Dirty? Write back
290
            else if (valid & dirty & addr_hit)
291
                next_state_r    = STATE_FLUSH4;
292
            // Valid line, invalidate
293
            else if (valid & addr_hit)
294
                next_state_r    = STATE_SINGLE_READY;
295
            else
296
                next_state_r    = STATE_SINGLE_READY;
297
        end
298
    end
299
    //-----------------------------------------
300
    // FETCH - Fetch row from memory
301
    //-----------------------------------------
302
    STATE_FETCH :
303
    begin
304
        // Cache line filled?
305
        if (done)
306
           next_state_r = STATE_WAIT;
307
    end
308
    //-----------------------------------------
309
    // WAIT - Wait cycle
310
    //-----------------------------------------
311
    STATE_WAIT :
312
    begin
313
        // Allow extra wait state to handle write & read collision               
314
        next_state_r    = STATE_WAIT2;
315
    end
316
    //-----------------------------------------
317
    // WAIT2 - Wait cycle
318
    //-----------------------------------------
319
    STATE_WAIT2 :
320
    begin
321
        next_state_r    = STATE_IDLE;
322
    end
323
    //-----------------------------------------
324
    // SINGLE_READY - Uncached access ready
325
    //-----------------------------------------
326
    STATE_SINGLE_READY :
327
    begin
328
        // Allow extra wait state to handle write & read collision               
329
        next_state_r    = STATE_IDLE;
330
    end
331
    //-----------------------------------------
332
    // FLUSHx - Flush dirty lines & invalidate
333
    //-----------------------------------------
334
    STATE_FLUSH1 :
335
    begin
336
        if (req_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] == {CACHE_LINE_ADDR_WIDTH{1'b1}})
337
            next_state_r    = STATE_WAIT;
338
        else
339
            next_state_r    = STATE_FLUSH2;
340
    end
341
    //-----------------------------------------
342
    // FLUSH2 - Wait state
343
    //-----------------------------------------
344
    STATE_FLUSH2 :
345
    begin
346
        // Allow a cycle to read line state
347
        next_state_r    = STATE_FLUSH3;
348
    end
349
    //-----------------------------------------
350
    // FLUSH3 - Check if line dirty & flush
351
    //-----------------------------------------            
352
    STATE_FLUSH3 :
353
    begin
354
        // Dirty line? Evict line first
355 36 ultra_embe
        if (dirty && ~req_init)
356 32 ultra_embe
            next_state_r    = STATE_FLUSH4;
357
        // Not dirty? Just invalidate
358
        else
359
        begin
360
            if (flush_single)
361
                next_state_r    = STATE_WAIT;
362
            else
363
                next_state_r    = STATE_FLUSH1;
364
        end
365
    end
366
    //-----------------------------------------
367
    // FLUSH4 - Wait for line flush to complete
368
    //-----------------------------------------            
369
    STATE_FLUSH4 :
370
    begin
371
        // Cache line filled?
372
        if (done)
373
        begin
374
            if (flush_single)
375
                next_state_r    = STATE_SINGLE_READY;
376
            else
377
                next_state_r    = STATE_FLUSH1;
378
        end
379
    end
380
 
381
    default:
382
        ;
383
   endcase
384
end
385
 
386
// Update state
387 27 ultra_embe
always @ (posedge rst_i or posedge clk_i )
388
begin
389
   if (rst_i == 1'b1)
390 32 ultra_embe
        state   <= STATE_IDLE;
391
   else
392
        state   <= next_state_r;
393
end
394
 
395
//-----------------------------------------------------------------
396
// Tag Write
397
//-----------------------------------------------------------------
398
always @ (posedge rst_i or posedge clk_i )
399
begin
400
   if (rst_i == 1'b1)
401 27 ultra_embe
   begin
402 32 ultra_embe
        tag_data_in     <= 16'b0;
403
        tag_wr          <= 1'b0;
404
   end
405
   else
406
   begin
407
        tag_wr          <= 1'b0;
408
 
409
        case (state)
410
        //-----------------------------------------
411 36 ultra_embe
        // WRITE
412 32 ultra_embe
        //-----------------------------------------
413
        STATE_WRITE :
414
        begin
415
            // Cache hit
416
            if (valid & addr_hit)
417
            begin
418
                // Mark line as dirty
419 36 ultra_embe
                if (~dirty)
420
                begin
421
                    tag_data_in  <= tag_data_out;
422
                    tag_data_in[CACHE_TAG_DIRTY_BIT] <= 1'b1;
423
                    tag_wr       <= 1'b1;
424
                end
425 32 ultra_embe
            end
426
            // Cache miss / cache line doesn't require write back
427
            else if (~valid | ~dirty)
428
            begin
429
                // Update tag memory with this line's details   
430
                tag_data_in <= {1'b1, 1'b1, req_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW]};
431
                tag_wr      <= 1'b1;
432
            end
433
        end
434
        //-----------------------------------------
435
        // EVICTING - Evicting cache line
436
        //-----------------------------------------
437
        STATE_EVICTING:
438
        begin
439
            // Data ready from memory?
440
            if (done)
441
            begin
442
                // Update tag memory with this new line's details   
443
                tag_data_in <= {1'b1, 1'b0, req_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW]};
444
                tag_wr      <= 1'b1;
445
            end
446
        end
447
        //-----------------------------------------
448
        // UPDATE - Update fetched cache line
449
        //-----------------------------------------
450
        STATE_UPDATE:
451
        begin
452
            // Data ready from memory?
453
            if (done)
454
            begin
455
                // Mark line as dirty
456
                tag_data_in  <= tag_data_out;
457
                tag_data_in[CACHE_TAG_DIRTY_BIT] <= 1'b1;
458
                tag_wr       <= 1'b1;
459
            end
460
        end
461
        //-----------------------------------------
462
        // CHECK - check cache for hit or miss
463
        //-----------------------------------------
464
        STATE_CHECK :
465
        begin
466
            // Cache hit
467
            if (valid & addr_hit)
468
            begin
469
 
470
            end
471
            // Cache miss / cache line doesn't require write back
472
            else if (~valid | ~dirty)
473
            begin
474
                // Update tag memory with this line's details   
475
                tag_data_in <= {1'b1, 1'b0, req_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW]};
476
                tag_wr      <= 1'b1;
477
            end
478
        end
479
        //-----------------------------------------
480
        // FETCH_SINGLE - Single access to memory
481
        //-----------------------------------------
482
        STATE_SINGLE:
483
        begin
484
            // Data ready from memory?
485
            if (done)
486
            begin
487
                // Single WRITE?
488
                if (~req_rd)
489
                begin
490
                    // Invalidate cached version
491
                    if (valid & addr_hit)
492
                    begin
493
                        tag_data_in  <= tag_data_out;
494
                        tag_data_in[CACHE_TAG_VALID_BIT] <= 1'b0;
495
                        tag_wr       <= 1'b1;
496
                    end
497
                end
498
                // Valid line (not dirty), just invalidate
499
                else if (valid & ~dirty & addr_hit)
500
                begin
501
                    tag_data_in  <= tag_data_out;
502
                    tag_data_in[CACHE_TAG_VALID_BIT] <= 1'b0;
503
                    tag_wr       <= 1'b1;
504
                end
505
            end
506
        end
507
 
508
        //-----------------------------------------
509
        // FLUSH3 - Check if line dirty & flush
510
        //-----------------------------------------            
511
        STATE_FLUSH3 :
512
        begin
513
            // Not dirty? Just invalidate
514 36 ultra_embe
            if (~dirty | req_init)
515 32 ultra_embe
            begin
516 36 ultra_embe
                tag_data_in  <= 16'b0;
517 32 ultra_embe
                tag_data_in[CACHE_TAG_VALID_BIT] <= 1'b0;
518
                tag_wr       <= 1'b1;
519
            end
520
        end
521
        //-----------------------------------------
522
        // FLUSH4 - Wait for line flush to complete
523
        //-----------------------------------------            
524
        STATE_FLUSH4 :
525
        begin
526
            // Cache line filled?
527
            if (done)
528
            begin
529
                // Invalidate line
530 36 ultra_embe
                tag_data_in  <= 16'b0;
531 32 ultra_embe
                tag_data_in[CACHE_TAG_VALID_BIT] <= 1'b0;
532
                tag_data_in[CACHE_TAG_DIRTY_BIT] <= 1'b0;
533
                tag_wr       <= 1'b1;
534
            end
535
        end
536
        default:
537
            ;
538
       endcase
539
   end
540
end
541
 
542
//-----------------------------------------------------------------
543
// Register requests
544
//-----------------------------------------------------------------
545
always @ (posedge rst_i or posedge clk_i )
546
begin
547
   if (rst_i == 1'b1)
548
   begin
549 27 ultra_embe
        req_address     <= 32'h00000000;
550 32 ultra_embe
        req_data        <= 32'h00000000;
551 27 ultra_embe
        req_ack         <= 1'b0;
552
        req_wr          <= 4'h0;
553
        req_rd          <= 1'b0;
554 36 ultra_embe
        req_flush       <= 1'b1;
555
        req_init        <= FLUSH_INITIAL;
556 32 ultra_embe
   end
557
   else
558
   begin
559
        if (flush_i)
560
            req_flush       <= 1'b1;
561
 
562
        case (state)
563
        //-----------------------------------------
564
        // IDLE
565
        //-----------------------------------------
566
        STATE_IDLE :
567
        begin
568
            // Cache flush request
569
            if (flush_i | req_flush)
570
            begin
571
                // Set to first line address
572
                req_address <= 32'h00000000;
573
                req_flush   <= 1'b0;
574
                req_ack     <= 1'b0;
575
            end
576
            // Read (uncacheable)
577
            else if (stb_i & ~we_i & ~cacheable)
578
            begin
579
                // Start read single from memory
580
                req_address <= address_i;
581
                req_address[ADDR_CACHE_BYPASS_BIT] <= 1'b0;
582
                req_rd      <= 1'b1;
583
                req_wr      <= 4'b0;
584
                req_ack     <= 1'b1;
585
            end
586
            // Read (cacheable)
587
            else if (stb_i & ~we_i)
588
            begin
589
                req_address <= address_i;
590
                req_rd      <= 1'b1;
591
                req_wr      <= 4'b0;
592
                req_ack     <= 1'b1;
593
            end
594
            // Write (uncacheable)
595
            else if (stb_i & we_i & ~cacheable)
596
            begin
597
                // Perform write single
598
                req_address <= address_i;
599
                req_address[ADDR_CACHE_BYPASS_BIT] <= 1'b0;
600
                req_data    <= data_i;
601
                req_wr      <= sel_i;
602
                req_rd      <= 1'b0;
603
                req_ack     <= 1'b1;
604
            end
605
            // Write (cacheable)
606
            else if (stb_i & we_i)
607
            begin
608
                req_address <= address_i;
609
                req_data    <= data_i;
610
                req_wr      <= sel_i;
611
                req_rd      <= 1'b0;
612
                req_ack     <= 1'b0;
613
            end
614
        end
615
        //-----------------------------------------
616
        // FLUSHx - Flush dirty lines & invalidate
617
        //-----------------------------------------
618
        STATE_FLUSH1 :
619
        begin
620
            if (req_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] == {CACHE_LINE_ADDR_WIDTH{1'b1}})
621
            begin
622
                req_ack <= 1'b0;
623 36 ultra_embe
                req_init <= 1'b0;
624 32 ultra_embe
            end
625
            else
626
            begin
627
                // Increment flush line address
628
                req_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] <=
629
                req_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] + 1;
630
            end
631
        end
632
        default:
633
            ;
634
       endcase
635
   end
636
end
637
 
638
//-----------------------------------------------------------------
639
// Cache Data Write
640
//-----------------------------------------------------------------
641
always @ (posedge rst_i or posedge clk_i )
642
begin
643
   if (rst_i == 1'b1)
644
   begin
645
        cache_data_w    <= 32'h00000000;
646
        cache_wr        <= 4'b0;
647
   end
648
   else
649
   begin
650
        cache_wr        <= 4'b0;
651
 
652
        case (state)
653
        //-----------------------------------------
654 36 ultra_embe
        // IDLE
655 32 ultra_embe
        //-----------------------------------------
656 36 ultra_embe
        STATE_IDLE:
657
        begin
658
            // Write (cacheable)
659
            if (stb_i & we_i & cacheable & ~(flush_i | req_flush))
660 32 ultra_embe
            begin
661 36 ultra_embe
                // Early write which is gated on line match
662
                cache_data_w <= data_i;
663
                cache_wr     <= sel_i;
664
            end
665 32 ultra_embe
        end
666
        //-----------------------------------------
667
        // UPDATE - Update fetched cache line
668
        //-----------------------------------------
669
        STATE_UPDATE:
670
        begin
671
            // Data ready from memory?
672
            if (done)
673
            begin
674
                // Update line already in cache
675
                cache_data_w <= req_data;
676
                cache_wr     <= req_wr;
677
            end
678
        end
679
        default:
680
            ;
681
       endcase
682
   end
683
end
684
 
685
//-----------------------------------------------------------------
686
// Control
687
//-----------------------------------------------------------------
688
always @ (posedge rst_i or posedge clk_i )
689
begin
690
   if (rst_i == 1'b1)
691
   begin
692
        wr_single       <= 4'h0;
693
        rd_single       <= 1'b0;
694 27 ultra_embe
        flush_single    <= 1'b0;
695
        fill            <= 1'b0;
696
        evict           <= 1'b0;
697
   end
698
   else
699
   begin
700
        fill            <= 1'b0;
701
        evict           <= 1'b0;
702 32 ultra_embe
        wr_single       <= 4'b0;
703
        rd_single       <= 1'b0;
704 27 ultra_embe
 
705
        case (state)
706
 
707
            //-----------------------------------------
708
            // IDLE
709
            //-----------------------------------------
710
            STATE_IDLE :
711 32 ultra_embe
            begin
712
                // Cache flush request
713
                if (flush_i | req_flush)
714
                begin
715
                    // Set to first line address
716
                    flush_single<= 1'b0;
717
                end
718 27 ultra_embe
                // Read (uncacheable)
719 32 ultra_embe
                else if (stb_i & ~we_i & ~cacheable)
720 27 ultra_embe
                begin
721
                    // Start read single from memory
722 32 ultra_embe
                    rd_single     <= 1'b1;
723
                end
724 27 ultra_embe
                // Write (uncacheable)
725 32 ultra_embe
                else if (stb_i & we_i & ~cacheable)
726 27 ultra_embe
                begin
727
                    // Perform write single
728 32 ultra_embe
                    wr_single     <= sel_i;
729
                end
730 27 ultra_embe
            end
731
            //-----------------------------------------
732 36 ultra_embe
            // WRITE
733 27 ultra_embe
            //-----------------------------------------
734
            STATE_WRITE :
735
            begin
736
                // Cache hit
737 32 ultra_embe
                if (valid & addr_hit)
738 27 ultra_embe
                begin
739
 
740
                end
741
                // Cache dirty
742
                else if (valid & dirty)
743
                begin
744
                    // Evict cache line
745
                    evict       <= 1'b1;
746
                end
747
                // Cache miss
748
                else
749
                begin
750
                    // Fill cache line
751
                    fill        <= 1'b1;
752
                end
753
            end
754
            //-----------------------------------------
755
            // EVICTING - Evicting cache line
756
            //-----------------------------------------
757
            STATE_EVICTING:
758
            begin
759
                // Data ready from memory?
760
                if (done)
761
                begin
762
                    // Fill cache line
763
                    fill        <= 1'b1;
764
                end
765 32 ultra_embe
            end
766 27 ultra_embe
            //-----------------------------------------
767
            // CHECK - check cache for hit or miss
768
            //-----------------------------------------
769
            STATE_CHECK :
770
            begin
771
                // Cache hit
772 32 ultra_embe
                if (valid & addr_hit)
773 27 ultra_embe
                begin
774 32 ultra_embe
 
775 27 ultra_embe
                end
776
                // Cache dirty
777
                else if (valid & dirty)
778
                begin
779
                    // Evict cache line
780
                    evict       <= 1'b1;
781
                end
782
                // Cache miss
783
                else
784
                begin
785
                    // Fill cache line
786
                    fill        <= 1'b1;
787
                end
788
            end
789
            //-----------------------------------------
790
            // FETCH_SINGLE - Single access to memory
791
            //-----------------------------------------
792
            STATE_SINGLE:
793
            begin
794
                // Data ready from memory?
795
                if (done)
796
                begin
797
                    // Single WRITE?
798
                    if (~req_rd)
799
                    begin
800 32 ultra_embe
 
801 27 ultra_embe
                    end
802
                    // Dirty? Write back
803 32 ultra_embe
                    else if (valid & dirty & addr_hit)
804 27 ultra_embe
                    begin
805
                        // Evict cache line
806
                        evict       <= 1'b1;
807
                        flush_single<= 1'b1;
808
                    end
809
                end
810 32 ultra_embe
            end
811 27 ultra_embe
            //-----------------------------------------
812
            // FLUSH3 - Check if line dirty & flush
813
            //-----------------------------------------            
814
            STATE_FLUSH3 :
815
            begin
816
                // Dirty line? Evict line first
817
                if (dirty)
818
                begin
819
                    // Evict cache line
820
                    evict       <= 1'b1;
821
                end
822 32 ultra_embe
            end
823
            default:
824
                ;
825
           endcase
826
   end
827
end
828 27 ultra_embe
 
829 32 ultra_embe
//-----------------------------------------------------------------
830
// ACK
831
//-----------------------------------------------------------------
832
always @ (posedge rst_i or posedge clk_i )
833
begin
834
   if (rst_i == 1'b1)
835
        ack     <= 1'b0;
836
   else
837
   begin
838
        ack     <= 1'b0;
839
 
840
        case (state)
841
 
842
        //-----------------------------------------
843
        // IDLE
844
        //-----------------------------------------
845
        STATE_IDLE :
846
        begin
847
            // Write (cacheable), early acknowledge
848
            if (~(flush_i | req_flush) & stb_i & we_i & cacheable)
849
                ack <= 1'b1;
850
        end
851
        //-----------------------------------------
852
        // FETCH_SINGLE - Single access to memory
853
        //-----------------------------------------
854
        STATE_SINGLE:
855
        begin
856
            // Data ready from memory?
857
            if (done)
858 27 ultra_embe
            begin
859 32 ultra_embe
                // Single WRITE?
860
                if (~req_rd)
861
                    ack         <= req_ack;
862
                // Dirty? Write back
863
                else if (valid & dirty & addr_hit)
864 27 ultra_embe
                begin
865
 
866
                end
867 32 ultra_embe
                // Valid line, invalidate
868
                else if (valid & addr_hit)
869
                    ack         <= req_ack;
870
                else
871
                    ack         <= req_ack;
872
            end
873
        end
874
        //-----------------------------------------
875
        // WAIT2 - Wait cycle
876
        //-----------------------------------------
877
        STATE_WAIT2 :
878
        begin
879
            ack     <= req_ack;
880
        end
881
        //-----------------------------------------
882
        // FLUSH4 - Wait for line flush to complete
883
        //-----------------------------------------            
884
        STATE_FLUSH4 :
885
        begin
886
            if (done & flush_single)
887
                ack     <= req_ack;
888
        end
889
        default:
890
            ;
891
       endcase
892 27 ultra_embe
   end
893
end
894
 
895
//-----------------------------------------------------------------
896
// Instantiation
897
//-----------------------------------------------------------------
898
 
899
altor32_dcache_mem_if
900
#(
901
    .CACHE_LINE_SIZE_WIDTH(CACHE_LINE_SIZE_WIDTH),
902
    .CACHE_LINE_WORDS_IDX_MAX(CACHE_LINE_WORDS_IDX_MAX)
903
)
904
u_mem_if
905
(
906
    .clk_i(clk_i),
907
    .rst_i(rst_i),
908
 
909
    // Cache interface
910
    .address_i(muxed_address),
911 32 ultra_embe
    .data_i(req_data),
912 27 ultra_embe
    .data_o(data_r),
913
    .fill_i(fill),
914
    .evict_i(evict),
915
    .evict_addr_i(line_address),
916 32 ultra_embe
    .rd_single_i(rd_single),
917
    .wr_single_i(wr_single),
918 27 ultra_embe
    .done_o(done),
919
 
920
    // Cache memory (fill/evict)
921
    .cache_addr_o(cache_update_addr),
922
    .cache_data_o(cache_update_data_w),
923
    .cache_data_i(cache_update_data_r),
924
    .cache_wr_o(cache_update_wr),
925
 
926
    // Memory interface (slave)
927
    .mem_addr_o(mem_addr_o),
928
    .mem_data_i(mem_data_i),
929
    .mem_data_o(mem_data_o),
930 32 ultra_embe
    .mem_cti_o(mem_cti_o),
931
    .mem_cyc_o(mem_cyc_o),
932
    .mem_stb_o(mem_stb_o),
933
    .mem_we_o(mem_we_o),
934
    .mem_sel_o(mem_sel_o),
935
    .mem_stall_i(mem_stall_i),
936 27 ultra_embe
    .mem_ack_i(mem_ack_i)
937
);
938
 
939
// Tag memory    
940
altor32_ram_sp
941
#(
942
    .WIDTH(CACHE_TAG_WIDTH),
943
    .SIZE(CACHE_LINE_ADDR_WIDTH)
944
)
945
u1_tag_mem
946
(
947
    .clk_i(clk_i),
948
    .dat_o(tag_data_out),
949
    .dat_i(tag_data_in),
950
    .adr_i(tag_entry),
951
    .wr_i(tag_wr)
952
);
953
 
954
// Data memory   
955
altor32_ram_dp
956
#(
957
    .WIDTH(8),
958
    .SIZE(CACHE_DWIDTH)
959
)
960
u2_data_mem0
961
(
962
    .aclk_i(clk_i),
963
    .aadr_i(cache_address),
964
    .adat_o(cache_data_r[7:0]),
965
    .adat_i(cache_data_w[7:0]),
966 36 ultra_embe
    .awr_i(cache_wr[0] & cache_wr_enable),
967 27 ultra_embe
 
968
    .bclk_i(clk_i),
969
    .badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),
970
    .bdat_o(cache_update_data_r[7:0]),
971
    .bdat_i(cache_update_data_w[7:0]),
972
    .bwr_i(cache_update_wr)
973
);
974
 
975
altor32_ram_dp
976
#(
977
    .WIDTH(8),
978
    .SIZE(CACHE_DWIDTH)
979
)
980
u2_data_mem1
981
(
982
    .aclk_i(clk_i),
983
    .aadr_i(cache_address),
984
    .adat_o(cache_data_r[15:8]),
985
    .adat_i(cache_data_w[15:8]),
986 36 ultra_embe
    .awr_i(cache_wr[1] & cache_wr_enable),
987 27 ultra_embe
 
988
    .bclk_i(clk_i),
989
    .badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),
990
    .bdat_o(cache_update_data_r[15:8]),
991
    .bdat_i(cache_update_data_w[15:8]),
992
    .bwr_i(cache_update_wr)
993
);
994
 
995
altor32_ram_dp
996
#(
997
    .WIDTH(8),
998
    .SIZE(CACHE_DWIDTH)
999
)
1000
u2_data_mem2
1001
(
1002
    .aclk_i(clk_i),
1003
    .aadr_i(cache_address),
1004
    .adat_o(cache_data_r[23:16]),
1005
    .adat_i(cache_data_w[23:16]),
1006 36 ultra_embe
    .awr_i(cache_wr[2] & cache_wr_enable),
1007 27 ultra_embe
 
1008
    .bclk_i(clk_i),
1009
    .badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),
1010
    .bdat_o(cache_update_data_r[23:16]),
1011
    .bdat_i(cache_update_data_w[23:16]),
1012
    .bwr_i(cache_update_wr)
1013
);
1014
 
1015
altor32_ram_dp
1016
#(
1017
    .WIDTH(8),
1018
    .SIZE(CACHE_DWIDTH)
1019
)
1020
u2_data_mem3
1021
(
1022
    .aclk_i(clk_i),
1023
    .aadr_i(cache_address),
1024
    .adat_o(cache_data_r[31:24]),
1025
    .adat_i(cache_data_w[31:24]),
1026 36 ultra_embe
    .awr_i(cache_wr[3] & cache_wr_enable),
1027 27 ultra_embe
 
1028
    .bclk_i(clk_i),
1029
    .badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),
1030
    .bdat_o(cache_update_data_r[31:24]),
1031
    .bdat_i(cache_update_data_w[31:24]),
1032
    .bwr_i(cache_update_wr)
1033
);
1034
 
1035
endmodule

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