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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_dcache_mem_if.v] - Blame information for rev 29

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1 27 ultra_embe
//-----------------------------------------------------------------
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//                           AltOR32 
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//                Alternative Lightweight OpenRisc 
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//                            V2.0
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//                     Ultra-Embedded.com
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//                   Copyright 2011 - 2013
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//
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//               Email: admin@ultra-embedded.com
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//
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//                       License: LGPL
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//-----------------------------------------------------------------
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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// This source file may be used and distributed without         
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// restriction provided that this copyright statement is not    
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// removed from the file and that any derivative work contains  
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// the original copyright notice and the associated disclaimer. 
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//
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// This source file is free software; you can redistribute it   
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// and/or modify it under the terms of the GNU Lesser General   
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// Public License as published by the Free Software Foundation; 
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// either version 2.1 of the License, or (at your option) any   
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// later version.
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//
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// This source is distributed in the hope that it will be       
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// useful, but WITHOUT ANY WARRANTY; without even the implied   
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
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// PURPOSE.  See the GNU Lesser General Public License for more 
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// details.
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//
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// You should have received a copy of the GNU Lesser General    
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// Public License along with this source; if not, write to the 
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
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// Boston, MA  02111-1307  USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Module - Data Cache Memory Interface
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//-----------------------------------------------------------------
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module altor32_dcache_mem_if
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(
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    input           clk_i /*verilator public*/,
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    input           rst_i /*verilator public*/,
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    // Cache interface
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    input [31:0]    address_i /*verilator public*/,
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    input [31:0]    data_i /*verilator public*/,
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    output [31:0]   data_o /*verilator public*/,
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    input           fill_i /*verilator public*/,
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    input           evict_i /*verilator public*/,
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    input  [31:0]   evict_addr_i /*verilator public*/,
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    input           rd_single_i /*verilator public*/,
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    input [3:0]     wr_single_i /*verilator public*/,
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    output          done_o /*verilator public*/,
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    // Cache memory (fill/evict)
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    output [31:2]   cache_addr_o /*verilator public*/,
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    output [31:0]   cache_data_o /*verilator public*/,
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    input  [31:0]   cache_data_i /*verilator public*/,
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    output          cache_wr_o /*verilator public*/,
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    // Memory interface (slave)
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    output [31:0]   mem_addr_o /*verilator public*/,
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    input  [31:0]   mem_data_i /*verilator public*/,
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    output [31:0]   mem_data_o /*verilator public*/,
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    output          mem_burst_o /*verilator public*/,
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    output          mem_rd_o /*verilator public*/,
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    output [3:0]    mem_wr_o /*verilator public*/,
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    input           mem_accept_i/*verilator public*/,
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    input           mem_ack_i/*verilator public*/
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);
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//-----------------------------------------------------------------
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// Params
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//-----------------------------------------------------------------
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parameter CACHE_LINE_SIZE_WIDTH     = 5;                         /* 5-bits -> 32 entries */
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parameter CACHE_LINE_WORDS_IDX_MAX  = CACHE_LINE_SIZE_WIDTH - 2; /* 3-bit -> 8 words */
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//-----------------------------------------------------------------
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// Registers / Wires
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//-----------------------------------------------------------------
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reg [31:2]                      cache_addr_o;
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reg [31:0]                      cache_data_o;
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reg                             cache_wr_o;
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reg [31:CACHE_LINE_SIZE_WIDTH]  line_address;
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reg [CACHE_LINE_SIZE_WIDTH-3:0] line_word;
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reg [31:0]                      data_o;
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reg                             done_o;
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reg [31:0]                      mem_addr_o;
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reg [31:0]                      mem_data_o;
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reg                             mem_rd_o;
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reg [3:0]                       mem_wr_o;
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reg                             mem_burst_o;
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// Current state
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parameter STATE_IDLE        = 0;
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parameter STATE_FETCH       = 1;
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parameter STATE_READ_WAIT   = 2;
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parameter STATE_WRITE       = 3;
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parameter STATE_WRITE_WAIT  = 4;
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parameter STATE_READ_SINGLE = 5;
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parameter STATE_WRITE_SINGLE= 6;
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reg [3:0] state;
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//-----------------------------------------------------------------
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// Control logic
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//-----------------------------------------------------------------
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reg [CACHE_LINE_SIZE_WIDTH-3:0] v_line_word;
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always @ (posedge rst_i or posedge clk_i )
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begin
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   if (rst_i == 1'b1)
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   begin
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        line_address    <= {32-CACHE_LINE_SIZE_WIDTH{1'b0}};
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        line_word       <= {CACHE_LINE_SIZE_WIDTH-2{1'b0}};
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        mem_addr_o      <= 32'h00000000;
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        mem_data_o      <= 32'h00000000;
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        mem_wr_o        <= 4'h0;
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        mem_rd_o        <= 1'b0;
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        mem_burst_o     <= 1'b0;
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        cache_addr_o    <= 30'h00000000;
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        cache_data_o    <= 32'h00000000;
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        cache_wr_o      <= 1'b0;
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        done_o          <= 1'b0;
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        data_o          <= 32'h00000000;
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        state           <= STATE_IDLE;
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   end
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   else
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   begin
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        if (mem_accept_i)
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        begin
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            mem_rd_o        <= 1'b0;
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            mem_wr_o        <= 4'h0;
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        end
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        done_o          <= 1'b0;
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        cache_wr_o      <= 1'b0;
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        case (state)
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            //-----------------------------------------
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            // IDLE
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            //-----------------------------------------
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            STATE_IDLE :
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            begin
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                // Perform cache evict (write)     
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                if (evict_i)
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                begin
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                    line_address  <= evict_addr_i[31:CACHE_LINE_SIZE_WIDTH];
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                    line_word     <= {CACHE_LINE_SIZE_WIDTH-2{1'b0}};
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                    // Read data from cache
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                    cache_addr_o  <= {evict_addr_i[31:CACHE_LINE_SIZE_WIDTH], {CACHE_LINE_SIZE_WIDTH-2{1'b0}}};
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                    state         <= STATE_READ_WAIT;
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                end
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                // Perform cache fill (read)
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                else if (fill_i)
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                begin
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                    line_address <= address_i[31:CACHE_LINE_SIZE_WIDTH];
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                    line_word    <= {CACHE_LINE_SIZE_WIDTH-2{1'b0}};
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                    // Start fetch from memory
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                    mem_addr_o   <= {address_i[31:CACHE_LINE_SIZE_WIDTH], {CACHE_LINE_SIZE_WIDTH{1'b0}}};
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                    mem_rd_o     <= 1'b1;
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                    mem_burst_o  <= 1'b1;
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                    state        <= STATE_FETCH;
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                end
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                // Read single
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                else if (rd_single_i)
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                begin
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                    // Start fetch from memory
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                    mem_addr_o   <= address_i;
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                    mem_data_o   <= 32'b0;
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                    mem_rd_o     <= 1'b1;
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                    mem_burst_o  <= 1'b0;
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                    state        <= STATE_READ_SINGLE;
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                end
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                // Write single
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                else if (|wr_single_i)
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                begin
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                    // Start fetch from memory
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                    mem_addr_o   <= address_i;
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                    mem_data_o   <= data_i;
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                    mem_wr_o     <= wr_single_i;
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                    mem_burst_o  <= 1'b0;
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                    state        <= STATE_WRITE_SINGLE;
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                end
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            end
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            //-----------------------------------------
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            // FETCH - Fetch line from memory
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            //-----------------------------------------
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            STATE_FETCH :
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            begin
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                // Data ready from memory?
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                if (mem_ack_i && mem_rd_o == 1'b0)
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                begin
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                    // Write data into cache
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                    cache_addr_o    <= {line_address, line_word};
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                    cache_data_o    <= mem_data_i;
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                    cache_wr_o      <= 1'b1;
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                    // Line fetch complete?
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                    if (line_word == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
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                    begin
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                        done_o      <= 1'b1;
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                        state       <= STATE_IDLE;
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                    end
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                    // Fetch next word for line
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                    else
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                    begin
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                        v_line_word = line_word + 1'b1;
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                        line_word   <= v_line_word;
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                        mem_addr_o <= {line_address, v_line_word, 2'b00};
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                        mem_rd_o   <= 1'b1;
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                        if (line_word == ({CACHE_LINE_WORDS_IDX_MAX{1'b1}}-1))
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                        begin
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                            mem_burst_o <= 1'b0;
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                        end
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                    end
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                end
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            end
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            //-----------------------------------------
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            // READ_WAIT - Wait for data from cache
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            //-----------------------------------------
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            STATE_READ_WAIT :
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            begin
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                // Not used yet, but set for start of burst
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                mem_burst_o  <= 1'b1;
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                state        <= STATE_WRITE;
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            end
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            //-----------------------------------------
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            // WRITE - Write word to memory
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            //-----------------------------------------
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            STATE_WRITE :
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            begin
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                // Write data into memory from cache
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                mem_addr_o   <= {line_address, line_word, 2'b00};
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                mem_data_o   <= cache_data_i;
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                mem_wr_o     <= 4'b1111;
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                // Setup next word read from cache
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                v_line_word = line_word + 1'b1;
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                cache_addr_o <= {line_address, v_line_word};
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254
                state        <= STATE_WRITE_WAIT;
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            end
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            //-----------------------------------------
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            // WRITE_WAIT - Wait for write to complete
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            //-----------------------------------------
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            STATE_WRITE_WAIT:
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            begin
261
                // Write to memory complete
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                if (mem_ack_i && mem_wr_o == 4'b0)
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                begin
264
                    // Line write complete?
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                    if (line_word == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
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                    begin
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                        done_o      <= 1'b1;
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                        state       <= STATE_IDLE;
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                    end
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                    // Fetch next word for line
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                    else
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                    begin
273
                        line_word   <= line_word + 1'b1;
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                        state       <= STATE_WRITE;
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276
                        if (line_word == ({CACHE_LINE_WORDS_IDX_MAX{1'b1}}-1))
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                            mem_burst_o <= 1'b0;
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                    end
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                end
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            end
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            //-----------------------------------------
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            // READ_SINGLE - Single access to memory
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            //-----------------------------------------
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            STATE_READ_SINGLE:
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            begin
286
                // Data ready from memory?
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                if (mem_ack_i && mem_rd_o == 1'b0)
288
                begin
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                    data_o      <= mem_data_i;
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                    done_o      <= 1'b1;
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                    state       <= STATE_IDLE;
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                end
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            end
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            //-----------------------------------------
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            // WRITE_SINGLE - Single access to memory
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            //-----------------------------------------
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            STATE_WRITE_SINGLE:
298
            begin
299
                if (mem_ack_i && mem_wr_o == 4'b0)
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                begin
301
                    done_o      <= 1'b1;
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                    state       <= STATE_IDLE;
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                end
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            end
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            default:
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                ;
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           endcase
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   end
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end
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endmodule

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