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//-----------------------------------------------------------------
//                           AltOR32 
//                Alternative Lightweight OpenRisc 
//                            V2.0
//                     Ultra-Embedded.com
//                   Copyright 2011 - 2013
//
//               Email: admin@ultra-embedded.com
//
//                       License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without         
// restriction provided that this copyright statement is not    
// removed from the file and that any derivative work contains  
// the original copyright notice and the associated disclaimer. 
//
// This source file is free software; you can redistribute it   
// and/or modify it under the terms of the GNU Lesser General   
// Public License as published by the Free Software Foundation; 
// either version 2.1 of the License, or (at your option) any   
// later version.
//
// This source is distributed in the hope that it will be       
// useful, but WITHOUT ANY WARRANTY; without even the implied   
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
// PURPOSE.  See the GNU Lesser General Public License for more 
// details.
//
// You should have received a copy of the GNU Lesser General    
// Public License along with this source; if not, write to the 
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
// Boston, MA  02111-1307  USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// ALU Operations
//-----------------------------------------------------------------
`define ALU_NONE                                4'b0000
`define ALU_SHIFTL                              4'b0001
`define ALU_SHIFTR                              4'b0010
`define ALU_SHIRTR_ARITH                        4'b0011
`define ALU_ADD                                 4'b0100
`define ALU_ADDC                                4'b0101
`define ALU_SUB                                 4'b0110
`define ALU_AND                                 4'b0111
`define ALU_OR                                  4'b1000
`define ALU_XOR                                 4'b1001
 
//-----------------------------------------------------------------
// ALU Instructions
//-----------------------------------------------------------------
`define INST_OR32_ALU                            8'h38
`define INST_OR32_ADD                            8'h00
`define INST_OR32_ADDC                           8'h01
`define INST_OR32_AND                            8'h03
`define INST_OR32_OR                             8'h04
`define INST_OR32_SLL                            8'h08
`define INST_OR32_SRA                            8'h28
`define INST_OR32_SRL                            8'h18
`define INST_OR32_SUB                            8'h02
`define INST_OR32_XOR                            8'h05
`define INST_OR32_MUL                            8'hc6
`define INST_OR32_MULU                           8'hcb
 
//-----------------------------------------------------------------
// INST_OR32_SHIFTI Instructions
//-----------------------------------------------------------------
`define INST_OR32_SHIFTI                         8'h2E
`define INST_OR32_SLLI                           2'b00
`define INST_OR32_SRAI                           2'b10
`define INST_OR32_SRLI                           2'b01
 
//-----------------------------------------------------------------
// General Instructions
//-----------------------------------------------------------------
`define INST_OR32_ADDI                           8'h27
`define INST_OR32_ANDI                           8'h29
`define INST_OR32_BF                             8'h04
`define INST_OR32_BNF                            8'h03
`define INST_OR32_J                              8'h00
`define INST_OR32_JAL                            8'h01
`define INST_OR32_JALR                           8'h12
`define INST_OR32_JR                             8'h11
`define INST_OR32_MFSPR                          8'h2D
`define INST_OR32_MOVHI                          8'h06
`define INST_OR32_MTSPR                          8'h30
`define INST_OR32_NOP                            8'h05
`define INST_OR32_ORI                            8'h2A
`define INST_OR32_RFE                            8'h09
`define INST_OR32_SB                             8'h36
`define INST_OR32_SH                             8'h37
`define INST_OR32_SW                             8'h35
`define INST_OR32_XORI                           8'h2B
`define INST_OR32_LBS                            8'h24
`define INST_OR32_LBZ                            8'h23
`define INST_OR32_LHS                            8'h26
`define INST_OR32_LHZ                            8'h25
`define INST_OR32_LWZ                            8'h21
`define INST_OR32_LWS                            8'h22
 
//-----------------------------------------------------------------
// Set Flag Instructions
//-----------------------------------------------------------------
`define INST_OR32_SFXX                           8'h39
`define INST_OR32_SFXXI                          8'h2F
`define INST_OR32_SFEQ                           16'h0720
`define INST_OR32_SFEQI                          16'h05E0
`define INST_OR32_SFGES                          16'h072B
`define INST_OR32_SFGESI                         16'h05EB
`define INST_OR32_SFGEU                          16'h0723
`define INST_OR32_SFGEUI                         16'h05E3
`define INST_OR32_SFGTS                          16'h072A
`define INST_OR32_SFGTSI                         16'h05EA
`define INST_OR32_SFGTU                          16'h0722
`define INST_OR32_SFGTUI                         16'h05E2
`define INST_OR32_SFLES                          16'h072D
`define INST_OR32_SFLESI                         16'h05ED
`define INST_OR32_SFLEU                          16'h0725
`define INST_OR32_SFLEUI                         16'h05E5
`define INST_OR32_SFLTS                          16'h072C
`define INST_OR32_SFLTSI                         16'h05EC
`define INST_OR32_SFLTU                          16'h0724
`define INST_OR32_SFLTUI                         16'h05E4
`define INST_OR32_SFNE                           16'h0721
`define INST_OR32_SFNEI                          16'h05E1
 
//-----------------------------------------------------------------
// Misc Instructions
//-----------------------------------------------------------------
`define INST_OR32_MISC                           8'h08
`define INST_OR32_SYS                            8'h20
`define INST_OR32_TRAP                           8'h21
 
`define INST_OR32_BUBBLE                         8'h3F
`define OPCODE_INST_BUBBLE                       32'hFC000000
 
//-----------------------------------------------------------------
// SPR Register Map
//-----------------------------------------------------------------
`define SPR_REG_VR                               16'h0000
`define SPR_VERSION_CURRENT                      8'h00
`define SPR_REG_SR                               16'h0011
`define SPR_REG_EPCR                             16'h0020
`define SPR_REG_ESR                              16'h0040
 
`define SPR_REG_MACLO                            16'h0080
`define SPR_REG_MACHI                            16'h0081
 
//-----------------------------------------------------------------
// SR Register bits
//-----------------------------------------------------------------
`define OR32_SR_SM                               0
`define OR32_SR_TEE                              1
`define OR32_SR_IEE                              2
`define OR32_SR_DCE                              3
`define OR32_SR_ICE                              4
`define OR32_SR_DME                              5
`define OR32_SR_IME                              6
`define OR32_SR_LEE                              7
`define OR32_SR_CE                               8
`define OR32_SR_F                                9
`define OR32_SR_CY                               10
`define OR32_SR_OV                               11
`define OR32_SR_OVE                              12
`define OR32_SR_DSX                              13
`define OR32_SR_EPH                              14
`define OR32_SR_FO                               15
`define OR32_SR_TED                              16
`define OR32_SR_ICACHE_FLUSH                     17
`define OR32_SR_DCACHE_FLUSH                     18
 
//-----------------------------------------------------------------
// OR32 Vectors
// NOTE: These differ from the real OR32 vectors for space reasons
//-----------------------------------------------------------------
`define VECTOR_RESET                             32'h00000100
`define VECTOR_ILLEGAL_INST                      32'h00000200
`define VECTOR_EXTINT                            32'h00000300
`define VECTOR_SYSCALL                           32'h00000400
`define VECTOR_TRAP                              32'h00000600
`define VECTOR_NMI                               32'h00000700
`define VECTOR_BUS_ERROR                         32'h00000800

Line No.	Rev	Author	Line
1	27	ultra_embe	`//-----------------------------------------------------------------`
2			`// AltOR32`
3			`// Alternative Lightweight OpenRisc`
4			`// V2.0`
5			`// Ultra-Embedded.com`
6			`// Copyright 2011 - 2013`
7			`//`
8			`// Email: admin@ultra-embedded.com`
9			`//`
10			`// License: LGPL`
11			`//-----------------------------------------------------------------`
12			`//`
13			`// Copyright (C) 2011 - 2013 Ultra-Embedded.com`
14			`//`
15			`// This source file may be used and distributed without`
16			`// restriction provided that this copyright statement is not`
17			`// removed from the file and that any derivative work contains`
18			`// the original copyright notice and the associated disclaimer.`
19			`//`
20			`// This source file is free software; you can redistribute it`
21			`// and/or modify it under the terms of the GNU Lesser General`
22			`// Public License as published by the Free Software Foundation;`
23			`// either version 2.1 of the License, or (at your option) any`
24			`// later version.`
25			`//`
26			`// This source is distributed in the hope that it will be`
27			`// useful, but WITHOUT ANY WARRANTY; without even the implied`
28			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
29			`// PURPOSE. See the GNU Lesser General Public License for more`
30			`// details.`
31			`//`
32			`// You should have received a copy of the GNU Lesser General`
33			`// Public License along with this source; if not, write to the`
34			`// Free Software Foundation, Inc., 59 Temple Place, Suite 330,`
35			`// Boston, MA 02111-1307 USA`
36			`//-----------------------------------------------------------------`
37
38			`//-----------------------------------------------------------------`
39			`// ALU Operations`
40			`//-----------------------------------------------------------------`
41			`define ALU_NONE 4'b0000
42			`define ALU_SHIFTL 4'b0001
43			`define ALU_SHIFTR 4'b0010
44			`define ALU_SHIRTR_ARITH 4'b0011
45			`define ALU_ADD 4'b0100
46			`define ALU_ADDC 4'b0101
47			`define ALU_SUB 4'b0110
48			`define ALU_AND 4'b0111
49			`define ALU_OR 4'b1000
50			`define ALU_XOR 4'b1001
51
52			`//-----------------------------------------------------------------`
53			`// ALU Instructions`
54			`//-----------------------------------------------------------------`
55			`define INST_OR32_ALU 8'h38
56			`define INST_OR32_ADD 8'h00
57			`define INST_OR32_ADDC 8'h01
58			`define INST_OR32_AND 8'h03
59			`define INST_OR32_OR 8'h04
60			`define INST_OR32_SLL 8'h08
61			`define INST_OR32_SRA 8'h28
62			`define INST_OR32_SRL 8'h18
63			`define INST_OR32_SUB 8'h02
64			`define INST_OR32_XOR 8'h05
65			`define INST_OR32_MUL 8'hc6
66			`define INST_OR32_MULU 8'hcb
67
68			`//-----------------------------------------------------------------`
69			`// INST_OR32_SHIFTI Instructions`
70			`//-----------------------------------------------------------------`
71			`define INST_OR32_SHIFTI 8'h2E
72			`define INST_OR32_SLLI 2'b00
73			`define INST_OR32_SRAI 2'b10
74			`define INST_OR32_SRLI 2'b01
75
76			`//-----------------------------------------------------------------`
77			`// General Instructions`
78			`//-----------------------------------------------------------------`
79			`define INST_OR32_ADDI 8'h27
80			`define INST_OR32_ANDI 8'h29
81			`define INST_OR32_BF 8'h04
82			`define INST_OR32_BNF 8'h03
83			`define INST_OR32_J 8'h00
84			`define INST_OR32_JAL 8'h01
85			`define INST_OR32_JALR 8'h12
86			`define INST_OR32_JR 8'h11
87			`define INST_OR32_MFSPR 8'h2D
88			`define INST_OR32_MOVHI 8'h06
89			`define INST_OR32_MTSPR 8'h30
90			`define INST_OR32_NOP 8'h05
91			`define INST_OR32_ORI 8'h2A
92			`define INST_OR32_RFE 8'h09
93			`define INST_OR32_SB 8'h36
94			`define INST_OR32_SH 8'h37
95			`define INST_OR32_SW 8'h35
96			`define INST_OR32_XORI 8'h2B
97			`define INST_OR32_LBS 8'h24
98			`define INST_OR32_LBZ 8'h23
99			`define INST_OR32_LHS 8'h26
100			`define INST_OR32_LHZ 8'h25
101			`define INST_OR32_LWZ 8'h21
102			`define INST_OR32_LWS 8'h22
103
104			`//-----------------------------------------------------------------`
105			`// Set Flag Instructions`
106			`//-----------------------------------------------------------------`
107	31	ultra_embe	`define INST_OR32_SFXX 8'h39
108			`define INST_OR32_SFXXI 8'h2F
109	27	ultra_embe	`define INST_OR32_SFEQ 16'h0720
110			`define INST_OR32_SFEQI 16'h05E0
111			`define INST_OR32_SFGES 16'h072B
112			`define INST_OR32_SFGESI 16'h05EB
113			`define INST_OR32_SFGEU 16'h0723
114			`define INST_OR32_SFGEUI 16'h05E3
115			`define INST_OR32_SFGTS 16'h072A
116			`define INST_OR32_SFGTSI 16'h05EA
117			`define INST_OR32_SFGTU 16'h0722
118			`define INST_OR32_SFGTUI 16'h05E2
119			`define INST_OR32_SFLES 16'h072D
120			`define INST_OR32_SFLESI 16'h05ED
121			`define INST_OR32_SFLEU 16'h0725
122			`define INST_OR32_SFLEUI 16'h05E5
123			`define INST_OR32_SFLTS 16'h072C
124			`define INST_OR32_SFLTSI 16'h05EC
125			`define INST_OR32_SFLTU 16'h0724
126			`define INST_OR32_SFLTUI 16'h05E4
127			`define INST_OR32_SFNE 16'h0721
128			`define INST_OR32_SFNEI 16'h05E1
129
130			`//-----------------------------------------------------------------`
131			`// Misc Instructions`
132			`//-----------------------------------------------------------------`
133			`define INST_OR32_MISC 8'h08
134			`define INST_OR32_SYS 8'h20
135			`define INST_OR32_TRAP 8'h21
136
137			`define INST_OR32_BUBBLE 8'h3F
138			`define OPCODE_INST_BUBBLE 32'hFC000000
139
140			`//-----------------------------------------------------------------`
141			`// SPR Register Map`
142			`//-----------------------------------------------------------------`
143			`define SPR_REG_VR 16'h0000
144			`define SPR_VERSION_CURRENT 8'h00
145			`define SPR_REG_SR 16'h0011
146			`define SPR_REG_EPCR 16'h0020
147			`define SPR_REG_ESR 16'h0040
148
149			`define SPR_REG_MACLO 16'h0080
150			`define SPR_REG_MACHI 16'h0081
151
152			`//-----------------------------------------------------------------`
153			`// SR Register bits`
154			`//-----------------------------------------------------------------`
155			`define OR32_SR_SM 0
156			`define OR32_SR_TEE 1
157			`define OR32_SR_IEE 2
158			`define OR32_SR_DCE 3
159			`define OR32_SR_ICE 4
160			`define OR32_SR_DME 5
161			`define OR32_SR_IME 6
162			`define OR32_SR_LEE 7
163			`define OR32_SR_CE 8
164			`define OR32_SR_F 9
165			`define OR32_SR_CY 10
166			`define OR32_SR_OV 11
167			`define OR32_SR_OVE 12
168			`define OR32_SR_DSX 13
169			`define OR32_SR_EPH 14
170			`define OR32_SR_FO 15
171			`define OR32_SR_TED 16
172			`define OR32_SR_ICACHE_FLUSH 17
173			`define OR32_SR_DCACHE_FLUSH 18
174
175			`//-----------------------------------------------------------------`
176			`// OR32 Vectors`
177			`// NOTE: These differ from the real OR32 vectors for space reasons`
178			`//-----------------------------------------------------------------`
179			`define VECTOR_RESET 32'h00000100
180			`define VECTOR_ILLEGAL_INST 32'h00000200
181			`define VECTOR_EXTINT 32'h00000300
182			`define VECTOR_SYSCALL 32'h00000400
183			`define VECTOR_TRAP 32'h00000600
184			`define VECTOR_NMI 32'h00000700
185			`define VECTOR_BUS_ERROR 32'h00000800

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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_defs.v] - Blame information for rev 31