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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_fetch.v] - Blame information for rev 29

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1 27 ultra_embe
//-----------------------------------------------------------------
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//                           AltOR32 
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//                Alternative Lightweight OpenRisc 
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//                            V2.0
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//                     Ultra-Embedded.com
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//                   Copyright 2011 - 2013
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//
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//               Email: admin@ultra-embedded.com
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//
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//                       License: LGPL
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//-----------------------------------------------------------------
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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// This source file may be used and distributed without         
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// restriction provided that this copyright statement is not    
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// removed from the file and that any derivative work contains  
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// the original copyright notice and the associated disclaimer. 
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//
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// This source file is free software; you can redistribute it   
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// and/or modify it under the terms of the GNU Lesser General   
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// Public License as published by the Free Software Foundation; 
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// either version 2.1 of the License, or (at your option) any   
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// later version.
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//
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// This source is distributed in the hope that it will be       
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// useful, but WITHOUT ANY WARRANTY; without even the implied   
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
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// PURPOSE.  See the GNU Lesser General Public License for more 
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// details.
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//
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// You should have received a copy of the GNU Lesser General    
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// Public License along with this source; if not, write to the 
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
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// Boston, MA  02111-1307  USA
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//-----------------------------------------------------------------
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//`define CONF_FETCH_DEBUG
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//-----------------------------------------------------------------
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// Includes
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//-----------------------------------------------------------------
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`include "altor32_defs.v"
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//-----------------------------------------------------------------
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// Module - Instruction Fetch
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//-----------------------------------------------------------------
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module altor32_fetch
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(
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    // General
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    input               clk_i /*verilator public*/,
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    input               rst_i /*verilator public*/,
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    // Instruction Fetch
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    output              fetch_o /*verilator public*/,
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    output [31:0]       pc_o /*verilator public*/,
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    input [31:0]        data_i /*verilator public*/,
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    input               data_valid_i/*verilator public*/,
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    // Branch target
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    input               branch_i /*verilator public*/,
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    input [31:0]        branch_pc_i /*verilator public*/,
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    input               stall_i /*verilator public*/,
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    // Decoded opcode
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    output [31:0]       opcode_o /*verilator public*/,
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    output [31:0]       opcode_pc_o /*verilator public*/,
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    output              opcode_valid_o /*verilator public*/,
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    // Decoded register details
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    output [4:0]        ra_o /*verilator public*/,
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    output [4:0]        rb_o /*verilator public*/,
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    output [4:0]        rd_o /*verilator public*/
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);
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//-----------------------------------------------------------------
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// Params
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//-----------------------------------------------------------------
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parameter           BOOT_VECTOR             = 32'h00000000;
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parameter           CACHE_LINE_SIZE_WIDTH   = 5; /* 5-bits -> 32 entries */
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//-----------------------------------------------------------------
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// Registers
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//-----------------------------------------------------------------
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reg [31:0]  r_pc;
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reg         r_rd;
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reg [31:0]  r_last_opcode;
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reg [31:0]  r_last_pc;
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reg         r_last_valid;
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reg [31:0]  d_pc;
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//-------------------------------------------------------------------
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// Next PC state machine
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//-------------------------------------------------------------------
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reg [31:0] v_pc;
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always @ (posedge clk_i or posedge rst_i)
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begin
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   if (rst_i)
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   begin
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        r_pc        <= BOOT_VECTOR + `VECTOR_RESET;
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        d_pc        <= BOOT_VECTOR + `VECTOR_RESET;
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        r_rd        <= 1'b1;
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   end
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   else
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   begin
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        r_rd        <= 1'b0;
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        d_pc        <= pc_o;
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        // Branch - Next PC = branch target + 4
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        if (branch_i)
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        begin
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            r_pc <= branch_pc_i + 4;
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        end
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        // Stall - rollback to previous PC + 4
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        else if (stall_i)
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        begin
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            r_pc <= d_pc + 4;
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        end
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        // Normal sequential execution (and instruction is ready)
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        else if (data_valid_i)
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        begin
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            v_pc = r_pc + 4;
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            // New cache line?
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            if (v_pc[CACHE_LINE_SIZE_WIDTH-1:0] == {CACHE_LINE_SIZE_WIDTH{1'b0}})
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            begin
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                // Start fetch of next line
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                r_rd  <= 1'b1;
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            end
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            r_pc <= v_pc;
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        end
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   end
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end
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//-------------------------------------------------------------------
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// Pipeline storage of last PC/opcode passed to exec stage
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//-------------------------------------------------------------------
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always @ (posedge clk_i or posedge rst_i)
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begin
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   if (rst_i)
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   begin
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        r_last_opcode   <= 32'b0;
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        r_last_pc       <= 32'b0;
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        r_last_valid    <= 1'b0;
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   end
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   else
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   begin
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        // Record last valid instruction passed to exec stage
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        if (!stall_i | !data_valid_i)
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        begin
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            r_last_pc        <= opcode_pc_o;
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            r_last_opcode    <= opcode_o;
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            r_last_valid     <= opcode_valid_o;
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        end
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   end
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end
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//-------------------------------------------------------------------
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// Assignments
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//-------------------------------------------------------------------
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// Instruction Fetch
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assign pc_o            = stall_i ? d_pc : (branch_i ? branch_pc_i : (~data_valid_i ? d_pc : r_pc));
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assign fetch_o         = branch_i ? 1'b1 : r_rd;
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// Opcode output
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assign opcode_valid_o  = stall_i ? r_last_valid : (data_valid_i & !branch_i);
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assign opcode_o        = stall_i ? r_last_opcode : (opcode_valid_o ? data_i : 32'b0);
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assign opcode_pc_o     = stall_i ? r_last_pc : (opcode_valid_o ? d_pc : 32'b0);
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// If simulation, RA = 03 if NOP instruction
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`ifdef SIMULATION
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    wire [7:0] v_fetch_inst = {2'b00, opcode_o[31:26]};
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    wire       v_is_nop     = (v_fetch_inst == `INST_OR32_NOP);
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    assign     ra_o         = v_is_nop ? 5'd3 : opcode_o[20:16];
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`else
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    assign     ra_o         = opcode_o[20:16];
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`endif
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assign rb_o            = opcode_o[15:11];
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assign rd_o            = opcode_o[25:21];
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endmodule

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