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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_lfu.v] - Blame information for rev 32

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1 27 ultra_embe
//-----------------------------------------------------------------
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//                           AltOR32 
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//                Alternative Lightweight OpenRisc 
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//                            V2.0
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//                     Ultra-Embedded.com
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//                   Copyright 2011 - 2013
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//
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//               Email: admin@ultra-embedded.com
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//
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//                       License: LGPL
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//-----------------------------------------------------------------
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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// This source file may be used and distributed without         
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// restriction provided that this copyright statement is not    
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// removed from the file and that any derivative work contains  
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// the original copyright notice and the associated disclaimer. 
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//
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// This source file is free software; you can redistribute it   
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// and/or modify it under the terms of the GNU Lesser General   
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// Public License as published by the Free Software Foundation; 
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// either version 2.1 of the License, or (at your option) any   
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// later version.
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//
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// This source is distributed in the hope that it will be       
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// useful, but WITHOUT ANY WARRANTY; without even the implied   
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
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// PURPOSE.  See the GNU Lesser General Public License for more 
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// details.
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//
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// You should have received a copy of the GNU Lesser General    
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// Public License along with this source; if not, write to the 
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
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// Boston, MA  02111-1307  USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Includes
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//-----------------------------------------------------------------
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`include "altor32_defs.v"
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//-----------------------------------------------------------------
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// Module: Load Forwarding Unit
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//-----------------------------------------------------------------
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module altor32_lfu
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(
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    // Opcode
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    input [7:0]         opcode_i /*verilator public*/,
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    // Memory load result
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    input [31:0]        mem_result_i /*verilator public*/,
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    input [1:0]         mem_offset_i /*verilator public*/,
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    // Result
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    output reg [31:0]   load_result_o /*verilator public*/,
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    output reg          load_insn_o /*verilator public*/
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);
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//-------------------------------------------------------------------
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// Load forwarding unit
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//-------------------------------------------------------------------
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always @ *
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begin
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    load_result_o   = 32'h00000000;
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    load_insn_o     = 1'b0;
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    case (opcode_i)
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        `INST_OR32_LBS: // l.lbs
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        begin
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            case (mem_offset_i)
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                2'b00 :   load_result_o[7:0] = mem_result_i[31:24];
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                2'b01 :   load_result_o[7:0] = mem_result_i[23:16];
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                2'b10 :   load_result_o[7:0] = mem_result_i[15:8];
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                2'b11 :   load_result_o[7:0] = mem_result_i[7:0];
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                default : ;
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            endcase
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            // Sign extend LB
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            if (load_result_o[7] == 1'b1)
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                load_result_o[31:8] = 24'hFFFFFF;
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            load_insn_o = 1'b1;
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        end
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        `INST_OR32_LBZ: // l.lbz
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        begin
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            case (mem_offset_i)
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                2'b00 :   load_result_o[7:0] = mem_result_i[31:24];
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                2'b01 :   load_result_o[7:0] = mem_result_i[23:16];
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                2'b10 :   load_result_o[7:0] = mem_result_i[15:8];
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                2'b11 :   load_result_o[7:0] = mem_result_i[7:0];
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                default : ;
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            endcase
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            load_insn_o = 1'b1;
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        end
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        `INST_OR32_LHS: // l.lhs
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        begin
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            case (mem_offset_i)
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                2'b00 :   load_result_o[15:0] = mem_result_i[31:16];
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                2'b10 :   load_result_o[15:0] = mem_result_i[15:0];
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                default : ;
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            endcase
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            // Sign extend LH
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            if (load_result_o[15] == 1'b1)
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                load_result_o[31:16] = 16'hFFFF;
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            load_insn_o = 1'b1;
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        end
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        `INST_OR32_LHZ: // l.lhz
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        begin
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            case (mem_offset_i)
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                2'b00 :   load_result_o[15:0] = mem_result_i[31:16];
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                2'b10 :   load_result_o[15:0] = mem_result_i[15:0];
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                default : ;
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            endcase
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            load_insn_o = 1'b1;
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        end
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        `INST_OR32_LWZ, `INST_OR32_LWS: // l.lwz l.lws
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        begin
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            load_result_o   = mem_result_i;
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            load_insn_o  = 1'b1;
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        end
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        default :
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            ;
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    endcase
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end
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endmodule

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