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ultra_embe |
//-----------------------------------------------------------------
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// AltOR32
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// Alternative Lightweight OpenRisc
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// V2.0
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// Ultra-Embedded.com
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// Copyright 2011 - 2013
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//
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// Email: admin@ultra-embedded.com
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//
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// License: LGPL
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//-----------------------------------------------------------------
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, write to the
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Boston, MA 02111-1307 USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Module: altor32_ram_sp - Single port RAM (used in cache)
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//-----------------------------------------------------------------
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30 |
ultra_embe |
module altor32_ram_sp
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#(
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parameter [31:0] WIDTH = 8,
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parameter [31:0] SIZE = 14
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)
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ultra_embe |
(
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input clk_i /*verilator public*/,
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output [(WIDTH - 1):0] dat_o /*verilator public*/,
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input [(WIDTH - 1):0] dat_i /*verilator public*/,
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input [(SIZE - 1):0] adr_i /*verilator public*/,
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input wr_i /*verilator public*/
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);
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//-----------------------------------------------------------------
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// Registers
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//-----------------------------------------------------------------
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reg [(WIDTH - 1):0] ram [((2<< (SIZE-1)) - 1):0] /*verilator public*/;
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reg [(SIZE - 1):0] rd_addr;
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//-----------------------------------------------------------------
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// Processes
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//-----------------------------------------------------------------
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always @ (posedge clk_i)
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begin
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if (wr_i == 1'b1)
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ram[adr_i] <= dat_i;
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rd_addr <= adr_i;
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end
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//-------------------------------------------------------------------
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// Combinatorial
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//-------------------------------------------------------------------
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assign dat_o = ram[rd_addr];
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endmodule
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