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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_writeback.v] - Blame information for rev 29

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1 27 ultra_embe
//-----------------------------------------------------------------
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//                           AltOR32 
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//                Alternative Lightweight OpenRisc 
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//                            V2.0
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//                     Ultra-Embedded.com
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//                   Copyright 2011 - 2013
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//
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//               Email: admin@ultra-embedded.com
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//
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//                       License: LGPL
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//-----------------------------------------------------------------
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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// This source file may be used and distributed without         
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// restriction provided that this copyright statement is not    
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// removed from the file and that any derivative work contains  
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// the original copyright notice and the associated disclaimer. 
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//
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// This source file is free software; you can redistribute it   
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// and/or modify it under the terms of the GNU Lesser General   
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// Public License as published by the Free Software Foundation; 
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// either version 2.1 of the License, or (at your option) any   
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// later version.
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//
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// This source is distributed in the hope that it will be       
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// useful, but WITHOUT ANY WARRANTY; without even the implied   
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
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// PURPOSE.  See the GNU Lesser General Public License for more 
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// details.
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//
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// You should have received a copy of the GNU Lesser General    
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// Public License along with this source; if not, write to the 
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
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// Boston, MA  02111-1307  USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Includes
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//-----------------------------------------------------------------
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`include "altor32_defs.v"
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//-----------------------------------------------------------------
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// Module - Writeback
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//-----------------------------------------------------------------
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module altor32_writeback
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(
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    // General
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    input               clk_i /*verilator public*/,
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    input               rst_i /*verilator public*/,
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    // Opcode
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    input [31:0]        opcode_i /*verilator public*/,
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    // Register target
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    input [4:0]         rd_i /*verilator public*/,
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    // ALU result
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    input [31:0]        alu_result_i /*verilator public*/,
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    // Memory load result
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    input [31:0]        mem_result_i /*verilator public*/,
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    input [1:0]         mem_offset_i /*verilator public*/,
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    input               mem_ready_i /*verilator public*/,
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    // Multiplier result
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    input               mult_i /*verilator public*/,
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    input [31:0]        mult_result_i /*verilator public*/,
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    // Outputs
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    output              write_enable_o /*verilator public*/,
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    output [4:0]        write_addr_o /*verilator public*/,
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    output [31:0]       write_data_o /*verilator public*/
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);
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//-----------------------------------------------------------------
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// Registers
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//-----------------------------------------------------------------
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// Register address
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reg [4:0]  r_w_rd;
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// Register writeback value
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reg [31:0] r_result;
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reg [7:0]  r_opcode;
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// Register writeback enable
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reg        r_w_write_rd;
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//-------------------------------------------------------------------
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// Writeback
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//-------------------------------------------------------------------
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always @ (posedge clk_i or posedge rst_i)
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begin
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   if (rst_i == 1'b1)
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   begin
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       r_w_write_rd <= 1'b1;
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       r_result     <= 32'h00000000;
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       r_w_rd       <= 5'b00000;
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       r_opcode     <= 8'b0;
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   end
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   else
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   begin
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        r_w_write_rd    <= 1'b0;
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        r_w_rd          <= rd_i;
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        r_result        <= alu_result_i;
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        r_opcode        <= {2'b00,opcode_i[31:26]};
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        // Register writeback required?
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        if (rd_i != 5'b00000)
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            r_w_write_rd <= 1'b1;
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   end
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end
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//-------------------------------------------------------------------
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// Load result resolve
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//-------------------------------------------------------------------
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wire            load_insn;
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wire [31:0]     load_result;
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altor32_lfu
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u_lfu
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(
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    // Opcode
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    .opcode_i(r_opcode),
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    // Memory load result
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    .mem_result_i(mem_result_i),
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    .mem_offset_i(mem_offset_i),
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    // Result
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    .load_result_o(load_result),
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    .load_insn_o(load_insn)
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);
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//-------------------------------------------------------------------
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// Assignments
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//-------------------------------------------------------------------
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assign write_enable_o = load_insn ? (r_w_write_rd & mem_ready_i) : r_w_write_rd;
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assign write_data_o   = load_insn ? load_result : (mult_i ? mult_result_i : r_result);
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assign write_addr_o   = r_w_rd;
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endmodule

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