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//-----------------------------------------------------------------
//                           AltOR32 
//                Alternative Lightweight OpenRisc 
//                            V2.1
//                     Ultra-Embedded.com
//                   Copyright 2011 - 2014
//
//               Email: admin@ultra-embedded.com
//
//                       License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
//
// This source file may be used and distributed without         
// restriction provided that this copyright statement is not    
// removed from the file and that any derivative work contains  
// the original copyright notice and the associated disclaimer. 
//
// This source file is free software; you can redistribute it   
// and/or modify it under the terms of the GNU Lesser General   
// Public License as published by the Free Software Foundation; 
// either version 2.1 of the License, or (at your option) any   
// later version.
//
// This source is distributed in the hope that it will be       
// useful, but WITHOUT ANY WARRANTY; without even the implied   
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
// PURPOSE.  See the GNU Lesser General Public License for more 
// details.
//
// You should have received a copy of the GNU Lesser General    
// Public License along with this source; if not, write to the 
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
// Boston, MA  02111-1307  USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "altor32_defs.v"
 
//-----------------------------------------------------------------
// Module - Simulation register file
//-----------------------------------------------------------------
module altor32_regfile_sim
(
    input             clk_i               /*verilator public*/,
    input             rst_i               /*verilator public*/,
    input             wr_i                /*verilator public*/,
    input [4:0]       ra_i                /*verilator public*/,
    input [4:0]       rb_i                /*verilator public*/,
    input [4:0]       rd_i                /*verilator public*/,
    output reg [31:0] reg_ra_o            /*verilator public*/,
    output reg [31:0] reg_rb_o            /*verilator public*/,
    input [31:0]      reg_rd_i            /*verilator public*/
);
 
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter       SUPPORT_32REGS = "ENABLED";
 
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
 
// Register file
reg [31:0] reg_r1_sp;
reg [31:0] reg_r2_fp;
reg [31:0] reg_r3;
reg [31:0] reg_r4;
reg [31:0] reg_r5;
reg [31:0] reg_r6;
reg [31:0] reg_r7;
reg [31:0] reg_r8;
reg [31:0] reg_r9_lr;
reg [31:0] reg_r10;
reg [31:0] reg_r11;
reg [31:0] reg_r12;
reg [31:0] reg_r13;
reg [31:0] reg_r14;
reg [31:0] reg_r15;
reg [31:0] reg_r16;
reg [31:0] reg_r17;
reg [31:0] reg_r18;
reg [31:0] reg_r19;
reg [31:0] reg_r20;
reg [31:0] reg_r21;
reg [31:0] reg_r22;
reg [31:0] reg_r23;
reg [31:0] reg_r24;
reg [31:0] reg_r25;
reg [31:0] reg_r26;
reg [31:0] reg_r27;
reg [31:0] reg_r28;
reg [31:0] reg_r29;
reg [31:0] reg_r30;
reg [31:0] reg_r31;
 
//-----------------------------------------------------------------
// Register File (for simulation)
//-----------------------------------------------------------------
 
// Synchronous register write back
always @ (posedge clk_i or posedge rst_i)
begin
   if (rst_i)
   begin
        reg_r1_sp   <= 32'h00000000;
        reg_r2_fp   <= 32'h00000000;
        reg_r3      <= 32'h00000000;
        reg_r4      <= 32'h00000000;
        reg_r5      <= 32'h00000000;
        reg_r6      <= 32'h00000000;
        reg_r7      <= 32'h00000000;
        reg_r8      <= 32'h00000000;
        reg_r9_lr   <= 32'h00000000;
        reg_r10     <= 32'h00000000;
        reg_r11     <= 32'h00000000;
        reg_r12     <= 32'h00000000;
        reg_r13     <= 32'h00000000;
        reg_r14     <= 32'h00000000;
        reg_r15     <= 32'h00000000;
        reg_r16     <= 32'h00000000;
        reg_r17     <= 32'h00000000;
        reg_r18     <= 32'h00000000;
        reg_r19     <= 32'h00000000;
        reg_r20     <= 32'h00000000;
        reg_r21     <= 32'h00000000;
        reg_r22     <= 32'h00000000;
        reg_r23     <= 32'h00000000;
        reg_r24     <= 32'h00000000;
        reg_r25     <= 32'h00000000;
        reg_r26     <= 32'h00000000;
        reg_r27     <= 32'h00000000;
        reg_r28     <= 32'h00000000;
        reg_r29     <= 32'h00000000;
        reg_r30     <= 32'h00000000;
        reg_r31     <= 32'h00000000;
   end
   else
   begin
       if (wr_i == 1'b1)
           case (rd_i[4:0])
               5'b00001 :
                       reg_r1_sp <= reg_rd_i;
               5'b00010 :
                       reg_r2_fp <= reg_rd_i;
               5'b00011 :
                       reg_r3 <= reg_rd_i;
               5'b00100 :
                       reg_r4 <= reg_rd_i;
               5'b00101 :
                       reg_r5 <= reg_rd_i;
               5'b00110 :
                       reg_r6 <= reg_rd_i;
               5'b00111 :
                       reg_r7 <= reg_rd_i;
               5'b01000 :
                       reg_r8 <= reg_rd_i;
               5'b01001 :
                       reg_r9_lr <= reg_rd_i;
               5'b01010 :
                       reg_r10 <= reg_rd_i;
               5'b01011 :
                       reg_r11 <= reg_rd_i;
               5'b01100 :
                       reg_r12 <= reg_rd_i;
               5'b01101 :
                       reg_r13 <= reg_rd_i;
               5'b01110 :
                       reg_r14 <= reg_rd_i;
               5'b01111 :
                       reg_r15 <= reg_rd_i;
               5'b10000 :
                       reg_r16 <= reg_rd_i;
               5'b10001 :
                       reg_r17 <= reg_rd_i;
               5'b10010 :
                       reg_r18 <= reg_rd_i;
               5'b10011 :
                       reg_r19 <= reg_rd_i;
               5'b10100 :
                       reg_r20 <= reg_rd_i;
               5'b10101 :
                       reg_r21 <= reg_rd_i;
               5'b10110 :
                       reg_r22 <= reg_rd_i;
               5'b10111 :
                       reg_r23 <= reg_rd_i;
               5'b11000 :
                       reg_r24 <= reg_rd_i;
               5'b11001 :
                       reg_r25 <= reg_rd_i;
               5'b11010 :
                       reg_r26 <= reg_rd_i;
               5'b11011 :
                       reg_r27 <= reg_rd_i;
               5'b11100 :
                       reg_r28 <= reg_rd_i;
               5'b11101 :
                       reg_r29 <= reg_rd_i;
               5'b11110 :
                       reg_r30 <= reg_rd_i;
               5'b11111 :
                       reg_r31 <= reg_rd_i;
               default :
                   ;
           endcase
   end
end
 
generate
if (SUPPORT_32REGS == "ENABLED")
begin
    // Asynchronous Register read (Rs & Rd)
    always @ *
    begin
       case (ra_i)
           5'b00000 :
                   reg_ra_o = 32'h00000000;
           5'b00001 :
                   reg_ra_o = reg_r1_sp;
           5'b00010 :
                   reg_ra_o = reg_r2_fp;
           5'b00011 :
                   reg_ra_o = reg_r3;
           5'b00100 :
                   reg_ra_o = reg_r4;
           5'b00101 :
                   reg_ra_o = reg_r5;
           5'b00110 :
                   reg_ra_o = reg_r6;
           5'b00111 :
                   reg_ra_o = reg_r7;
           5'b01000 :
                   reg_ra_o = reg_r8;
           5'b01001 :
                   reg_ra_o = reg_r9_lr;
           5'b01010 :
                   reg_ra_o = reg_r10;
           5'b01011 :
                   reg_ra_o = reg_r11;
           5'b01100 :
                   reg_ra_o = reg_r12;
           5'b01101 :
                   reg_ra_o = reg_r13;
           5'b01110 :
                   reg_ra_o = reg_r14;
           5'b01111 :
                   reg_ra_o = reg_r15;
           5'b10000 :
                   reg_ra_o = reg_r16;
           5'b10001 :
                   reg_ra_o = reg_r17;
           5'b10010 :
                   reg_ra_o = reg_r18;
           5'b10011 :
                   reg_ra_o = reg_r19;
           5'b10100 :
                   reg_ra_o = reg_r20;
           5'b10101 :
                   reg_ra_o = reg_r21;
           5'b10110 :
                   reg_ra_o = reg_r22;
           5'b10111 :
                   reg_ra_o = reg_r23;
           5'b11000 :
                   reg_ra_o = reg_r24;
           5'b11001 :
                   reg_ra_o = reg_r25;
           5'b11010 :
                   reg_ra_o = reg_r26;
           5'b11011 :
                   reg_ra_o = reg_r27;
           5'b11100 :
                   reg_ra_o = reg_r28;
           5'b11101 :
                   reg_ra_o = reg_r29;
           5'b11110 :
                   reg_ra_o = reg_r30;
           5'b11111 :
                   reg_ra_o = reg_r31;
           default :
                   reg_ra_o = 32'h00000000;
       endcase
 
       case (rb_i)
           5'b00000 :
                   reg_rb_o = 32'h00000000;
           5'b00001 :
                   reg_rb_o = reg_r1_sp;
           5'b00010 :
                   reg_rb_o = reg_r2_fp;
           5'b00011 :
                   reg_rb_o = reg_r3;
           5'b00100 :
                   reg_rb_o = reg_r4;
           5'b00101 :
                   reg_rb_o = reg_r5;
           5'b00110 :
                   reg_rb_o = reg_r6;
           5'b00111 :
                   reg_rb_o = reg_r7;
           5'b01000 :
                   reg_rb_o = reg_r8;
           5'b01001 :
                   reg_rb_o = reg_r9_lr;
           5'b01010 :
                   reg_rb_o = reg_r10;
           5'b01011 :
                   reg_rb_o = reg_r11;
           5'b01100 :
                   reg_rb_o = reg_r12;
           5'b01101 :
                   reg_rb_o = reg_r13;
           5'b01110 :
                   reg_rb_o = reg_r14;
           5'b01111 :
                   reg_rb_o = reg_r15;
           5'b10000 :
                   reg_rb_o = reg_r16;
           5'b10001 :
                   reg_rb_o = reg_r17;
           5'b10010 :
                   reg_rb_o = reg_r18;
           5'b10011 :
                   reg_rb_o = reg_r19;
           5'b10100 :
                   reg_rb_o = reg_r20;
           5'b10101 :
                   reg_rb_o = reg_r21;
           5'b10110 :
                   reg_rb_o = reg_r22;
           5'b10111 :
                   reg_rb_o = reg_r23;
           5'b11000 :
                   reg_rb_o = reg_r24;
           5'b11001 :
                   reg_rb_o = reg_r25;
           5'b11010 :
                   reg_rb_o = reg_r26;
           5'b11011 :
                   reg_rb_o = reg_r27;
           5'b11100 :
                   reg_rb_o = reg_r28;
           5'b11101 :
                   reg_rb_o = reg_r29;
           5'b11110 :
                   reg_rb_o = reg_r30;
           5'b11111 :
                   reg_rb_o = reg_r31;
           default :
                   reg_rb_o = 32'h00000000;
       endcase
    end
end
else
begin
    // Asynchronous Register read (Rs & Rd)
    always @ *
    begin
       case (ra_i)
           5'b00000 :
                   reg_ra_o = 32'h00000000;
           5'b00001 :
                   reg_ra_o = reg_r1_sp;
           5'b00010 :
                   reg_ra_o = reg_r2_fp;
           5'b00011 :
                   reg_ra_o = reg_r3;
           5'b00100 :
                   reg_ra_o = reg_r4;
           5'b00101 :
                   reg_ra_o = reg_r5;
           5'b00110 :
                   reg_ra_o = reg_r6;
           5'b00111 :
                   reg_ra_o = reg_r7;
           5'b01000 :
                   reg_ra_o = reg_r8;
           5'b01001 :
                   reg_ra_o = reg_r9_lr;
           5'b01010 :
                   reg_ra_o = reg_r10;
           5'b01011 :
                   reg_ra_o = reg_r11;
           5'b01100 :
                   reg_ra_o = reg_r12;
           5'b01101 :
                   reg_ra_o = reg_r13;
           5'b01110 :
                   reg_ra_o = reg_r14;
           5'b01111 :
                   reg_ra_o = reg_r15;
           default :
                   reg_ra_o = 32'h00000000;
       endcase
 
       case (rb_i)
           5'b00000 :
                   reg_rb_o = 32'h00000000;
           5'b00001 :
                   reg_rb_o = reg_r1_sp;
           5'b00010 :
                   reg_rb_o = reg_r2_fp;
           5'b00011 :
                   reg_rb_o = reg_r3;
           5'b00100 :
                   reg_rb_o = reg_r4;
           5'b00101 :
                   reg_rb_o = reg_r5;
           5'b00110 :
                   reg_rb_o = reg_r6;
           5'b00111 :
                   reg_rb_o = reg_r7;
           5'b01000 :
                   reg_rb_o = reg_r8;
           5'b01001 :
                   reg_rb_o = reg_r9_lr;
           5'b01010 :
                   reg_rb_o = reg_r10;
           5'b01011 :
                   reg_rb_o = reg_r11;
           5'b01100 :
                   reg_rb_o = reg_r12;
           5'b01101 :
                   reg_rb_o = reg_r13;
           5'b01110 :
                   reg_rb_o = reg_r14;
           5'b01111 :
                   reg_rb_o = reg_r15;
           default :
                   reg_rb_o = 32'h00000000;
       endcase
    end
end
endgenerate
 
endmodule

Line No.	Rev	Author	Line
1	34	ultra_embe	`//-----------------------------------------------------------------`
2			`// AltOR32`
3			`// Alternative Lightweight OpenRisc`
4	36	ultra_embe	`// V2.1`
5	34	ultra_embe	`// Ultra-Embedded.com`
6	36	ultra_embe	`// Copyright 2011 - 2014`
7	34	ultra_embe	`//`
8			`// Email: admin@ultra-embedded.com`
9			`//`
10			`// License: LGPL`
11			`//-----------------------------------------------------------------`
12			`//`
13	37	ultra_embe	`// Copyright (C) 2011 - 2014 Ultra-Embedded.com`
14	34	ultra_embe	`//`
15			`// This source file may be used and distributed without`
16			`// restriction provided that this copyright statement is not`
17			`// removed from the file and that any derivative work contains`
18			`// the original copyright notice and the associated disclaimer.`
19			`//`
20			`// This source file is free software; you can redistribute it`
21			`// and/or modify it under the terms of the GNU Lesser General`
22			`// Public License as published by the Free Software Foundation;`
23			`// either version 2.1 of the License, or (at your option) any`
24			`// later version.`
25			`//`
26			`// This source is distributed in the hope that it will be`
27			`// useful, but WITHOUT ANY WARRANTY; without even the implied`
28			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
29			`// PURPOSE. See the GNU Lesser General Public License for more`
30			`// details.`
31			`//`
32			`// You should have received a copy of the GNU Lesser General`
33			`// Public License along with this source; if not, write to the`
34			`// Free Software Foundation, Inc., 59 Temple Place, Suite 330,`
35			`// Boston, MA 02111-1307 USA`
36			`//-----------------------------------------------------------------`
37
38			`//-----------------------------------------------------------------`
39			`// Includes`
40			`//-----------------------------------------------------------------`
41			`include "altor32_defs.v"
42
43			`//-----------------------------------------------------------------`
44			`// Module - Simulation register file`
45			`//-----------------------------------------------------------------`
46			`module altor32_regfile_sim`
47			`(`
48			`input clk_i /verilator public/,`
49			`input rst_i /verilator public/,`
50			`input wr_i /verilator public/,`
51	37	ultra_embe	`input [4:0] ra_i /verilator public/,`
52			`input [4:0] rb_i /verilator public/,`
53	34	ultra_embe	`input [4:0] rd_i /verilator public/,`
54	37	ultra_embe	`output reg [31:0] reg_ra_o /verilator public/,`
55			`output reg [31:0] reg_rb_o /verilator public/,`
56	34	ultra_embe	`input [31:0] reg_rd_i /verilator public/`
57			`);`
58
59			`//-----------------------------------------------------------------`
60			`// Params`
61			`//-----------------------------------------------------------------`
62			`parameter SUPPORT_32REGS = "ENABLED";`
63
64			`//-----------------------------------------------------------------`
65			`// Registers`
66			`//-----------------------------------------------------------------`
67
68			`// Register file`
69			`reg [31:0] reg_r1_sp;`
70			`reg [31:0] reg_r2_fp;`
71			`reg [31:0] reg_r3;`
72			`reg [31:0] reg_r4;`
73			`reg [31:0] reg_r5;`
74			`reg [31:0] reg_r6;`
75			`reg [31:0] reg_r7;`
76			`reg [31:0] reg_r8;`
77			`reg [31:0] reg_r9_lr;`
78			`reg [31:0] reg_r10;`
79			`reg [31:0] reg_r11;`
80			`reg [31:0] reg_r12;`
81			`reg [31:0] reg_r13;`
82			`reg [31:0] reg_r14;`
83			`reg [31:0] reg_r15;`
84			`reg [31:0] reg_r16;`
85			`reg [31:0] reg_r17;`
86			`reg [31:0] reg_r18;`
87			`reg [31:0] reg_r19;`
88			`reg [31:0] reg_r20;`
89			`reg [31:0] reg_r21;`
90			`reg [31:0] reg_r22;`
91			`reg [31:0] reg_r23;`
92			`reg [31:0] reg_r24;`
93			`reg [31:0] reg_r25;`
94			`reg [31:0] reg_r26;`
95			`reg [31:0] reg_r27;`
96			`reg [31:0] reg_r28;`
97			`reg [31:0] reg_r29;`
98			`reg [31:0] reg_r30;`
99			`reg [31:0] reg_r31;`
100
101			`//-----------------------------------------------------------------`
102			`// Register File (for simulation)`
103			`//-----------------------------------------------------------------`
104
105			`// Synchronous register write back`
106			`always @ (posedge clk_i or posedge rst_i)`
107			`begin`
108			`if (rst_i)`
109			`begin`
110	37	ultra_embe	`reg_r1_sp <= 32'h00000000;`
111			`reg_r2_fp <= 32'h00000000;`
112			`reg_r3 <= 32'h00000000;`
113			`reg_r4 <= 32'h00000000;`
114			`reg_r5 <= 32'h00000000;`
115			`reg_r6 <= 32'h00000000;`
116			`reg_r7 <= 32'h00000000;`
117			`reg_r8 <= 32'h00000000;`
118			`reg_r9_lr <= 32'h00000000;`
119			`reg_r10 <= 32'h00000000;`
120			`reg_r11 <= 32'h00000000;`
121			`reg_r12 <= 32'h00000000;`
122			`reg_r13 <= 32'h00000000;`
123			`reg_r14 <= 32'h00000000;`
124			`reg_r15 <= 32'h00000000;`
125			`reg_r16 <= 32'h00000000;`
126			`reg_r17 <= 32'h00000000;`
127			`reg_r18 <= 32'h00000000;`
128			`reg_r19 <= 32'h00000000;`
129			`reg_r20 <= 32'h00000000;`
130			`reg_r21 <= 32'h00000000;`
131			`reg_r22 <= 32'h00000000;`
132			`reg_r23 <= 32'h00000000;`
133			`reg_r24 <= 32'h00000000;`
134			`reg_r25 <= 32'h00000000;`
135			`reg_r26 <= 32'h00000000;`
136			`reg_r27 <= 32'h00000000;`
137			`reg_r28 <= 32'h00000000;`
138			`reg_r29 <= 32'h00000000;`
139			`reg_r30 <= 32'h00000000;`
140			`reg_r31 <= 32'h00000000;`
141	34	ultra_embe	`end`
142			`else`
143			`begin`
144			`if (wr_i == 1'b1)`
145			`case (rd_i[4:0])`
146			`5'b00001 :`
147			`reg_r1_sp <= reg_rd_i;`
148			`5'b00010 :`
149			`reg_r2_fp <= reg_rd_i;`
150			`5'b00011 :`
151			`reg_r3 <= reg_rd_i;`
152			`5'b00100 :`
153			`reg_r4 <= reg_rd_i;`
154			`5'b00101 :`
155			`reg_r5 <= reg_rd_i;`
156			`5'b00110 :`
157			`reg_r6 <= reg_rd_i;`
158			`5'b00111 :`
159			`reg_r7 <= reg_rd_i;`
160			`5'b01000 :`
161			`reg_r8 <= reg_rd_i;`
162			`5'b01001 :`
163			`reg_r9_lr <= reg_rd_i;`
164			`5'b01010 :`
165			`reg_r10 <= reg_rd_i;`
166			`5'b01011 :`
167			`reg_r11 <= reg_rd_i;`
168			`5'b01100 :`
169			`reg_r12 <= reg_rd_i;`
170			`5'b01101 :`
171			`reg_r13 <= reg_rd_i;`
172			`5'b01110 :`
173			`reg_r14 <= reg_rd_i;`
174			`5'b01111 :`
175			`reg_r15 <= reg_rd_i;`
176			`5'b10000 :`
177			`reg_r16 <= reg_rd_i;`
178			`5'b10001 :`
179			`reg_r17 <= reg_rd_i;`
180			`5'b10010 :`
181			`reg_r18 <= reg_rd_i;`
182			`5'b10011 :`
183			`reg_r19 <= reg_rd_i;`
184			`5'b10100 :`
185			`reg_r20 <= reg_rd_i;`
186			`5'b10101 :`
187			`reg_r21 <= reg_rd_i;`
188			`5'b10110 :`
189			`reg_r22 <= reg_rd_i;`
190			`5'b10111 :`
191			`reg_r23 <= reg_rd_i;`
192			`5'b11000 :`
193			`reg_r24 <= reg_rd_i;`
194			`5'b11001 :`
195			`reg_r25 <= reg_rd_i;`
196			`5'b11010 :`
197			`reg_r26 <= reg_rd_i;`
198			`5'b11011 :`
199			`reg_r27 <= reg_rd_i;`
200			`5'b11100 :`
201			`reg_r28 <= reg_rd_i;`
202			`5'b11101 :`
203			`reg_r29 <= reg_rd_i;`
204			`5'b11110 :`
205			`reg_r30 <= reg_rd_i;`
206			`5'b11111 :`
207			`reg_r31 <= reg_rd_i;`
208			`default :`
209			`;`
210			`endcase`
211			`end`
212			`end`
213
214			`generate`
215			`if (SUPPORT_32REGS == "ENABLED")`
216			`begin`
217			`// Asynchronous Register read (Rs & Rd)`
218			`always @ *`
219			`begin`
220	37	ultra_embe	`case (ra_i)`
221	34	ultra_embe	`5'b00000 :`
222	37	ultra_embe	`reg_ra_o = 32'h00000000;`
223	34	ultra_embe	`5'b00001 :`
224	37	ultra_embe	`reg_ra_o = reg_r1_sp;`
225	34	ultra_embe	`5'b00010 :`
226	37	ultra_embe	`reg_ra_o = reg_r2_fp;`
227	34	ultra_embe	`5'b00011 :`
228	37	ultra_embe	`reg_ra_o = reg_r3;`
229	34	ultra_embe	`5'b00100 :`
230	37	ultra_embe	`reg_ra_o = reg_r4;`
231	34	ultra_embe	`5'b00101 :`
232	37	ultra_embe	`reg_ra_o = reg_r5;`
233	34	ultra_embe	`5'b00110 :`
234	37	ultra_embe	`reg_ra_o = reg_r6;`
235	34	ultra_embe	`5'b00111 :`
236	37	ultra_embe	`reg_ra_o = reg_r7;`
237	34	ultra_embe	`5'b01000 :`
238	37	ultra_embe	`reg_ra_o = reg_r8;`
239	34	ultra_embe	`5'b01001 :`
240	37	ultra_embe	`reg_ra_o = reg_r9_lr;`
241	34	ultra_embe	`5'b01010 :`
242	37	ultra_embe	`reg_ra_o = reg_r10;`
243	34	ultra_embe	`5'b01011 :`
244	37	ultra_embe	`reg_ra_o = reg_r11;`
245	34	ultra_embe	`5'b01100 :`
246	37	ultra_embe	`reg_ra_o = reg_r12;`
247	34	ultra_embe	`5'b01101 :`
248	37	ultra_embe	`reg_ra_o = reg_r13;`
249	34	ultra_embe	`5'b01110 :`
250	37	ultra_embe	`reg_ra_o = reg_r14;`
251	34	ultra_embe	`5'b01111 :`
252	37	ultra_embe	`reg_ra_o = reg_r15;`
253	34	ultra_embe	`5'b10000 :`
254	37	ultra_embe	`reg_ra_o = reg_r16;`
255	34	ultra_embe	`5'b10001 :`
256	37	ultra_embe	`reg_ra_o = reg_r17;`
257	34	ultra_embe	`5'b10010 :`
258	37	ultra_embe	`reg_ra_o = reg_r18;`
259	34	ultra_embe	`5'b10011 :`
260	37	ultra_embe	`reg_ra_o = reg_r19;`
261	34	ultra_embe	`5'b10100 :`
262	37	ultra_embe	`reg_ra_o = reg_r20;`
263	34	ultra_embe	`5'b10101 :`
264	37	ultra_embe	`reg_ra_o = reg_r21;`
265	34	ultra_embe	`5'b10110 :`
266	37	ultra_embe	`reg_ra_o = reg_r22;`
267	34	ultra_embe	`5'b10111 :`
268	37	ultra_embe	`reg_ra_o = reg_r23;`
269	34	ultra_embe	`5'b11000 :`
270	37	ultra_embe	`reg_ra_o = reg_r24;`
271	34	ultra_embe	`5'b11001 :`
272	37	ultra_embe	`reg_ra_o = reg_r25;`
273	34	ultra_embe	`5'b11010 :`
274	37	ultra_embe	`reg_ra_o = reg_r26;`
275	34	ultra_embe	`5'b11011 :`
276	37	ultra_embe	`reg_ra_o = reg_r27;`
277	34	ultra_embe	`5'b11100 :`
278	37	ultra_embe	`reg_ra_o = reg_r28;`
279	34	ultra_embe	`5'b11101 :`
280	37	ultra_embe	`reg_ra_o = reg_r29;`
281	34	ultra_embe	`5'b11110 :`
282	37	ultra_embe	`reg_ra_o = reg_r30;`
283	34	ultra_embe	`5'b11111 :`
284	37	ultra_embe	`reg_ra_o = reg_r31;`
285	34	ultra_embe	`default :`
286	37	ultra_embe	`reg_ra_o = 32'h00000000;`
287	34	ultra_embe	`endcase`
288
289	37	ultra_embe	`case (rb_i)`
290	34	ultra_embe	`5'b00000 :`
291	37	ultra_embe	`reg_rb_o = 32'h00000000;`
292	34	ultra_embe	`5'b00001 :`
293	37	ultra_embe	`reg_rb_o = reg_r1_sp;`
294	34	ultra_embe	`5'b00010 :`
295	37	ultra_embe	`reg_rb_o = reg_r2_fp;`
296	34	ultra_embe	`5'b00011 :`
297	37	ultra_embe	`reg_rb_o = reg_r3;`
298	34	ultra_embe	`5'b00100 :`
299	37	ultra_embe	`reg_rb_o = reg_r4;`
300	34	ultra_embe	`5'b00101 :`
301	37	ultra_embe	`reg_rb_o = reg_r5;`
302	34	ultra_embe	`5'b00110 :`
303	37	ultra_embe	`reg_rb_o = reg_r6;`
304	34	ultra_embe	`5'b00111 :`
305	37	ultra_embe	`reg_rb_o = reg_r7;`
306	34	ultra_embe	`5'b01000 :`
307	37	ultra_embe	`reg_rb_o = reg_r8;`
308	34	ultra_embe	`5'b01001 :`
309	37	ultra_embe	`reg_rb_o = reg_r9_lr;`
310	34	ultra_embe	`5'b01010 :`
311	37	ultra_embe	`reg_rb_o = reg_r10;`
312	34	ultra_embe	`5'b01011 :`
313	37	ultra_embe	`reg_rb_o = reg_r11;`
314	34	ultra_embe	`5'b01100 :`
315	37	ultra_embe	`reg_rb_o = reg_r12;`
316	34	ultra_embe	`5'b01101 :`
317	37	ultra_embe	`reg_rb_o = reg_r13;`
318	34	ultra_embe	`5'b01110 :`
319	37	ultra_embe	`reg_rb_o = reg_r14;`
320	34	ultra_embe	`5'b01111 :`
321	37	ultra_embe	`reg_rb_o = reg_r15;`
322	34	ultra_embe	`5'b10000 :`
323	37	ultra_embe	`reg_rb_o = reg_r16;`
324	34	ultra_embe	`5'b10001 :`
325	37	ultra_embe	`reg_rb_o = reg_r17;`
326	34	ultra_embe	`5'b10010 :`
327	37	ultra_embe	`reg_rb_o = reg_r18;`
328	34	ultra_embe	`5'b10011 :`
329	37	ultra_embe	`reg_rb_o = reg_r19;`
330	34	ultra_embe	`5'b10100 :`
331	37	ultra_embe	`reg_rb_o = reg_r20;`
332	34	ultra_embe	`5'b10101 :`
333	37	ultra_embe	`reg_rb_o = reg_r21;`
334	34	ultra_embe	`5'b10110 :`
335	37	ultra_embe	`reg_rb_o = reg_r22;`
336	34	ultra_embe	`5'b10111 :`
337	37	ultra_embe	`reg_rb_o = reg_r23;`
338	34	ultra_embe	`5'b11000 :`
339	37	ultra_embe	`reg_rb_o = reg_r24;`
340	34	ultra_embe	`5'b11001 :`
341	37	ultra_embe	`reg_rb_o = reg_r25;`
342	34	ultra_embe	`5'b11010 :`
343	37	ultra_embe	`reg_rb_o = reg_r26;`
344	34	ultra_embe	`5'b11011 :`
345	37	ultra_embe	`reg_rb_o = reg_r27;`
346	34	ultra_embe	`5'b11100 :`
347	37	ultra_embe	`reg_rb_o = reg_r28;`
348	34	ultra_embe	`5'b11101 :`
349	37	ultra_embe	`reg_rb_o = reg_r29;`
350	34	ultra_embe	`5'b11110 :`
351	37	ultra_embe	`reg_rb_o = reg_r30;`
352	34	ultra_embe	`5'b11111 :`
353	37	ultra_embe	`reg_rb_o = reg_r31;`
354	34	ultra_embe	`default :`
355	37	ultra_embe	`reg_rb_o = 32'h00000000;`
356	34	ultra_embe	`endcase`
357			`end`
358			`end`
359			`else`
360			`begin`
361			`// Asynchronous Register read (Rs & Rd)`
362			`always @ *`
363			`begin`
364	37	ultra_embe	`case (ra_i)`
365	34	ultra_embe	`5'b00000 :`
366	37	ultra_embe	`reg_ra_o = 32'h00000000;`
367	34	ultra_embe	`5'b00001 :`
368	37	ultra_embe	`reg_ra_o = reg_r1_sp;`
369	34	ultra_embe	`5'b00010 :`
370	37	ultra_embe	`reg_ra_o = reg_r2_fp;`
371	34	ultra_embe	`5'b00011 :`
372	37	ultra_embe	`reg_ra_o = reg_r3;`
373	34	ultra_embe	`5'b00100 :`
374	37	ultra_embe	`reg_ra_o = reg_r4;`
375	34	ultra_embe	`5'b00101 :`
376	37	ultra_embe	`reg_ra_o = reg_r5;`
377	34	ultra_embe	`5'b00110 :`
378	37	ultra_embe	`reg_ra_o = reg_r6;`
379	34	ultra_embe	`5'b00111 :`
380	37	ultra_embe	`reg_ra_o = reg_r7;`
381	34	ultra_embe	`5'b01000 :`
382	37	ultra_embe	`reg_ra_o = reg_r8;`
383	34	ultra_embe	`5'b01001 :`
384	37	ultra_embe	`reg_ra_o = reg_r9_lr;`
385	34	ultra_embe	`5'b01010 :`
386	37	ultra_embe	`reg_ra_o = reg_r10;`
387	34	ultra_embe	`5'b01011 :`
388	37	ultra_embe	`reg_ra_o = reg_r11;`
389	34	ultra_embe	`5'b01100 :`
390	37	ultra_embe	`reg_ra_o = reg_r12;`
391	34	ultra_embe	`5'b01101 :`
392	37	ultra_embe	`reg_ra_o = reg_r13;`
393	34	ultra_embe	`5'b01110 :`
394	37	ultra_embe	`reg_ra_o = reg_r14;`
395	34	ultra_embe	`5'b01111 :`
396	37	ultra_embe	`reg_ra_o = reg_r15;`
397	34	ultra_embe	`default :`
398	37	ultra_embe	`reg_ra_o = 32'h00000000;`
399	34	ultra_embe	`endcase`
400
401	37	ultra_embe	`case (rb_i)`
402	34	ultra_embe	`5'b00000 :`
403	37	ultra_embe	`reg_rb_o = 32'h00000000;`
404	34	ultra_embe	`5'b00001 :`
405	37	ultra_embe	`reg_rb_o = reg_r1_sp;`
406	34	ultra_embe	`5'b00010 :`
407	37	ultra_embe	`reg_rb_o = reg_r2_fp;`
408	34	ultra_embe	`5'b00011 :`
409	37	ultra_embe	`reg_rb_o = reg_r3;`
410	34	ultra_embe	`5'b00100 :`
411	37	ultra_embe	`reg_rb_o = reg_r4;`
412	34	ultra_embe	`5'b00101 :`
413	37	ultra_embe	`reg_rb_o = reg_r5;`
414	34	ultra_embe	`5'b00110 :`
415	37	ultra_embe	`reg_rb_o = reg_r6;`
416	34	ultra_embe	`5'b00111 :`
417	37	ultra_embe	`reg_rb_o = reg_r7;`
418	34	ultra_embe	`5'b01000 :`
419	37	ultra_embe	`reg_rb_o = reg_r8;`
420	34	ultra_embe	`5'b01001 :`
421	37	ultra_embe	`reg_rb_o = reg_r9_lr;`
422	34	ultra_embe	`5'b01010 :`
423	37	ultra_embe	`reg_rb_o = reg_r10;`
424	34	ultra_embe	`5'b01011 :`
425	37	ultra_embe	`reg_rb_o = reg_r11;`
426	34	ultra_embe	`5'b01100 :`
427	37	ultra_embe	`reg_rb_o = reg_r12;`
428	34	ultra_embe	`5'b01101 :`
429	37	ultra_embe	`reg_rb_o = reg_r13;`
430	34	ultra_embe	`5'b01110 :`
431	37	ultra_embe	`reg_rb_o = reg_r14;`
432	34	ultra_embe	`5'b01111 :`
433	37	ultra_embe	`reg_rb_o = reg_r15;`
434	34	ultra_embe	`default :`
435	37	ultra_embe	`reg_rb_o = 32'h00000000;`
436	34	ultra_embe	`endcase`
437			`end`
438			`end`
439			`endgenerate`
440
441			`endmodule`

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