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URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

[/] [altor32/] [trunk/] [rtl/] [sim/] [makefile] - Blame information for rev 29

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Line No. Rev Author Line
1 27 ultra_embe
 
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# Default binary to load & run
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TEST_IMAGE  ?= test_image.bin
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SIMARGS     ?=
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CYCLES      ?= -1
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STOP_AT     ?= 0xFFFFFFFF
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# Default core to simulate
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RTL_CORE      ?= cpu
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CORE_FILENAME ?= altor32.v
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# Waveform trace disabled by default
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TRACE?= 0
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# Enable debug output
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DEBUG?= 0
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# Enable instruction trace
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INST_TRACE?= 0
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# Top module (without .v extension)
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TOP_MODULE = top
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# Additional modules which can't be auto found
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ADDITIONAL_MODULES = ../$(RTL_CORE)/$(CORE_FILENAME)
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# CPP Source Files
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SRC_CPP = main.cpp top.cpp
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# Source directories
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INC_DIRS = -I../$(RTL_CORE) -I../soc -I../peripheral
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# Build directory
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BUILD_DIR = build
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VERILATOR_OPTS =
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ifeq ($(TRACE),1)
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    VERILATOR_OPTS += --trace
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endif
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ifeq ($(DEBUG),1)
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    VERILATOR_OPTS += +define+CONF_CORE_DEBUG+
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endif
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ifeq ($(INST_TRACE),1)
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    VERILATOR_OPTS += -CFLAGS "-DINST_TRACE"
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endif
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VERILATOR_OPTS += +define+SIMULATION+
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all: run
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compile: clean
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        verilator --cc $(TOP_MODULE).v $(ADDITIONAL_MODULES) $(SRC_CPP) $(INC_DIRS) +define+CONF_TARGET_SIM+ --exe -Mdir $(BUILD_DIR) $(VERILATOR_OPTS)
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        make -j -f V$(TOP_MODULE).mk -C $(BUILD_DIR)
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run: compile
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        ./$(BUILD_DIR)/V$(TOP_MODULE) -b $(STOP_AT) -c $(CYCLES) -f $(TEST_IMAGE) $(SIMARGS)
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ifeq ($(TRACE),1)
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view:
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        gtkwave wave_dump.vcd gtksettings.sav
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endif
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clean :
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        -rm -rf $(BUILD_DIR) wave_dump.vcd

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