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dragos_don |
/////////////////////////////////////////////////////////////////////
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//// ////
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//// This project has been provided to you on behalf of: ////
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//// ////
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//// S.C. ASICArt S.R.L. ////
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//// www.asicart.com ////
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//// eli_f@asicart.com ////
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//// ////
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//// Author: Dragos Constantin Doncean ////
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//// Email: doncean@asicart.com ////
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//// Mobile: +40-740-936997 ////
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//// ////
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//// Downloaded from: http://www.opencores.org/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2007 Dragos Constantin Doncean ////
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//// www.asicart.com ////
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//// doncean@asicart.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//TEST MODULE - IMPROVED TEST
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module proj_improved_test;
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wire test_clk, test_res, test_stb;
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wire [1:0] test_sel;
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wire [7:0] test_data_in_0, test_data_in_1, test_data_in_2;
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wire test_data_valid_in;
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wire test_valid_0, test_valid_1;
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wire [15:0] test_out_0, test_out_1;
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wire test_parity_0, test_parity_1;
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wire [7:0] test_ic_data_0, test_ic_data_1, test_ic_data_2, test_ic_data_3;
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wire [15:0] test_oc_data;
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wire test_oc_parity;
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wire [0:127] test_ic_data_collected, test_oc_data_collected;
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//DUT instantiation
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DUT dut(.dut_clk(test_clk), .dut_res(test_res), .dut_stb(test_stb),
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.dut_sel(test_sel),
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.dut_data_in_0(test_data_in_0), .dut_data_in_1(test_data_in_1), .dut_data_in_2(test_data_in_2),
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.dut_data_valid_in(test_data_valid_in),
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.dut_valid_0(test_valid_0), .dut_valid_1(test_valid_1),
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.dut_out_0(test_out_0), .dut_out_1(test_out_1),
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.dut_parity_0(test_parity_0), .dut_parity_1(test_parity_1));
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//DUT VERIFICATION ENVIRONMENT
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//Contains CLK generator, monitors, BFMs, collectors and the checker
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//They are instantiated here, in the test module
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//--------BFMs' instantiations--------
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CLK_GEN clk_gen(.gen_clk(test_clk));
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RES_BFM res_bfm(.bfm_res(test_res));
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DATA_IN_BFM data_in_bfm(.bfm_stb(test_stb),
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.bfm_sel(test_sel),
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.bfm_data_in_0(test_data_in_0), .bfm_data_in_1(test_data_in_1), .bfm_data_in_2(test_data_in_2),
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.bfm_data_valid_in(test_data_valid_in));
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//--------Monitors' instantiations--------
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CLK_MONITOR clk_monitor(.m_clk(test_clk));
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RES_MONITOR res_monitor(.m_res(test_res));
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STB_MONITOR stb_monitor(.m_clk(test_clk), .m_stb(test_stb));
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SEL_MONITOR sel_monitor(.m_clk(test_clk), .m_stb(test_stb), .m_sel(test_sel));
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DATA_IN_MONITOR data_in_monitor(.m_clk(test_clk), .m_stb(test_stb),
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.m_data_in_0(test_data_in_0), .m_data_in_1(test_data_in_1), .m_data_in_2(test_data_in_2));
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DATA_VALID_IN_MONITOR data_valid_in_monitor(.m_clk(test_clk), .m_stb(test_stb),
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.m_data_valid_in(test_data_valid_in));
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VALID_MONITOR valid_monitor(.m_clk(test_clk), .m_res(test_res),
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.m_valid_0(test_valid_0), .m_valid_1(test_valid_1));
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DATA_OUT_MONITOR data_out_monitor(.m_clk(test_clk), .m_res(test_res),
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.m_out_0(test_out_0), .m_out_1(test_out_1));
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PARITY_MONITOR parity_monitor(.m_clk(test_clk), .m_res(test_res),
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.m_parity_0(test_parity_0), .m_parity_1(test_parity_1));
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//--------Collectors' instantiations--------
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INPUT_COLLECTOR input_collector(.ic_clk(test_clk), .ic_res(test_res), .ic_stb(test_stb),
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.ic_sel(test_sel),
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.ic_data_in_0(test_data_in_0), .ic_data_in_1(test_data_in_1), .ic_data_in_2(test_data_in_2),
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.ic_data_valid_in(test_data_valid_in),
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.ic_data_out_0(test_ic_data_0), .ic_data_out_1(test_ic_data_1), .ic_data_out_2(test_ic_data_2), .ic_data_out_3(test_ic_data_3),
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.ic_data_collected(test_ic_data_collected));
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OUTPUT_COLLECTOR output_collector(.oc_clk(test_clk), .oc_res(test_res),
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.oc_valid_0(test_valid_0), .oc_valid_1(test_valid_1),
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.oc_out_0(test_out_0), .oc_out_1(test_out_1),
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.oc_parity_0(test_parity_0), .oc_parity_1(test_parity_1),
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.oc_data(test_oc_data),
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.oc_parity(test_oc_parity),
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.oc_data_collected(test_oc_data_collected));
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//--------Checker's instantiation--------
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CHECKER checker(.c_clk(test_clk), .c_res(test_res),
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.ic_data_0(test_ic_data_0), .ic_data_1(test_ic_data_1), .ic_data_2(test_ic_data_2), .ic_data_3(test_ic_data_3),
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.oc_data(test_oc_data),
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.oc_parity(test_oc_parity),
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.ic_data_collected(test_ic_data_collected),
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.oc_data_collected(test_oc_data_collected));
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//Waveform database
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initial
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begin
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$shm_open("../run/waves/waves_improved_test"); // Open database named "waves"
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$shm_probe(proj_improved_test, "AS"); // Record tb scope and all sub hierarchy
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end
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/*
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//for waveform viewing with GTKWave
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initial
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begin
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$dumpfile ("proj0.dump") ;
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$dumpvars;
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$dumpon;
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//$dumpall;
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end
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*/
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endmodule
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